drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/delay.h>
  23
  24 #include "internal.h"
  25
  26 ACPI_MODULE_NAME("acpi_lpss");
  27
  28 #ifdef CONFIG_X86_INTEL_LPSS
  29
  30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  31
  32 #define LPSS_CLK_SIZE   0x04
  33 #define LPSS_LTR_SIZE   0x18
  34
  35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  36 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  37 #define LPSS_GENERAL                    0x08
  38 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  39 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  40 #define LPSS_SW_LTR                     0x10
  41 #define LPSS_AUTO_LTR                   0x14
  42 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  43 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  44 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  45 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  46 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  47 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  48 #define LPSS_LTR_MAX_VAL                0x3FF
  49 #define LPSS_TX_INT                     0x20
  50 #define LPSS_TX_INT_MASK                BIT(1)
  51
  52 #define LPSS_PRV_REG_COUNT              9
  53
  54 struct lpss_shared_clock {
  55         const char *name;
  56         unsigned long rate;
  57         struct clk *clk;
  58 };
  59
  60 struct lpss_private_data;
  61
  62 struct lpss_device_desc {
  63         bool clk_required;
  64         const char *clkdev_name;
  65         bool ltr_required;
  66         unsigned int prv_offset;
  67         size_t prv_size_override;
  68         bool clk_divider;
  69         bool clk_gate;
  70         bool save_ctx;
  71         struct lpss_shared_clock *shared_clock;
  72         void (*setup)(struct lpss_private_data *pdata);
  73 };
  74
  75 static struct lpss_device_desc lpss_dma_desc = {
  76         .clk_required = true,
  77         .clkdev_name = "hclk",
  78 };
  79
  80 struct lpss_private_data {
  81         void __iomem *mmio_base;
  82         resource_size_t mmio_size;
  83         struct clk *clk;
  84         const struct lpss_device_desc *dev_desc;
  85         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  86 };
  87
  88 static void lpss_uart_setup(struct lpss_private_data *pdata)
  89 {
  90         unsigned int offset;
  91         u32 reg;
  92
  93         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
  94         reg = readl(pdata->mmio_base + offset);
  95         writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
  96
  97         offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
  98         reg = readl(pdata->mmio_base + offset);
  99         writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset);
 100 }
 101
 102 static struct lpss_device_desc lpt_dev_desc = {
 103         .clk_required = true,
 104         .prv_offset = 0x800,
 105         .ltr_required = true,
 106         .clk_divider = true,
 107         .clk_gate = true,
 108 };
 109
 110 static struct lpss_device_desc lpt_i2c_dev_desc = {
 111         .clk_required = true,
 112         .prv_offset = 0x800,
 113         .ltr_required = true,
 114         .clk_gate = true,
 115 };
 116
 117 static struct lpss_device_desc lpt_uart_dev_desc = {
 118         .clk_required = true,
 119         .prv_offset = 0x800,
 120         .ltr_required = true,
 121         .clk_divider = true,
 122         .clk_gate = true,
 123         .setup = lpss_uart_setup,
 124 };
 125
 126 static struct lpss_device_desc lpt_sdio_dev_desc = {
 127         .prv_offset = 0x1000,
 128         .prv_size_override = 0x1018,
 129         .ltr_required = true,
 130 };
 131
 132 static struct lpss_shared_clock pwm_clock = {
 133         .name = "pwm_clk",
 134         .rate = 25000000,
 135 };
 136
 137 static struct lpss_device_desc byt_pwm_dev_desc = {
 138         .clk_required = true,
 139         .save_ctx = true,
 140         .shared_clock = &pwm_clock,
 141 };
 142
 143 static struct lpss_device_desc byt_uart_dev_desc = {
 144         .clk_required = true,
 145         .prv_offset = 0x800,
 146         .clk_divider = true,
 147         .clk_gate = true,
 148         .save_ctx = true,
 149         .setup = lpss_uart_setup,
 150 };
 151
 152 static struct lpss_device_desc byt_spi_dev_desc = {
 153         .clk_required = true,
 154         .prv_offset = 0x400,
 155         .clk_divider = true,
 156         .clk_gate = true,
 157         .save_ctx = true,
 158 };
 159
 160 static struct lpss_device_desc byt_sdio_dev_desc = {
 161         .clk_required = true,
 162 };
 163
 164 static struct lpss_shared_clock i2c_clock = {
 165         .name = "i2c_clk",
 166         .rate = 100000000,
 167 };
 168
 169 static struct lpss_device_desc byt_i2c_dev_desc = {
 170         .clk_required = true,
 171         .prv_offset = 0x800,
 172         .save_ctx = true,
 173         .shared_clock = &i2c_clock,
 174 };
 175
 176 #else
 177
 178 #define LPSS_ADDR(desc) (0UL)
 179
 180 #endif /* CONFIG_X86_INTEL_LPSS */
 181
 182 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 183         /* Generic LPSS devices */
 184         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 185
 186         /* Lynxpoint LPSS devices */
 187         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 188         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 189         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 190         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 191         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 192         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 193         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 194         { "INT33C7", },
 195
 196         /* BayTrail LPSS devices */
 197         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 198         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 199         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 200         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 201         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 202         { "INT33B2", },
 203
 204         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 205         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 206         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 207         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 208         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 209         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 210         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 211         { "INT3437", },
 212
 213         { }
 214 };
 215
 216 #ifdef CONFIG_X86_INTEL_LPSS
 217
 218 static int is_memory(struct acpi_resource *res, void *not_used)
 219 {
 220         struct resource r;
 221         return !acpi_dev_resource_memory(res, &r);
 222 }
 223
 224 /* LPSS main clock device. */
 225 static struct platform_device *lpss_clk_dev;
 226
 227 static inline void lpt_register_clock_device(void)
 228 {
 229         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 230 }
 231
 232 static int register_device_clock(struct acpi_device *adev,
 233                                  struct lpss_private_data *pdata)
 234 {
 235         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 236         struct lpss_shared_clock *shared_clock = dev_desc->shared_clock;
 237         const char *devname = dev_name(&adev->dev);
 238         struct clk *clk = ERR_PTR(-ENODEV);
 239         struct lpss_clk_data *clk_data;
 240         const char *parent, *clk_name;
 241         void __iomem *prv_base;
 242
 243         if (!lpss_clk_dev)
 244                 lpt_register_clock_device();
 245
 246         clk_data = platform_get_drvdata(lpss_clk_dev);
 247         if (!clk_data)
 248                 return -ENODEV;
 249
 250         if (dev_desc->clkdev_name) {
 251                 clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name,
 252                                     devname);
 253                 return 0;
 254         }
 255
 256         if (!pdata->mmio_base
 257             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 258                 return -ENODATA;
 259
 260         parent = clk_data->name;
 261         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 262
 263         if (shared_clock) {
 264                 clk = shared_clock->clk;
 265                 if (!clk) {
 266                         clk = clk_register_fixed_rate(NULL, shared_clock->name,
 267                                                       "lpss_clk", 0,
 268                                                       shared_clock->rate);
 269                         shared_clock->clk = clk;
 270                 }
 271                 parent = shared_clock->name;
 272         }
 273
 274         if (dev_desc->clk_gate) {
 275                 clk = clk_register_gate(NULL, devname, parent, 0,
 276                                         prv_base, 0, 0, NULL);
 277                 parent = devname;
 278         }
 279
 280         if (dev_desc->clk_divider) {
 281                 /* Prevent division by zero */
 282                 if (!readl(prv_base))
 283                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 284
 285                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 286                 if (!clk_name)
 287                         return -ENOMEM;
 288                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 289                                                       0, prv_base,
 290                                                       1, 15, 16, 15, 0, NULL);
 291                 parent = clk_name;
 292
 293                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 294                 if (!clk_name) {
 295                         kfree(parent);
 296                         return -ENOMEM;
 297                 }
 298                 clk = clk_register_gate(NULL, clk_name, parent,
 299                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 300                                         prv_base, 31, 0, NULL);
 301                 kfree(parent);
 302                 kfree(clk_name);
 303         }
 304
 305         if (IS_ERR(clk))
 306                 return PTR_ERR(clk);
 307
 308         pdata->clk = clk;
 309         clk_register_clkdev(clk, NULL, devname);
 310         return 0;
 311 }
 312
 313 static int acpi_lpss_create_device(struct acpi_device *adev,
 314                                    const struct acpi_device_id *id)
 315 {
 316         struct lpss_device_desc *dev_desc;
 317         struct lpss_private_data *pdata;
 318         struct resource_list_entry *rentry;
 319         struct list_head resource_list;
 320         struct platform_device *pdev;
 321         int ret;
 322
 323         dev_desc = (struct lpss_device_desc *)id->driver_data;
 324         if (!dev_desc) {
 325                 pdev = acpi_create_platform_device(adev);
 326                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 327         }
 328         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 329         if (!pdata)
 330                 return -ENOMEM;
 331
 332         INIT_LIST_HEAD(&resource_list);
 333         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 334         if (ret < 0)
 335                 goto err_out;
 336
 337         list_for_each_entry(rentry, &resource_list, node)
 338                 if (resource_type(&rentry->res) == IORESOURCE_MEM) {
 339                         if (dev_desc->prv_size_override)
 340                                 pdata->mmio_size = dev_desc->prv_size_override;
 341                         else
 342                                 pdata->mmio_size = resource_size(&rentry->res);
 343                         pdata->mmio_base = ioremap(rentry->res.start,
 344                                                    pdata->mmio_size);
 345                         break;
 346                 }
 347
 348         acpi_dev_free_resource_list(&resource_list);
 349
 350         pdata->dev_desc = dev_desc;
 351
 352         if (dev_desc->clk_required) {
 353                 ret = register_device_clock(adev, pdata);
 354                 if (ret) {
 355                         /* Skip the device, but continue the namespace scan. */
 356                         ret = 0;
 357                         goto err_out;
 358                 }
 359         }
 360
 361         /*
 362          * This works around a known issue in ACPI tables where LPSS devices
 363          * have _PS0 and _PS3 without _PSC (and no power resources), so
 364          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 365          */
 366         ret = acpi_device_fix_up_power(adev);
 367         if (ret) {
 368                 /* Skip the device, but continue the namespace scan. */
 369                 ret = 0;
 370                 goto err_out;
 371         }
 372
 373         if (dev_desc->setup)
 374                 dev_desc->setup(pdata);
 375
 376         adev->driver_data = pdata;
 377         pdev = acpi_create_platform_device(adev);
 378         if (!IS_ERR_OR_NULL(pdev)) {
 379                 device_enable_async_suspend(&pdev->dev);
 380                 return 1;
 381         }
 382
 383         ret = PTR_ERR(pdev);
 384         adev->driver_data = NULL;
 385
 386  err_out:
 387         kfree(pdata);
 388         return ret;
 389 }
 390
 391 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 392 {
 393         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 394 }
 395
 396 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 397                              unsigned int reg)
 398 {
 399         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 400 }
 401
 402 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 403 {
 404         struct acpi_device *adev;
 405         struct lpss_private_data *pdata;
 406         unsigned long flags;
 407         int ret;
 408
 409         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 410         if (WARN_ON(ret))
 411                 return ret;
 412
 413         spin_lock_irqsave(&dev->power.lock, flags);
 414         if (pm_runtime_suspended(dev)) {
 415                 ret = -EAGAIN;
 416                 goto out;
 417         }
 418         pdata = acpi_driver_data(adev);
 419         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 420                 ret = -ENODEV;
 421                 goto out;
 422         }
 423         *val = __lpss_reg_read(pdata, reg);
 424
 425  out:
 426         spin_unlock_irqrestore(&dev->power.lock, flags);
 427         return ret;
 428 }
 429
 430 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 431                              char *buf)
 432 {
 433         u32 ltr_value = 0;
 434         unsigned int reg;
 435         int ret;
 436
 437         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 438         ret = lpss_reg_read(dev, reg, &ltr_value);
 439         if (ret)
 440                 return ret;
 441
 442         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 443 }
 444
 445 static ssize_t lpss_ltr_mode_show(struct device *dev,
 446                                   struct device_attribute *attr, char *buf)
 447 {
 448         u32 ltr_mode = 0;
 449         char *outstr;
 450         int ret;
 451
 452         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 453         if (ret)
 454                 return ret;
 455
 456         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 457         return sprintf(buf, "%s\n", outstr);
 458 }
 459
 460 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 461 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 462 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 463
 464 static struct attribute *lpss_attrs[] = {
 465         &dev_attr_auto_ltr.attr,
 466         &dev_attr_sw_ltr.attr,
 467         &dev_attr_ltr_mode.attr,
 468         NULL,
 469 };
 470
 471 static struct attribute_group lpss_attr_group = {
 472         .attrs = lpss_attrs,
 473         .name = "lpss_ltr",
 474 };
 475
 476 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 477 {
 478         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 479         u32 ltr_mode, ltr_val;
 480
 481         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 482         if (val < 0) {
 483                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 484                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 485                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 486                 }
 487                 return;
 488         }
 489         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 490         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 491                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 492                 val = LPSS_LTR_MAX_VAL;
 493         } else if (val > LPSS_LTR_MAX_VAL) {
 494                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 495                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 496         } else {
 497                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 498         }
 499         ltr_val |= val;
 500         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 501         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 502                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 503                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 504         }
 505 }
 506
 507 #ifdef CONFIG_PM
 508 /**
 509  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 510  * @dev: LPSS device
 511  *
 512  * Most LPSS devices have private registers which may loose their context when
 513  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 514  * prv_reg_ctx array.
 515  */
 516 static void acpi_lpss_save_ctx(struct device *dev)
 517 {
 518         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 519         unsigned int i;
 520
 521         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 522                 unsigned long offset = i * sizeof(u32);
 523
 524                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 525                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 526                         pdata->prv_reg_ctx[i], offset);
 527         }
 528 }
 529
 530 /**
 531  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 532  * @dev: LPSS device
 533  *
 534  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 535  */
 536 static void acpi_lpss_restore_ctx(struct device *dev)
 537 {
 538         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 539         unsigned int i;
 540
 541         /*
 542          * The following delay is needed or the subsequent write operations may
 543          * fail. The LPSS devices are actually PCI devices and the PCI spec
 544          * expects 10ms delay before the device can be accessed after D3 to D0
 545          * transition.
 546          */
 547         msleep(10);
 548
 549         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 550                 unsigned long offset = i * sizeof(u32);
 551
 552                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 553                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 554                         pdata->prv_reg_ctx[i], offset);
 555         }
 556 }
 557
 558 #ifdef CONFIG_PM_SLEEP
 559 static int acpi_lpss_suspend_late(struct device *dev)
 560 {
 561         int ret = pm_generic_suspend_late(dev);
 562
 563         if (ret)
 564                 return ret;
 565
 566         acpi_lpss_save_ctx(dev);
 567         return acpi_dev_suspend_late(dev);
 568 }
 569
 570 static int acpi_lpss_restore_early(struct device *dev)
 571 {
 572         int ret = acpi_dev_resume_early(dev);
 573
 574         if (ret)
 575                 return ret;
 576
 577         acpi_lpss_restore_ctx(dev);
 578         return pm_generic_resume_early(dev);
 579 }
 580 #endif /* CONFIG_PM_SLEEP */
 581
 582 #ifdef CONFIG_PM_RUNTIME
 583 static int acpi_lpss_runtime_suspend(struct device *dev)
 584 {
 585         int ret = pm_generic_runtime_suspend(dev);
 586
 587         if (ret)
 588                 return ret;
 589
 590         acpi_lpss_save_ctx(dev);
 591         return acpi_dev_runtime_suspend(dev);
 592 }
 593
 594 static int acpi_lpss_runtime_resume(struct device *dev)
 595 {
 596         int ret = acpi_dev_runtime_resume(dev);
 597
 598         if (ret)
 599                 return ret;
 600
 601         acpi_lpss_restore_ctx(dev);
 602         return pm_generic_runtime_resume(dev);
 603 }
 604 #endif /* CONFIG_PM_RUNTIME */
 605 #endif /* CONFIG_PM */
 606
 607 static struct dev_pm_domain acpi_lpss_pm_domain = {
 608         .ops = {
 609 #ifdef CONFIG_PM_SLEEP
 610                 .suspend_late = acpi_lpss_suspend_late,
 611                 .restore_early = acpi_lpss_restore_early,
 612                 .prepare = acpi_subsys_prepare,
 613                 .complete = acpi_subsys_complete,
 614                 .suspend = acpi_subsys_suspend,
 615                 .resume_early = acpi_subsys_resume_early,
 616                 .freeze = acpi_subsys_freeze,
 617                 .poweroff = acpi_subsys_suspend,
 618                 .poweroff_late = acpi_subsys_suspend_late,
 619 #endif
 620 #ifdef CONFIG_PM_RUNTIME
 621                 .runtime_suspend = acpi_lpss_runtime_suspend,
 622                 .runtime_resume = acpi_lpss_runtime_resume,
 623 #endif
 624         },
 625 };
 626
 627 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 628                                      unsigned long action, void *data)
 629 {
 630         struct platform_device *pdev = to_platform_device(data);
 631         struct lpss_private_data *pdata;
 632         struct acpi_device *adev;
 633         const struct acpi_device_id *id;
 634
 635         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 636         if (!id || !id->driver_data)
 637                 return 0;
 638
 639         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 640                 return 0;
 641
 642         pdata = acpi_driver_data(adev);
 643         if (!pdata || !pdata->mmio_base)
 644                 return 0;
 645
 646         if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 647                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 648                 return 0;
 649         }
 650
 651         switch (action) {
 652         case BUS_NOTIFY_BOUND_DRIVER:
 653                 if (pdata->dev_desc->save_ctx)
 654                         pdev->dev.pm_domain = &acpi_lpss_pm_domain;
 655                 break;
 656         case BUS_NOTIFY_UNBOUND_DRIVER:
 657                 if (pdata->dev_desc->save_ctx)
 658                         pdev->dev.pm_domain = NULL;
 659                 break;
 660         case BUS_NOTIFY_ADD_DEVICE:
 661                 if (pdata->dev_desc->ltr_required)
 662                         return sysfs_create_group(&pdev->dev.kobj,
 663                                                   &lpss_attr_group);
 664         case BUS_NOTIFY_DEL_DEVICE:
 665                 if (pdata->dev_desc->ltr_required)
 666                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 667         default:
 668                 break;
 669         }
 670
 671         return 0;
 672 }
 673
 674 static struct notifier_block acpi_lpss_nb = {
 675         .notifier_call = acpi_lpss_platform_notify,
 676 };
 677
 678 static void acpi_lpss_bind(struct device *dev)
 679 {
 680         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 681
 682         if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required)
 683                 return;
 684
 685         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 686                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 687         else
 688                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 689 }
 690
 691 static void acpi_lpss_unbind(struct device *dev)
 692 {
 693         dev->power.set_latency_tolerance = NULL;
 694 }
 695
 696 static struct acpi_scan_handler lpss_handler = {
 697         .ids = acpi_lpss_device_ids,
 698         .attach = acpi_lpss_create_device,
 699         .bind = acpi_lpss_bind,
 700         .unbind = acpi_lpss_unbind,
 701 };
 702
 703 void __init acpi_lpss_init(void)
 704 {
 705         if (!lpt_clk_init()) {
 706                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 707                 acpi_scan_add_handler(&lpss_handler);
 708         }
 709 }
 710
 711 #else
 712
 713 static struct acpi_scan_handler lpss_handler = {
 714         .ids = acpi_lpss_device_ids,
 715 };
 716
 717 void __init acpi_lpss_init(void)
 718 {
 719         acpi_scan_add_handler(&lpss_handler);
 720 }
 721
 722 #endif /* CONFIG_X86_INTEL_LPSS */