drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/platform_data/clk-lpss.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/delay.h>
  22
  23 #include "internal.h"
  24
  25 ACPI_MODULE_NAME("acpi_lpss");
  26
  27 #ifdef CONFIG_X86_INTEL_LPSS
  28
  29 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  30
  31 #define LPSS_CLK_SIZE   0x04
  32 #define LPSS_LTR_SIZE   0x18
  33
  34 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  35 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  36 #define LPSS_RESETS                     0x04
  37 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  38 #define LPSS_RESETS_RESET_APB           BIT(1)
  39 #define LPSS_GENERAL                    0x08
  40 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  41 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  42 #define LPSS_SW_LTR                     0x10
  43 #define LPSS_AUTO_LTR                   0x14
  44 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  45 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  46 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  47 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  48 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  49 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  50 #define LPSS_LTR_MAX_VAL                0x3FF
  51 #define LPSS_TX_INT                     0x20
  52 #define LPSS_TX_INT_MASK                BIT(1)
  53
  54 #define LPSS_PRV_REG_COUNT              9
  55
  56 /* LPSS Flags */
  57 #define LPSS_CLK                        BIT(0)
  58 #define LPSS_CLK_GATE                   BIT(1)
  59 #define LPSS_CLK_DIVIDER                BIT(2)
  60 #define LPSS_LTR                        BIT(3)
  61 #define LPSS_SAVE_CTX                   BIT(4)
  62 #define LPSS_NO_D3_DELAY                BIT(5)
  63
  64 struct lpss_private_data;
  65
  66 struct lpss_device_desc {
  67         unsigned int flags;
  68         const char *clk_con_id;
  69         unsigned int prv_offset;
  70         size_t prv_size_override;
  71         void (*setup)(struct lpss_private_data *pdata);
  72 };
  73
  74 static struct lpss_device_desc lpss_dma_desc = {
  75         .flags = LPSS_CLK,
  76 };
  77
  78 struct lpss_private_data {
  79         void __iomem *mmio_base;
  80         resource_size_t mmio_size;
  81         unsigned int fixed_clk_rate;
  82         struct clk *clk;
  83         const struct lpss_device_desc *dev_desc;
  84         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  85 };
  86
  87 /* UART Component Parameter Register */
  88 #define LPSS_UART_CPR                   0xF4
  89 #define LPSS_UART_CPR_AFCE              BIT(4)
  90
  91 static void lpss_uart_setup(struct lpss_private_data *pdata)
  92 {
  93         unsigned int offset;
  94         u32 val;
  95
  96         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
  97         val = readl(pdata->mmio_base + offset);
  98         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
  99
 100         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 101         if (!(val & LPSS_UART_CPR_AFCE)) {
 102                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 103                 val = readl(pdata->mmio_base + offset);
 104                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 105                 writel(val, pdata->mmio_base + offset);
 106         }
 107 }
 108
 109 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 110 {
 111         unsigned int offset;
 112         u32 val;
 113
 114         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 115         val = readl(pdata->mmio_base + offset);
 116         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 117         writel(val, pdata->mmio_base + offset);
 118 }
 119
 120 #define LPSS_I2C_ENABLE                 0x6c
 121
 122 static void byt_i2c_setup(struct lpss_private_data *pdata)
 123 {
 124         lpss_deassert_reset(pdata);
 125
 126         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 127                 pdata->fixed_clk_rate = 133000000;
 128
 129         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 130 }
 131
 132 static const struct lpss_device_desc lpt_dev_desc = {
 133         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 134         .prv_offset = 0x800,
 135 };
 136
 137 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 138         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 139         .prv_offset = 0x800,
 140 };
 141
 142 static const struct lpss_device_desc lpt_uart_dev_desc = {
 143         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 144         .clk_con_id = "baudclk",
 145         .prv_offset = 0x800,
 146         .setup = lpss_uart_setup,
 147 };
 148
 149 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 150         .flags = LPSS_LTR,
 151         .prv_offset = 0x1000,
 152         .prv_size_override = 0x1018,
 153 };
 154
 155 static const struct lpss_device_desc byt_pwm_dev_desc = {
 156         .flags = LPSS_SAVE_CTX,
 157 };
 158
 159 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 160         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 161 };
 162
 163 static const struct lpss_device_desc byt_uart_dev_desc = {
 164         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 165         .clk_con_id = "baudclk",
 166         .prv_offset = 0x800,
 167         .setup = lpss_uart_setup,
 168 };
 169
 170 static const struct lpss_device_desc bsw_uart_dev_desc = {
 171         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 172                         | LPSS_NO_D3_DELAY,
 173         .clk_con_id = "baudclk",
 174         .prv_offset = 0x800,
 175         .setup = lpss_uart_setup,
 176 };
 177
 178 static const struct lpss_device_desc byt_spi_dev_desc = {
 179         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 180         .prv_offset = 0x400,
 181 };
 182
 183 static const struct lpss_device_desc byt_sdio_dev_desc = {
 184         .flags = LPSS_CLK,
 185 };
 186
 187 static const struct lpss_device_desc byt_i2c_dev_desc = {
 188         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 189         .prv_offset = 0x800,
 190         .setup = byt_i2c_setup,
 191 };
 192
 193 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 194         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 195         .prv_offset = 0x800,
 196         .setup = byt_i2c_setup,
 197 };
 198
 199 static struct lpss_device_desc bsw_spi_dev_desc = {
 200         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 201                         | LPSS_NO_D3_DELAY,
 202         .prv_offset = 0x400,
 203         .setup = lpss_deassert_reset,
 204 };
 205
 206 #else
 207
 208 #define LPSS_ADDR(desc) (0UL)
 209
 210 #endif /* CONFIG_X86_INTEL_LPSS */
 211
 212 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 213         /* Generic LPSS devices */
 214         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 215
 216         /* Lynxpoint LPSS devices */
 217         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 218         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 219         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 220         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 221         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 222         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 223         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 224         { "INT33C7", },
 225
 226         /* BayTrail LPSS devices */
 227         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 228         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 229         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 230         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 231         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 232         { "INT33B2", },
 233         { "INT33FC", },
 234
 235         /* Braswell LPSS devices */
 236         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 237         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 238         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 239         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 240
 241         /* Broadwell LPSS devices */
 242         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 243         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 244         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 245         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 246         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 247         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 248         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 249         { "INT3437", },
 250
 251         /* Wildcat Point LPSS devices */
 252         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 253
 254         { }
 255 };
 256
 257 #ifdef CONFIG_X86_INTEL_LPSS
 258
 259 static int is_memory(struct acpi_resource *res, void *not_used)
 260 {
 261         struct resource r;
 262         return !acpi_dev_resource_memory(res, &r);
 263 }
 264
 265 /* LPSS main clock device. */
 266 static struct platform_device *lpss_clk_dev;
 267
 268 static inline void lpt_register_clock_device(void)
 269 {
 270         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 271 }
 272
 273 static int register_device_clock(struct acpi_device *adev,
 274                                  struct lpss_private_data *pdata)
 275 {
 276         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 277         const char *devname = dev_name(&adev->dev);
 278         struct clk *clk = ERR_PTR(-ENODEV);
 279         struct lpss_clk_data *clk_data;
 280         const char *parent, *clk_name;
 281         void __iomem *prv_base;
 282
 283         if (!lpss_clk_dev)
 284                 lpt_register_clock_device();
 285
 286         clk_data = platform_get_drvdata(lpss_clk_dev);
 287         if (!clk_data)
 288                 return -ENODEV;
 289         clk = clk_data->clk;
 290
 291         if (!pdata->mmio_base
 292             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 293                 return -ENODATA;
 294
 295         parent = clk_data->name;
 296         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 297
 298         if (pdata->fixed_clk_rate) {
 299                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 300                                               pdata->fixed_clk_rate);
 301                 goto out;
 302         }
 303
 304         if (dev_desc->flags & LPSS_CLK_GATE) {
 305                 clk = clk_register_gate(NULL, devname, parent, 0,
 306                                         prv_base, 0, 0, NULL);
 307                 parent = devname;
 308         }
 309
 310         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 311                 /* Prevent division by zero */
 312                 if (!readl(prv_base))
 313                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 314
 315                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 316                 if (!clk_name)
 317                         return -ENOMEM;
 318                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 319                                                       0, prv_base,
 320                                                       1, 15, 16, 15, 0, NULL);
 321                 parent = clk_name;
 322
 323                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 324                 if (!clk_name) {
 325                         kfree(parent);
 326                         return -ENOMEM;
 327                 }
 328                 clk = clk_register_gate(NULL, clk_name, parent,
 329                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 330                                         prv_base, 31, 0, NULL);
 331                 kfree(parent);
 332                 kfree(clk_name);
 333         }
 334 out:
 335         if (IS_ERR(clk))
 336                 return PTR_ERR(clk);
 337
 338         pdata->clk = clk;
 339         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 340         return 0;
 341 }
 342
 343 static int acpi_lpss_create_device(struct acpi_device *adev,
 344                                    const struct acpi_device_id *id)
 345 {
 346         const struct lpss_device_desc *dev_desc;
 347         struct lpss_private_data *pdata;
 348         struct resource_entry *rentry;
 349         struct list_head resource_list;
 350         struct platform_device *pdev;
 351         int ret;
 352
 353         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 354         if (!dev_desc) {
 355                 pdev = acpi_create_platform_device(adev);
 356                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 357         }
 358         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 359         if (!pdata)
 360                 return -ENOMEM;
 361
 362         INIT_LIST_HEAD(&resource_list);
 363         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 364         if (ret < 0)
 365                 goto err_out;
 366
 367         list_for_each_entry(rentry, &resource_list, node)
 368                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 369                         if (dev_desc->prv_size_override)
 370                                 pdata->mmio_size = dev_desc->prv_size_override;
 371                         else
 372                                 pdata->mmio_size = resource_size(rentry->res);
 373                         pdata->mmio_base = ioremap(rentry->res->start,
 374                                                    pdata->mmio_size);
 375                         break;
 376                 }
 377
 378         acpi_dev_free_resource_list(&resource_list);
 379
 380         if (!pdata->mmio_base) {
 381                 ret = -ENOMEM;
 382                 goto err_out;
 383         }
 384
 385         pdata->dev_desc = dev_desc;
 386
 387         if (dev_desc->setup)
 388                 dev_desc->setup(pdata);
 389
 390         if (dev_desc->flags & LPSS_CLK) {
 391                 ret = register_device_clock(adev, pdata);
 392                 if (ret) {
 393                         /* Skip the device, but continue the namespace scan. */
 394                         ret = 0;
 395                         goto err_out;
 396                 }
 397         }
 398
 399         /*
 400          * This works around a known issue in ACPI tables where LPSS devices
 401          * have _PS0 and _PS3 without _PSC (and no power resources), so
 402          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 403          */
 404         ret = acpi_device_fix_up_power(adev);
 405         if (ret) {
 406                 /* Skip the device, but continue the namespace scan. */
 407                 ret = 0;
 408                 goto err_out;
 409         }
 410
 411         adev->driver_data = pdata;
 412         pdev = acpi_create_platform_device(adev);
 413         if (!IS_ERR_OR_NULL(pdev)) {
 414                 return 1;
 415         }
 416
 417         ret = PTR_ERR(pdev);
 418         adev->driver_data = NULL;
 419
 420  err_out:
 421         kfree(pdata);
 422         return ret;
 423 }
 424
 425 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 426 {
 427         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 428 }
 429
 430 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 431                              unsigned int reg)
 432 {
 433         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 434 }
 435
 436 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 437 {
 438         struct acpi_device *adev;
 439         struct lpss_private_data *pdata;
 440         unsigned long flags;
 441         int ret;
 442
 443         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 444         if (WARN_ON(ret))
 445                 return ret;
 446
 447         spin_lock_irqsave(&dev->power.lock, flags);
 448         if (pm_runtime_suspended(dev)) {
 449                 ret = -EAGAIN;
 450                 goto out;
 451         }
 452         pdata = acpi_driver_data(adev);
 453         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 454                 ret = -ENODEV;
 455                 goto out;
 456         }
 457         *val = __lpss_reg_read(pdata, reg);
 458
 459  out:
 460         spin_unlock_irqrestore(&dev->power.lock, flags);
 461         return ret;
 462 }
 463
 464 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 465                              char *buf)
 466 {
 467         u32 ltr_value = 0;
 468         unsigned int reg;
 469         int ret;
 470
 471         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 472         ret = lpss_reg_read(dev, reg, &ltr_value);
 473         if (ret)
 474                 return ret;
 475
 476         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 477 }
 478
 479 static ssize_t lpss_ltr_mode_show(struct device *dev,
 480                                   struct device_attribute *attr, char *buf)
 481 {
 482         u32 ltr_mode = 0;
 483         char *outstr;
 484         int ret;
 485
 486         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 487         if (ret)
 488                 return ret;
 489
 490         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 491         return sprintf(buf, "%s\n", outstr);
 492 }
 493
 494 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 495 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 496 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 497
 498 static struct attribute *lpss_attrs[] = {
 499         &dev_attr_auto_ltr.attr,
 500         &dev_attr_sw_ltr.attr,
 501         &dev_attr_ltr_mode.attr,
 502         NULL,
 503 };
 504
 505 static struct attribute_group lpss_attr_group = {
 506         .attrs = lpss_attrs,
 507         .name = "lpss_ltr",
 508 };
 509
 510 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 511 {
 512         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 513         u32 ltr_mode, ltr_val;
 514
 515         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 516         if (val < 0) {
 517                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 518                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 519                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 520                 }
 521                 return;
 522         }
 523         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 524         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 525                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 526                 val = LPSS_LTR_MAX_VAL;
 527         } else if (val > LPSS_LTR_MAX_VAL) {
 528                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 529                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 530         } else {
 531                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 532         }
 533         ltr_val |= val;
 534         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 535         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 536                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 537                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 538         }
 539 }
 540
 541 #ifdef CONFIG_PM
 542 /**
 543  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 544  * @dev: LPSS device
 545  * @pdata: pointer to the private data of the LPSS device
 546  *
 547  * Most LPSS devices have private registers which may loose their context when
 548  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 549  * prv_reg_ctx array.
 550  */
 551 static void acpi_lpss_save_ctx(struct device *dev,
 552                                struct lpss_private_data *pdata)
 553 {
 554         unsigned int i;
 555
 556         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 557                 unsigned long offset = i * sizeof(u32);
 558
 559                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 560                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 561                         pdata->prv_reg_ctx[i], offset);
 562         }
 563 }
 564
 565 /**
 566  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 567  * @dev: LPSS device
 568  * @pdata: pointer to the private data of the LPSS device
 569  *
 570  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 571  */
 572 static void acpi_lpss_restore_ctx(struct device *dev,
 573                                   struct lpss_private_data *pdata)
 574 {
 575         unsigned int i;
 576
 577         /*
 578          * The following delay is needed or the subsequent write operations may
 579          * fail. The LPSS devices are actually PCI devices and the PCI spec
 580          * expects 10ms delay before the device can be accessed after D3 to D0
 581          * transition. However some platforms like BSW does not need this delay.
 582          */
 583         unsigned int delay = 10;        /* default 10ms delay */
 584
 585         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 586                 delay = 0;
 587
 588         msleep(delay);
 589
 590         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 591                 unsigned long offset = i * sizeof(u32);
 592
 593                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 594                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 595                         pdata->prv_reg_ctx[i], offset);
 596         }
 597 }
 598
 599 #ifdef CONFIG_PM_SLEEP
 600 static int acpi_lpss_suspend_late(struct device *dev)
 601 {
 602         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 603         int ret;
 604
 605         ret = pm_generic_suspend_late(dev);
 606         if (ret)
 607                 return ret;
 608
 609         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 610                 acpi_lpss_save_ctx(dev, pdata);
 611
 612         return acpi_dev_suspend_late(dev);
 613 }
 614
 615 static int acpi_lpss_resume_early(struct device *dev)
 616 {
 617         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 618         int ret;
 619
 620         ret = acpi_dev_resume_early(dev);
 621         if (ret)
 622                 return ret;
 623
 624         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 625                 acpi_lpss_restore_ctx(dev, pdata);
 626
 627         return pm_generic_resume_early(dev);
 628 }
 629 #endif /* CONFIG_PM_SLEEP */
 630
 631 static int acpi_lpss_runtime_suspend(struct device *dev)
 632 {
 633         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 634         int ret;
 635
 636         ret = pm_generic_runtime_suspend(dev);
 637         if (ret)
 638                 return ret;
 639
 640         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 641                 acpi_lpss_save_ctx(dev, pdata);
 642
 643         return acpi_dev_runtime_suspend(dev);
 644 }
 645
 646 static int acpi_lpss_runtime_resume(struct device *dev)
 647 {
 648         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 649         int ret;
 650
 651         ret = acpi_dev_runtime_resume(dev);
 652         if (ret)
 653                 return ret;
 654
 655         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 656                 acpi_lpss_restore_ctx(dev, pdata);
 657
 658         return pm_generic_runtime_resume(dev);
 659 }
 660 #endif /* CONFIG_PM */
 661
 662 static struct dev_pm_domain acpi_lpss_pm_domain = {
 663         .ops = {
 664 #ifdef CONFIG_PM
 665 #ifdef CONFIG_PM_SLEEP
 666                 .prepare = acpi_subsys_prepare,
 667                 .complete = pm_complete_with_resume_check,
 668                 .suspend = acpi_subsys_suspend,
 669                 .suspend_late = acpi_lpss_suspend_late,
 670                 .resume_early = acpi_lpss_resume_early,
 671                 .freeze = acpi_subsys_freeze,
 672                 .poweroff = acpi_subsys_suspend,
 673                 .poweroff_late = acpi_lpss_suspend_late,
 674                 .restore_early = acpi_lpss_resume_early,
 675 #endif
 676                 .runtime_suspend = acpi_lpss_runtime_suspend,
 677                 .runtime_resume = acpi_lpss_runtime_resume,
 678 #endif
 679         },
 680 };
 681
 682 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 683                                      unsigned long action, void *data)
 684 {
 685         struct platform_device *pdev = to_platform_device(data);
 686         struct lpss_private_data *pdata;
 687         struct acpi_device *adev;
 688         const struct acpi_device_id *id;
 689
 690         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 691         if (!id || !id->driver_data)
 692                 return 0;
 693
 694         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 695                 return 0;
 696
 697         pdata = acpi_driver_data(adev);
 698         if (!pdata)
 699                 return 0;
 700
 701         if (pdata->mmio_base &&
 702             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 703                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 704                 return 0;
 705         }
 706
 707         switch (action) {
 708         case BUS_NOTIFY_ADD_DEVICE:
 709                 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
 710                 if (pdata->dev_desc->flags & LPSS_LTR)
 711                         return sysfs_create_group(&pdev->dev.kobj,
 712                                                   &lpss_attr_group);
 713                 break;
 714         case BUS_NOTIFY_DEL_DEVICE:
 715                 if (pdata->dev_desc->flags & LPSS_LTR)
 716                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 717                 pdev->dev.pm_domain = NULL;
 718                 break;
 719         default:
 720                 break;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static struct notifier_block acpi_lpss_nb = {
 727         .notifier_call = acpi_lpss_platform_notify,
 728 };
 729
 730 static void acpi_lpss_bind(struct device *dev)
 731 {
 732         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 733
 734         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 735                 return;
 736
 737         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 738                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 739         else
 740                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 741 }
 742
 743 static void acpi_lpss_unbind(struct device *dev)
 744 {
 745         dev->power.set_latency_tolerance = NULL;
 746 }
 747
 748 static struct acpi_scan_handler lpss_handler = {
 749         .ids = acpi_lpss_device_ids,
 750         .attach = acpi_lpss_create_device,
 751         .bind = acpi_lpss_bind,
 752         .unbind = acpi_lpss_unbind,
 753 };
 754
 755 void __init acpi_lpss_init(void)
 756 {
 757         if (!lpt_clk_init()) {
 758                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 759                 acpi_scan_add_handler(&lpss_handler);
 760         }
 761 }
 762
 763 #else
 764
 765 static struct acpi_scan_handler lpss_handler = {
 766         .ids = acpi_lpss_device_ids,
 767 };
 768
 769 void __init acpi_lpss_init(void)
 770 {
 771         acpi_scan_add_handler(&lpss_handler);
 772 }
 773
 774 #endif /* CONFIG_X86_INTEL_LPSS */