2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
60 /* board IDs by feature in alphabetical order */
66 /* board IDs for specific chipsets in alphabetical order */
72 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
86 static bool is_mcp89_apple(struct pci_dev *pdev);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 static struct scsi_host_template ahci_sht = {
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
108 static const struct ata_port_info ahci_port_info[] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
116 [board_ahci_ign_iferr] = {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
123 [board_ahci_nosntf] = {
124 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
130 [board_ahci_yes_fbs] = {
131 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
138 [board_ahci_mcp65] = {
139 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
141 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
146 [board_ahci_mcp77] = {
147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
153 [board_ahci_mcp89] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
161 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
162 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
163 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
168 [board_ahci_sb600] = {
169 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
170 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
171 AHCI_HFLAG_32BIT_ONLY),
172 .flags = AHCI_FLAG_COMMON,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_pmp_retry_srst_ops,
177 [board_ahci_sb700] = { /* for SB700 and SB800 */
178 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
184 [board_ahci_vt8251] = {
185 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_vt8251_ops,
193 static const struct pci_device_id ahci_pci_tbl[] = {
195 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
196 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
197 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
198 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
199 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
200 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
201 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
204 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
205 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
208 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
210 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
215 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
222 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
223 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
224 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
225 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
226 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
227 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
228 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
229 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
230 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
231 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
232 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
233 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
234 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
237 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
241 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
242 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
244 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
245 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
248 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
252 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
253 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
261 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
263 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
268 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
269 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
271 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
277 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
286 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
287 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
288 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
291 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
292 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
296 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
297 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
301 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
302 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
303 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
304 /* JMicron 362B and 362C have an AHCI function with IDE class code */
305 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
306 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
309 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
310 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
311 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
312 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
313 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
315 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
319 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
320 /* AMD is using RAID class only for ahci controllers */
321 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
322 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
325 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
326 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
329 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
330 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
332 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
416 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
417 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
419 /* ST Microelectronics */
420 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
423 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
424 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
425 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
426 .class = PCI_CLASS_STORAGE_SATA_AHCI,
427 .class_mask = 0xffffff,
428 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
429 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
430 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
431 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
432 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
433 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
439 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
441 .driver_data = board_ahci_yes_fbs },
442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
443 .driver_data = board_ahci_yes_fbs },
446 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
449 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
450 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
451 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
452 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
455 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
457 /* Generic, PCI class code for AHCI */
458 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
459 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
461 { } /* terminate list */
465 static struct pci_driver ahci_pci_driver = {
467 .id_table = ahci_pci_tbl,
468 .probe = ahci_init_one,
469 .remove = ata_pci_remove_one,
471 .suspend = ahci_pci_device_suspend,
472 .resume = ahci_pci_device_resume,
476 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
477 static int marvell_enable;
479 static int marvell_enable = 1;
481 module_param(marvell_enable, int, 0644);
482 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
485 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
486 struct ahci_host_priv *hpriv)
488 unsigned int force_port_map = 0;
489 unsigned int mask_port_map = 0;
491 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
492 dev_info(&pdev->dev, "JMB361 has only one port\n");
497 * Temporary Marvell 6145 hack: PATA port presence
498 * is asserted through the standard AHCI port
499 * presence register, as bit 4 (counting from 0)
501 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
502 if (pdev->device == 0x6121)
507 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
510 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
514 static int ahci_pci_reset_controller(struct ata_host *host)
516 struct pci_dev *pdev = to_pci_dev(host->dev);
518 ahci_reset_controller(host);
520 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
521 struct ahci_host_priv *hpriv = host->private_data;
525 pci_read_config_word(pdev, 0x92, &tmp16);
526 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
527 tmp16 |= hpriv->port_map;
528 pci_write_config_word(pdev, 0x92, tmp16);
535 static void ahci_pci_init_controller(struct ata_host *host)
537 struct ahci_host_priv *hpriv = host->private_data;
538 struct pci_dev *pdev = to_pci_dev(host->dev);
539 void __iomem *port_mmio;
543 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
544 if (pdev->device == 0x6121)
548 port_mmio = __ahci_port_base(host, mv);
550 writel(0, port_mmio + PORT_IRQ_MASK);
553 tmp = readl(port_mmio + PORT_IRQ_STAT);
554 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
556 writel(tmp, port_mmio + PORT_IRQ_STAT);
559 ahci_init_controller(host);
562 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
563 unsigned long deadline)
565 struct ata_port *ap = link->ap;
566 struct ahci_host_priv *hpriv = ap->host->private_data;
572 ahci_stop_engine(ap);
574 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
575 deadline, &online, NULL);
577 hpriv->start_engine(ap);
579 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
581 /* vt8251 doesn't clear BSY on signature FIS reception,
582 * request follow-up softreset.
584 return online ? -EAGAIN : rc;
587 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
588 unsigned long deadline)
590 struct ata_port *ap = link->ap;
591 struct ahci_port_priv *pp = ap->private_data;
592 struct ahci_host_priv *hpriv = ap->host->private_data;
593 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
594 struct ata_taskfile tf;
598 ahci_stop_engine(ap);
600 /* clear D2H reception area to properly wait for D2H FIS */
601 ata_tf_init(link->device, &tf);
602 tf.command = ATA_BUSY;
603 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
605 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
606 deadline, &online, NULL);
608 hpriv->start_engine(ap);
610 /* The pseudo configuration device on SIMG4726 attached to
611 * ASUS P5W-DH Deluxe doesn't send signature FIS after
612 * hardreset if no device is attached to the first downstream
613 * port && the pseudo device locks up on SRST w/ PMP==0. To
614 * work around this, wait for !BSY only briefly. If BSY isn't
615 * cleared, perform CLO and proceed to IDENTIFY (achieved by
616 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
618 * Wait for two seconds. Devices attached to downstream port
619 * which can't process the following IDENTIFY after this will
620 * have to be reset again. For most cases, this should
621 * suffice while making probing snappish enough.
624 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
627 ahci_kick_engine(ap);
633 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
635 struct ata_host *host = pci_get_drvdata(pdev);
636 struct ahci_host_priv *hpriv = host->private_data;
637 void __iomem *mmio = hpriv->mmio;
640 if (mesg.event & PM_EVENT_SUSPEND &&
641 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
643 "BIOS update required for suspend/resume\n");
647 if (mesg.event & PM_EVENT_SLEEP) {
648 /* AHCI spec rev1.1 section 8.3.3:
649 * Software must disable interrupts prior to requesting a
650 * transition of the HBA to D3 state.
652 ctl = readl(mmio + HOST_CTL);
654 writel(ctl, mmio + HOST_CTL);
655 readl(mmio + HOST_CTL); /* flush */
658 return ata_pci_device_suspend(pdev, mesg);
661 static int ahci_pci_device_resume(struct pci_dev *pdev)
663 struct ata_host *host = pci_get_drvdata(pdev);
666 rc = ata_pci_device_do_resume(pdev);
670 /* Apple BIOS helpfully mangles the registers on resume */
671 if (is_mcp89_apple(pdev))
672 ahci_mcp89_apple_enable(pdev);
674 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
675 rc = ahci_pci_reset_controller(host);
679 ahci_pci_init_controller(host);
682 ata_host_resume(host);
688 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
693 * If the device fixup already set the dma_mask to some non-standard
694 * value, don't extend it here. This happens on STA2X11, for example.
696 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
700 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
701 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
703 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
706 "64-bit DMA enable failed\n");
711 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
713 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
716 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
719 "32-bit consistent DMA enable failed\n");
726 static void ahci_pci_print_info(struct ata_host *host)
728 struct pci_dev *pdev = to_pci_dev(host->dev);
732 pci_read_config_word(pdev, 0x0a, &cc);
733 if (cc == PCI_CLASS_STORAGE_IDE)
735 else if (cc == PCI_CLASS_STORAGE_SATA)
737 else if (cc == PCI_CLASS_STORAGE_RAID)
742 ahci_print_info(host, scc_s);
745 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
746 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
747 * support PMP and the 4726 either directly exports the device
748 * attached to the first downstream port or acts as a hardware storage
749 * controller and emulate a single ATA device (can be RAID 0/1 or some
750 * other configuration).
752 * When there's no device attached to the first downstream port of the
753 * 4726, "Config Disk" appears, which is a pseudo ATA device to
754 * configure the 4726. However, ATA emulation of the device is very
755 * lame. It doesn't send signature D2H Reg FIS after the initial
756 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
758 * The following function works around the problem by always using
759 * hardreset on the port and not depending on receiving signature FIS
760 * afterward. If signature FIS isn't received soon, ATA class is
761 * assumed without follow-up softreset.
763 static void ahci_p5wdh_workaround(struct ata_host *host)
765 static struct dmi_system_id sysids[] = {
767 .ident = "P5W DH Deluxe",
769 DMI_MATCH(DMI_SYS_VENDOR,
770 "ASUSTEK COMPUTER INC"),
771 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
776 struct pci_dev *pdev = to_pci_dev(host->dev);
778 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
779 dmi_check_system(sysids)) {
780 struct ata_port *ap = host->ports[1];
783 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
785 ap->ops = &ahci_p5wdh_ops;
786 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
791 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
792 * booting in BIOS compatibility mode. We restore the registers but not ID.
794 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
798 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
800 pci_read_config_dword(pdev, 0xf8, &val);
802 /* the following changes the device ID, but appears not to affect function */
803 /* val = (val & ~0xf0000000) | 0x80000000; */
804 pci_write_config_dword(pdev, 0xf8, val);
806 pci_read_config_dword(pdev, 0x54c, &val);
808 pci_write_config_dword(pdev, 0x54c, val);
810 pci_read_config_dword(pdev, 0x4a4, &val);
813 pci_write_config_dword(pdev, 0x4a4, val);
815 pci_read_config_dword(pdev, 0x54c, &val);
817 pci_write_config_dword(pdev, 0x54c, val);
819 pci_read_config_dword(pdev, 0xf8, &val);
821 pci_write_config_dword(pdev, 0xf8, val);
824 static bool is_mcp89_apple(struct pci_dev *pdev)
826 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
827 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
828 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
829 pdev->subsystem_device == 0xcb89;
832 /* only some SB600 ahci controllers can do 64bit DMA */
833 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
835 static const struct dmi_system_id sysids[] = {
837 * The oldest version known to be broken is 0901 and
838 * working is 1501 which was released on 2007-10-26.
839 * Enable 64bit DMA on 1501 and anything newer.
841 * Please read bko#9412 for more info.
844 .ident = "ASUS M2A-VM",
846 DMI_MATCH(DMI_BOARD_VENDOR,
847 "ASUSTeK Computer INC."),
848 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
850 .driver_data = "20071026", /* yyyymmdd */
853 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
856 * BIOS versions earlier than 1.5 had the Manufacturer DMI
857 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
858 * This spelling mistake was fixed in BIOS version 1.5, so
859 * 1.5 and later have the Manufacturer as
860 * "MICRO-STAR INTERNATIONAL CO.,LTD".
861 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
863 * BIOS versions earlier than 1.9 had a Board Product Name
864 * DMI field of "MS-7376". This was changed to be
865 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
866 * match on DMI_BOARD_NAME of "MS-7376".
869 .ident = "MSI K9A2 Platinum",
871 DMI_MATCH(DMI_BOARD_VENDOR,
873 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
877 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
880 * This board also had the typo mentioned above in the
881 * Manufacturer DMI field (fixed in BIOS version 1.5), so
882 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
885 .ident = "MSI K9AGM2",
887 DMI_MATCH(DMI_BOARD_VENDOR,
889 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
893 * All BIOS versions for the Asus M3A support 64bit DMA.
894 * (all release versions from 0301 to 1206 were tested)
899 DMI_MATCH(DMI_BOARD_VENDOR,
900 "ASUSTeK Computer INC."),
901 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
906 const struct dmi_system_id *match;
907 int year, month, date;
910 match = dmi_first_match(sysids);
911 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
915 if (!match->driver_data)
918 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
919 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
921 if (strcmp(buf, match->driver_data) >= 0)
925 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
931 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
935 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
937 static const struct dmi_system_id broken_systems[] = {
939 .ident = "HP Compaq nx6310",
941 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
942 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
944 /* PCI slot number of the controller */
945 .driver_data = (void *)0x1FUL,
948 .ident = "HP Compaq 6720s",
950 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
951 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
953 /* PCI slot number of the controller */
954 .driver_data = (void *)0x1FUL,
957 { } /* terminate list */
959 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
962 unsigned long slot = (unsigned long)dmi->driver_data;
963 /* apply the quirk only to on-board controllers */
964 return slot == PCI_SLOT(pdev->devfn);
970 static bool ahci_broken_suspend(struct pci_dev *pdev)
972 static const struct dmi_system_id sysids[] = {
974 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
975 * to the harddisk doesn't become online after
976 * resuming from STR. Warn and fail suspend.
978 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
980 * Use dates instead of versions to match as HP is
981 * apparently recycling both product and version
984 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
989 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
990 DMI_MATCH(DMI_PRODUCT_NAME,
991 "HP Pavilion dv4 Notebook PC"),
993 .driver_data = "20090105", /* F.30 */
998 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
999 DMI_MATCH(DMI_PRODUCT_NAME,
1000 "HP Pavilion dv5 Notebook PC"),
1002 .driver_data = "20090506", /* F.16 */
1007 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1008 DMI_MATCH(DMI_PRODUCT_NAME,
1009 "HP Pavilion dv6 Notebook PC"),
1011 .driver_data = "20090423", /* F.21 */
1016 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1017 DMI_MATCH(DMI_PRODUCT_NAME,
1018 "HP HDX18 Notebook PC"),
1020 .driver_data = "20090430", /* F.23 */
1023 * Acer eMachines G725 has the same problem. BIOS
1024 * V1.03 is known to be broken. V3.04 is known to
1025 * work. Between, there are V1.06, V2.06 and V3.03
1026 * that we don't have much idea about. For now,
1027 * blacklist anything older than V3.04.
1029 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1034 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1035 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1037 .driver_data = "20091216", /* V3.04 */
1039 { } /* terminate list */
1041 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1042 int year, month, date;
1045 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1048 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1049 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1051 return strcmp(buf, dmi->driver_data) < 0;
1054 static bool ahci_broken_online(struct pci_dev *pdev)
1056 #define ENCODE_BUSDEVFN(bus, slot, func) \
1057 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1058 static const struct dmi_system_id sysids[] = {
1060 * There are several gigabyte boards which use
1061 * SIMG5723s configured as hardware RAID. Certain
1062 * 5723 firmware revisions shipped there keep the link
1063 * online but fail to answer properly to SRST or
1064 * IDENTIFY when no device is attached downstream
1065 * causing libata to retry quite a few times leading
1066 * to excessive detection delay.
1068 * As these firmwares respond to the second reset try
1069 * with invalid device signature, considering unknown
1070 * sig as offline works around the problem acceptably.
1073 .ident = "EP45-DQ6",
1075 DMI_MATCH(DMI_BOARD_VENDOR,
1076 "Gigabyte Technology Co., Ltd."),
1077 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1079 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1082 .ident = "EP45-DS5",
1084 DMI_MATCH(DMI_BOARD_VENDOR,
1085 "Gigabyte Technology Co., Ltd."),
1086 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1088 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1090 { } /* terminate list */
1092 #undef ENCODE_BUSDEVFN
1093 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1099 val = (unsigned long)dmi->driver_data;
1101 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1104 #ifdef CONFIG_ATA_ACPI
1105 static void ahci_gtf_filter_workaround(struct ata_host *host)
1107 static const struct dmi_system_id sysids[] = {
1109 * Aspire 3810T issues a bunch of SATA enable commands
1110 * via _GTF including an invalid one and one which is
1111 * rejected by the device. Among the successful ones
1112 * is FPDMA non-zero offset enable which when enabled
1113 * only on the drive side leads to NCQ command
1114 * failures. Filter it out.
1117 .ident = "Aspire 3810T",
1119 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1120 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1122 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1126 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1127 unsigned int filter;
1133 filter = (unsigned long)dmi->driver_data;
1134 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1135 filter, dmi->ident);
1137 for (i = 0; i < host->n_ports; i++) {
1138 struct ata_port *ap = host->ports[i];
1139 struct ata_link *link;
1140 struct ata_device *dev;
1142 ata_for_each_link(link, ap, EDGE)
1143 ata_for_each_dev(dev, link, ALL)
1144 dev->gtf_filter |= filter;
1148 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1152 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1153 struct ahci_host_priv *hpriv)
1157 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1160 rc = pci_msi_vec_count(pdev);
1165 * If number of MSIs is less than number of ports then Sharing Last
1166 * Message mode could be enforced. In this case assume that advantage
1167 * of multipe MSIs is negated and use single MSI mode instead.
1173 rc = pci_enable_msi_block(pdev, nvec);
1180 rc = pci_enable_msi(pdev);
1191 * ahci_host_activate - start AHCI host, request IRQs and register it
1192 * @host: target ATA host
1193 * @irq: base IRQ number to request
1194 * @n_msis: number of MSIs allocated for this host
1195 * @irq_handler: irq_handler used when requesting IRQs
1196 * @irq_flags: irq_flags used when requesting IRQs
1198 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1199 * when multiple MSIs were allocated. That is one MSI per port, starting
1203 * Inherited from calling layer (may sleep).
1206 * 0 on success, -errno otherwise.
1208 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1212 /* Sharing Last Message among several ports is not supported */
1213 if (n_msis < host->n_ports)
1216 rc = ata_host_start(host);
1220 for (i = 0; i < host->n_ports; i++) {
1222 struct ahci_port_priv *pp = host->ports[i]->private_data;
1224 /* pp is NULL for dummy ports */
1226 desc = pp->irq_desc;
1228 desc = dev_driver_string(host->dev);
1230 rc = devm_request_threaded_irq(host->dev,
1231 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1232 desc, host->ports[i]);
1237 for (i = 0; i < host->n_ports; i++)
1238 ata_port_desc(host->ports[i], "irq %d", irq + i);
1240 rc = ata_host_register(host, &ahci_sht);
1242 goto out_free_all_irqs;
1249 for (i--; i >= 0; i--)
1250 devm_free_irq(host->dev, irq + i, host->ports[i]);
1255 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1257 unsigned int board_id = ent->driver_data;
1258 struct ata_port_info pi = ahci_port_info[board_id];
1259 const struct ata_port_info *ppi[] = { &pi, NULL };
1260 struct device *dev = &pdev->dev;
1261 struct ahci_host_priv *hpriv;
1262 struct ata_host *host;
1263 int n_ports, n_msis, i, rc;
1264 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1268 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1270 ata_print_version_once(&pdev->dev, DRV_VERSION);
1272 /* The AHCI driver can only drive the SATA ports, the PATA driver
1273 can drive them all so if both drivers are selected make sure
1274 AHCI stays out of the way */
1275 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1278 /* Apple BIOS on MCP89 prevents us using AHCI */
1279 if (is_mcp89_apple(pdev))
1280 ahci_mcp89_apple_enable(pdev);
1282 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1283 * At the moment, we can only use the AHCI mode. Let the users know
1284 * that for SAS drives they're out of luck.
1286 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1287 dev_info(&pdev->dev,
1288 "PDC42819 can only drive SATA devices with this driver\n");
1290 /* Both Connext and Enmotus devices use non-standard BARs */
1291 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1292 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1293 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1294 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1296 /* acquire resources */
1297 rc = pcim_enable_device(pdev);
1301 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1302 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1305 /* ICH6s share the same PCI ID for both piix and ahci
1306 * modes. Enabling ahci mode while MAP indicates
1307 * combined mode is a bad idea. Yield to ata_piix.
1309 pci_read_config_byte(pdev, ICH_MAP, &map);
1311 dev_info(&pdev->dev,
1312 "controller is in combined mode, can't enable AHCI mode\n");
1317 /* AHCI controllers often implement SFF compatible interface.
1318 * Grab all PCI BARs just in case.
1320 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1322 pcim_pin_device(pdev);
1326 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1329 hpriv->flags |= (unsigned long)pi.private_data;
1331 /* MCP65 revision A1 and A2 can't do MSI */
1332 if (board_id == board_ahci_mcp65 &&
1333 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1334 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1336 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1337 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1338 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1340 /* only some SB600s can do 64bit DMA */
1341 if (ahci_sb600_enable_64bit(pdev))
1342 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1344 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1346 /* save initial config */
1347 ahci_pci_save_initial_config(pdev, hpriv);
1350 if (hpriv->cap & HOST_CAP_NCQ) {
1351 pi.flags |= ATA_FLAG_NCQ;
1353 * Auto-activate optimization is supposed to be
1354 * supported on all AHCI controllers indicating NCQ
1355 * capability, but it seems to be broken on some
1356 * chipsets including NVIDIAs.
1358 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1359 pi.flags |= ATA_FLAG_FPDMA_AA;
1362 * All AHCI controllers should be forward-compatible
1363 * with the new auxiliary field. This code should be
1364 * conditionalized if any buggy AHCI controllers are
1367 pi.flags |= ATA_FLAG_FPDMA_AUX;
1370 if (hpriv->cap & HOST_CAP_PMP)
1371 pi.flags |= ATA_FLAG_PMP;
1373 ahci_set_em_messages(hpriv, &pi);
1375 if (ahci_broken_system_poweroff(pdev)) {
1376 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1377 dev_info(&pdev->dev,
1378 "quirky BIOS, skipping spindown on poweroff\n");
1381 if (ahci_broken_suspend(pdev)) {
1382 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1383 dev_warn(&pdev->dev,
1384 "BIOS update required for suspend/resume\n");
1387 if (ahci_broken_online(pdev)) {
1388 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1389 dev_info(&pdev->dev,
1390 "online status unreliable, applying workaround\n");
1393 /* CAP.NP sometimes indicate the index of the last enabled
1394 * port, at other times, that of the last possible port, so
1395 * determining the maximum port number requires looking at
1396 * both CAP.NP and port_map.
1398 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1400 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1402 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1404 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1407 host->private_data = hpriv;
1409 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1410 host->flags |= ATA_HOST_PARALLEL_SCAN;
1412 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1414 if (pi.flags & ATA_FLAG_EM)
1415 ahci_reset_em(host);
1417 for (i = 0; i < host->n_ports; i++) {
1418 struct ata_port *ap = host->ports[i];
1420 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1421 ata_port_pbar_desc(ap, ahci_pci_bar,
1422 0x100 + ap->port_no * 0x80, "port");
1424 /* set enclosure management message type */
1425 if (ap->flags & ATA_FLAG_EM)
1426 ap->em_message_type = hpriv->em_msg_type;
1429 /* disabled/not-implemented port */
1430 if (!(hpriv->port_map & (1 << i)))
1431 ap->ops = &ata_dummy_port_ops;
1434 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1435 ahci_p5wdh_workaround(host);
1437 /* apply gtf filter quirk */
1438 ahci_gtf_filter_workaround(host);
1440 /* initialize adapter */
1441 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1445 rc = ahci_pci_reset_controller(host);
1449 ahci_pci_init_controller(host);
1450 ahci_pci_print_info(host);
1452 pci_set_master(pdev);
1454 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1455 return ahci_host_activate(host, pdev->irq, n_msis);
1457 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1461 module_pci_driver(ahci_pci_driver);
1463 MODULE_AUTHOR("Jeff Garzik");
1464 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1465 MODULE_LICENSE("GPL");
1466 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1467 MODULE_VERSION(DRV_VERSION);