2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_sb700, /* for SB700 and SB800 */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
95 static struct scsi_host_template ahci_sht = {
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
109 static const struct ata_port_info ahci_port_info[] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_nomsi] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
131 [board_ahci_noncq] = {
132 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
138 [board_ahci_nosntf] = {
139 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
145 [board_ahci_yes_fbs] = {
146 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
153 [board_ahci_mcp65] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
161 [board_ahci_mcp77] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
168 [board_ahci_mcp89] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
183 [board_ahci_sb600] = {
184 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
185 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
186 AHCI_HFLAG_32BIT_ONLY),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
192 [board_ahci_sb700] = { /* for SB700 and SB800 */
193 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_pmp_retry_srst_ops,
199 [board_ahci_vt8251] = {
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_vt8251_ops,
208 static const struct pci_device_id ahci_pci_tbl[] = {
210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
257 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
258 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
260 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
261 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
269 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
277 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
279 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
293 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
303 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
307 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
308 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
311 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
312 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
313 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
316 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
318 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
324 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
327 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
328 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
329 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
330 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
332 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
333 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
334 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
335 /* JMicron 362B and 362C have an AHCI function with IDE class code */
336 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
337 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
340 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
341 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
346 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
349 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
350 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
351 /* AMD is using RAID class only for ahci controllers */
352 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
353 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
356 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
357 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
360 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
368 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
380 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
432 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
443 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
446 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
447 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
448 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
450 /* ST Microelectronics */
451 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
454 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
455 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
457 .class = PCI_CLASS_STORAGE_SATA_AHCI,
458 .class_mask = 0xffffff,
459 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
461 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
462 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
463 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
464 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
465 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
466 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
467 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
468 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
469 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
470 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
472 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
474 .driver_data = board_ahci_yes_fbs },
475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
476 .driver_data = board_ahci_yes_fbs },
477 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
478 .driver_data = board_ahci_yes_fbs },
479 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
480 .driver_data = board_ahci_yes_fbs },
483 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
484 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
487 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
488 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
489 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
490 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
493 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
494 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
496 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
497 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
500 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
502 /* Generic, PCI class code for AHCI */
503 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
504 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
506 { } /* terminate list */
510 static struct pci_driver ahci_pci_driver = {
512 .id_table = ahci_pci_tbl,
513 .probe = ahci_init_one,
514 .remove = ata_pci_remove_one,
516 .suspend = ahci_pci_device_suspend,
517 .resume = ahci_pci_device_resume,
521 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
522 static int marvell_enable;
524 static int marvell_enable = 1;
526 module_param(marvell_enable, int, 0644);
527 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
530 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
531 struct ahci_host_priv *hpriv)
533 unsigned int force_port_map = 0;
534 unsigned int mask_port_map = 0;
536 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
537 dev_info(&pdev->dev, "JMB361 has only one port\n");
542 * Temporary Marvell 6145 hack: PATA port presence
543 * is asserted through the standard AHCI port
544 * presence register, as bit 4 (counting from 0)
546 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
547 if (pdev->device == 0x6121)
552 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
555 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
559 static int ahci_pci_reset_controller(struct ata_host *host)
561 struct pci_dev *pdev = to_pci_dev(host->dev);
563 ahci_reset_controller(host);
565 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
566 struct ahci_host_priv *hpriv = host->private_data;
570 pci_read_config_word(pdev, 0x92, &tmp16);
571 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
572 tmp16 |= hpriv->port_map;
573 pci_write_config_word(pdev, 0x92, tmp16);
580 static void ahci_pci_init_controller(struct ata_host *host)
582 struct ahci_host_priv *hpriv = host->private_data;
583 struct pci_dev *pdev = to_pci_dev(host->dev);
584 void __iomem *port_mmio;
588 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
589 if (pdev->device == 0x6121)
593 port_mmio = __ahci_port_base(host, mv);
595 writel(0, port_mmio + PORT_IRQ_MASK);
598 tmp = readl(port_mmio + PORT_IRQ_STAT);
599 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
601 writel(tmp, port_mmio + PORT_IRQ_STAT);
604 ahci_init_controller(host);
607 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
608 unsigned long deadline)
610 struct ata_port *ap = link->ap;
616 ahci_stop_engine(ap);
618 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
619 deadline, &online, NULL);
621 ahci_start_engine(ap);
623 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
625 /* vt8251 doesn't clear BSY on signature FIS reception,
626 * request follow-up softreset.
628 return online ? -EAGAIN : rc;
631 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
632 unsigned long deadline)
634 struct ata_port *ap = link->ap;
635 struct ahci_port_priv *pp = ap->private_data;
636 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
637 struct ata_taskfile tf;
641 ahci_stop_engine(ap);
643 /* clear D2H reception area to properly wait for D2H FIS */
644 ata_tf_init(link->device, &tf);
646 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
648 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
649 deadline, &online, NULL);
651 ahci_start_engine(ap);
653 /* The pseudo configuration device on SIMG4726 attached to
654 * ASUS P5W-DH Deluxe doesn't send signature FIS after
655 * hardreset if no device is attached to the first downstream
656 * port && the pseudo device locks up on SRST w/ PMP==0. To
657 * work around this, wait for !BSY only briefly. If BSY isn't
658 * cleared, perform CLO and proceed to IDENTIFY (achieved by
659 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
661 * Wait for two seconds. Devices attached to downstream port
662 * which can't process the following IDENTIFY after this will
663 * have to be reset again. For most cases, this should
664 * suffice while making probing snappish enough.
667 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
670 ahci_kick_engine(ap);
676 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
678 struct ata_host *host = dev_get_drvdata(&pdev->dev);
679 struct ahci_host_priv *hpriv = host->private_data;
680 void __iomem *mmio = hpriv->mmio;
683 if (mesg.event & PM_EVENT_SUSPEND &&
684 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
686 "BIOS update required for suspend/resume\n");
690 if (mesg.event & PM_EVENT_SLEEP) {
691 /* AHCI spec rev1.1 section 8.3.3:
692 * Software must disable interrupts prior to requesting a
693 * transition of the HBA to D3 state.
695 ctl = readl(mmio + HOST_CTL);
697 writel(ctl, mmio + HOST_CTL);
698 readl(mmio + HOST_CTL); /* flush */
701 return ata_pci_device_suspend(pdev, mesg);
704 static int ahci_pci_device_resume(struct pci_dev *pdev)
706 struct ata_host *host = dev_get_drvdata(&pdev->dev);
709 rc = ata_pci_device_do_resume(pdev);
713 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
714 rc = ahci_pci_reset_controller(host);
718 ahci_pci_init_controller(host);
721 ata_host_resume(host);
727 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
732 * If the device fixup already set the dma_mask to some non-standard
733 * value, don't extend it here. This happens on STA2X11, for example.
735 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
739 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
740 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
742 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
745 "64-bit DMA enable failed\n");
750 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
752 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
755 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
758 "32-bit consistent DMA enable failed\n");
765 static void ahci_pci_print_info(struct ata_host *host)
767 struct pci_dev *pdev = to_pci_dev(host->dev);
771 pci_read_config_word(pdev, 0x0a, &cc);
772 if (cc == PCI_CLASS_STORAGE_IDE)
774 else if (cc == PCI_CLASS_STORAGE_SATA)
776 else if (cc == PCI_CLASS_STORAGE_RAID)
781 ahci_print_info(host, scc_s);
784 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
785 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
786 * support PMP and the 4726 either directly exports the device
787 * attached to the first downstream port or acts as a hardware storage
788 * controller and emulate a single ATA device (can be RAID 0/1 or some
789 * other configuration).
791 * When there's no device attached to the first downstream port of the
792 * 4726, "Config Disk" appears, which is a pseudo ATA device to
793 * configure the 4726. However, ATA emulation of the device is very
794 * lame. It doesn't send signature D2H Reg FIS after the initial
795 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
797 * The following function works around the problem by always using
798 * hardreset on the port and not depending on receiving signature FIS
799 * afterward. If signature FIS isn't received soon, ATA class is
800 * assumed without follow-up softreset.
802 static void ahci_p5wdh_workaround(struct ata_host *host)
804 static struct dmi_system_id sysids[] = {
806 .ident = "P5W DH Deluxe",
808 DMI_MATCH(DMI_SYS_VENDOR,
809 "ASUSTEK COMPUTER INC"),
810 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
815 struct pci_dev *pdev = to_pci_dev(host->dev);
817 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
818 dmi_check_system(sysids)) {
819 struct ata_port *ap = host->ports[1];
822 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
824 ap->ops = &ahci_p5wdh_ops;
825 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
829 /* only some SB600 ahci controllers can do 64bit DMA */
830 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
832 static const struct dmi_system_id sysids[] = {
834 * The oldest version known to be broken is 0901 and
835 * working is 1501 which was released on 2007-10-26.
836 * Enable 64bit DMA on 1501 and anything newer.
838 * Please read bko#9412 for more info.
841 .ident = "ASUS M2A-VM",
843 DMI_MATCH(DMI_BOARD_VENDOR,
844 "ASUSTeK Computer INC."),
845 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
847 .driver_data = "20071026", /* yyyymmdd */
850 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
853 * BIOS versions earlier than 1.5 had the Manufacturer DMI
854 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
855 * This spelling mistake was fixed in BIOS version 1.5, so
856 * 1.5 and later have the Manufacturer as
857 * "MICRO-STAR INTERNATIONAL CO.,LTD".
858 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
860 * BIOS versions earlier than 1.9 had a Board Product Name
861 * DMI field of "MS-7376". This was changed to be
862 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
863 * match on DMI_BOARD_NAME of "MS-7376".
866 .ident = "MSI K9A2 Platinum",
868 DMI_MATCH(DMI_BOARD_VENDOR,
870 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
874 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
877 * This board also had the typo mentioned above in the
878 * Manufacturer DMI field (fixed in BIOS version 1.5), so
879 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
882 .ident = "MSI K9AGM2",
884 DMI_MATCH(DMI_BOARD_VENDOR,
886 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
890 * All BIOS versions for the Asus M3A support 64bit DMA.
891 * (all release versions from 0301 to 1206 were tested)
896 DMI_MATCH(DMI_BOARD_VENDOR,
897 "ASUSTeK Computer INC."),
898 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
903 const struct dmi_system_id *match;
904 int year, month, date;
907 match = dmi_first_match(sysids);
908 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
912 if (!match->driver_data)
915 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
916 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
918 if (strcmp(buf, match->driver_data) >= 0)
922 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
928 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
932 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
934 static const struct dmi_system_id broken_systems[] = {
936 .ident = "HP Compaq nx6310",
938 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
939 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
941 /* PCI slot number of the controller */
942 .driver_data = (void *)0x1FUL,
945 .ident = "HP Compaq 6720s",
947 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
948 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
950 /* PCI slot number of the controller */
951 .driver_data = (void *)0x1FUL,
954 { } /* terminate list */
956 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
959 unsigned long slot = (unsigned long)dmi->driver_data;
960 /* apply the quirk only to on-board controllers */
961 return slot == PCI_SLOT(pdev->devfn);
967 static bool ahci_broken_suspend(struct pci_dev *pdev)
969 static const struct dmi_system_id sysids[] = {
971 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
972 * to the harddisk doesn't become online after
973 * resuming from STR. Warn and fail suspend.
975 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
977 * Use dates instead of versions to match as HP is
978 * apparently recycling both product and version
981 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
986 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
987 DMI_MATCH(DMI_PRODUCT_NAME,
988 "HP Pavilion dv4 Notebook PC"),
990 .driver_data = "20090105", /* F.30 */
995 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
996 DMI_MATCH(DMI_PRODUCT_NAME,
997 "HP Pavilion dv5 Notebook PC"),
999 .driver_data = "20090506", /* F.16 */
1004 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1005 DMI_MATCH(DMI_PRODUCT_NAME,
1006 "HP Pavilion dv6 Notebook PC"),
1008 .driver_data = "20090423", /* F.21 */
1013 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1014 DMI_MATCH(DMI_PRODUCT_NAME,
1015 "HP HDX18 Notebook PC"),
1017 .driver_data = "20090430", /* F.23 */
1020 * Acer eMachines G725 has the same problem. BIOS
1021 * V1.03 is known to be broken. V3.04 is known to
1022 * work. Between, there are V1.06, V2.06 and V3.03
1023 * that we don't have much idea about. For now,
1024 * blacklist anything older than V3.04.
1026 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1031 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1032 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1034 .driver_data = "20091216", /* V3.04 */
1036 { } /* terminate list */
1038 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1039 int year, month, date;
1042 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1045 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1046 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1048 return strcmp(buf, dmi->driver_data) < 0;
1051 static bool ahci_broken_online(struct pci_dev *pdev)
1053 #define ENCODE_BUSDEVFN(bus, slot, func) \
1054 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1055 static const struct dmi_system_id sysids[] = {
1057 * There are several gigabyte boards which use
1058 * SIMG5723s configured as hardware RAID. Certain
1059 * 5723 firmware revisions shipped there keep the link
1060 * online but fail to answer properly to SRST or
1061 * IDENTIFY when no device is attached downstream
1062 * causing libata to retry quite a few times leading
1063 * to excessive detection delay.
1065 * As these firmwares respond to the second reset try
1066 * with invalid device signature, considering unknown
1067 * sig as offline works around the problem acceptably.
1070 .ident = "EP45-DQ6",
1072 DMI_MATCH(DMI_BOARD_VENDOR,
1073 "Gigabyte Technology Co., Ltd."),
1074 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1076 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1079 .ident = "EP45-DS5",
1081 DMI_MATCH(DMI_BOARD_VENDOR,
1082 "Gigabyte Technology Co., Ltd."),
1083 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1085 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1087 { } /* terminate list */
1089 #undef ENCODE_BUSDEVFN
1090 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1096 val = (unsigned long)dmi->driver_data;
1098 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1101 #ifdef CONFIG_ATA_ACPI
1102 static void ahci_gtf_filter_workaround(struct ata_host *host)
1104 static const struct dmi_system_id sysids[] = {
1106 * Aspire 3810T issues a bunch of SATA enable commands
1107 * via _GTF including an invalid one and one which is
1108 * rejected by the device. Among the successful ones
1109 * is FPDMA non-zero offset enable which when enabled
1110 * only on the drive side leads to NCQ command
1111 * failures. Filter it out.
1114 .ident = "Aspire 3810T",
1116 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1117 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1119 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1123 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1124 unsigned int filter;
1130 filter = (unsigned long)dmi->driver_data;
1131 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1132 filter, dmi->ident);
1134 for (i = 0; i < host->n_ports; i++) {
1135 struct ata_port *ap = host->ports[i];
1136 struct ata_link *link;
1137 struct ata_device *dev;
1139 ata_for_each_link(link, ap, EDGE)
1140 ata_for_each_dev(dev, link, ALL)
1141 dev->gtf_filter |= filter;
1145 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1149 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1152 unsigned int maxvec;
1154 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1155 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1157 if ((rc == maxvec) || (rc == 1))
1160 * Assume that advantage of multipe MSIs is negated,
1161 * so fallback to single MSI mode to save resources
1163 pci_disable_msi(pdev);
1164 if (!pci_enable_msi(pdev))
1174 * ahci_host_activate - start AHCI host, request IRQs and register it
1175 * @host: target ATA host
1176 * @irq: base IRQ number to request
1177 * @n_msis: number of MSIs allocated for this host
1178 * @irq_handler: irq_handler used when requesting IRQs
1179 * @irq_flags: irq_flags used when requesting IRQs
1181 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1182 * when multiple MSIs were allocated. That is one MSI per port, starting
1186 * Inherited from calling layer (may sleep).
1189 * 0 on success, -errno otherwise.
1191 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1195 /* Sharing Last Message among several ports is not supported */
1196 if (n_msis < host->n_ports)
1199 rc = ata_host_start(host);
1203 for (i = 0; i < host->n_ports; i++) {
1204 rc = devm_request_threaded_irq(host->dev,
1205 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1206 dev_driver_string(host->dev), host->ports[i]);
1211 for (i = 0; i < host->n_ports; i++)
1212 ata_port_desc(host->ports[i], "irq %d", irq + i);
1214 rc = ata_host_register(host, &ahci_sht);
1216 goto out_free_all_irqs;
1223 for (i--; i >= 0; i--)
1224 devm_free_irq(host->dev, irq + i, host->ports[i]);
1229 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1231 unsigned int board_id = ent->driver_data;
1232 struct ata_port_info pi = ahci_port_info[board_id];
1233 const struct ata_port_info *ppi[] = { &pi, NULL };
1234 struct device *dev = &pdev->dev;
1235 struct ahci_host_priv *hpriv;
1236 struct ata_host *host;
1237 int n_ports, n_msis, i, rc;
1238 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1242 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1244 ata_print_version_once(&pdev->dev, DRV_VERSION);
1246 /* The AHCI driver can only drive the SATA ports, the PATA driver
1247 can drive them all so if both drivers are selected make sure
1248 AHCI stays out of the way */
1249 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1253 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1254 * ahci, use ata_generic instead.
1256 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1257 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1258 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1259 pdev->subsystem_device == 0xcb89)
1262 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1263 * At the moment, we can only use the AHCI mode. Let the users know
1264 * that for SAS drives they're out of luck.
1266 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1267 dev_info(&pdev->dev,
1268 "PDC42819 can only drive SATA devices with this driver\n");
1270 /* Both Connext and Enmotus devices use non-standard BARs */
1271 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1272 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1273 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1274 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1276 /* acquire resources */
1277 rc = pcim_enable_device(pdev);
1281 /* AHCI controllers often implement SFF compatible interface.
1282 * Grab all PCI BARs just in case.
1284 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1286 pcim_pin_device(pdev);
1290 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1291 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1294 /* ICH6s share the same PCI ID for both piix and ahci
1295 * modes. Enabling ahci mode while MAP indicates
1296 * combined mode is a bad idea. Yield to ata_piix.
1298 pci_read_config_byte(pdev, ICH_MAP, &map);
1300 dev_info(&pdev->dev,
1301 "controller is in combined mode, can't enable AHCI mode\n");
1306 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1309 hpriv->flags |= (unsigned long)pi.private_data;
1311 /* MCP65 revision A1 and A2 can't do MSI */
1312 if (board_id == board_ahci_mcp65 &&
1313 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1314 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1316 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1317 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1318 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1320 /* only some SB600s can do 64bit DMA */
1321 if (ahci_sb600_enable_64bit(pdev))
1322 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1324 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1326 n_msis = ahci_init_interrupts(pdev, hpriv);
1328 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1330 /* save initial config */
1331 ahci_pci_save_initial_config(pdev, hpriv);
1334 if (hpriv->cap & HOST_CAP_NCQ) {
1335 pi.flags |= ATA_FLAG_NCQ;
1337 * Auto-activate optimization is supposed to be
1338 * supported on all AHCI controllers indicating NCQ
1339 * capability, but it seems to be broken on some
1340 * chipsets including NVIDIAs.
1342 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1343 pi.flags |= ATA_FLAG_FPDMA_AA;
1346 if (hpriv->cap & HOST_CAP_PMP)
1347 pi.flags |= ATA_FLAG_PMP;
1349 ahci_set_em_messages(hpriv, &pi);
1351 if (ahci_broken_system_poweroff(pdev)) {
1352 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1353 dev_info(&pdev->dev,
1354 "quirky BIOS, skipping spindown on poweroff\n");
1357 if (ahci_broken_suspend(pdev)) {
1358 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1359 dev_warn(&pdev->dev,
1360 "BIOS update required for suspend/resume\n");
1363 if (ahci_broken_online(pdev)) {
1364 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1365 dev_info(&pdev->dev,
1366 "online status unreliable, applying workaround\n");
1369 /* CAP.NP sometimes indicate the index of the last enabled
1370 * port, at other times, that of the last possible port, so
1371 * determining the maximum port number requires looking at
1372 * both CAP.NP and port_map.
1374 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1376 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1379 host->private_data = hpriv;
1381 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1382 host->flags |= ATA_HOST_PARALLEL_SCAN;
1384 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1386 if (pi.flags & ATA_FLAG_EM)
1387 ahci_reset_em(host);
1389 for (i = 0; i < host->n_ports; i++) {
1390 struct ata_port *ap = host->ports[i];
1392 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1393 ata_port_pbar_desc(ap, ahci_pci_bar,
1394 0x100 + ap->port_no * 0x80, "port");
1396 /* set enclosure management message type */
1397 if (ap->flags & ATA_FLAG_EM)
1398 ap->em_message_type = hpriv->em_msg_type;
1401 /* disabled/not-implemented port */
1402 if (!(hpriv->port_map & (1 << i)))
1403 ap->ops = &ata_dummy_port_ops;
1406 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1407 ahci_p5wdh_workaround(host);
1409 /* apply gtf filter quirk */
1410 ahci_gtf_filter_workaround(host);
1412 /* initialize adapter */
1413 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1417 rc = ahci_pci_reset_controller(host);
1421 ahci_pci_init_controller(host);
1422 ahci_pci_print_info(host);
1424 pci_set_master(pdev);
1426 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1427 return ahci_host_activate(host, pdev->irq, n_msis);
1429 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1433 module_pci_driver(ahci_pci_driver);
1435 MODULE_AUTHOR("Jeff Garzik");
1436 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1437 MODULE_LICENSE("GPL");
1438 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1439 MODULE_VERSION(DRV_VERSION);