2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
53 /* Enclosure Management Control */
54 #define EM_CTRL_MSG_TYPE 0x000f0000
56 /* Enclosure Management LED Message Type */
57 #define EM_MSG_LED_HBA_PORT 0x0000000f
58 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
59 #define EM_MSG_LED_VALUE 0xffff0000
60 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
61 #define EM_MSG_LED_VALUE_OFF 0xfff80000
62 #define EM_MSG_LED_VALUE_ON 0x00010000
64 static int ahci_skip_host_reset;
65 static int ahci_ignore_sss;
67 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
68 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
70 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
71 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
73 static int ahci_enable_alpm(struct ata_port *ap,
75 static void ahci_disable_alpm(struct ata_port *ap);
76 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
77 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
79 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
85 AHCI_MAX_SG = 168, /* hardware max is 64K */
86 AHCI_DMA_BOUNDARY = 0xffffffff,
89 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
91 AHCI_CMD_TBL_CDB = 0x40,
92 AHCI_CMD_TBL_HDR_SZ = 0x80,
93 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
94 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
95 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
97 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
99 (AHCI_RX_FIS_SZ * 16),
100 AHCI_IRQ_ON_SG = (1 << 31),
101 AHCI_CMD_ATAPI = (1 << 5),
102 AHCI_CMD_WRITE = (1 << 6),
103 AHCI_CMD_PREFETCH = (1 << 7),
104 AHCI_CMD_RESET = (1 << 8),
105 AHCI_CMD_CLR_BUSY = (1 << 10),
107 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
108 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
109 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
112 board_ahci_vt8251 = 1,
113 board_ahci_ign_iferr = 2,
114 board_ahci_sb600 = 3,
116 board_ahci_sb700 = 5, /* for SB700 and SB800 */
117 board_ahci_mcp65 = 6,
118 board_ahci_nopmp = 7,
119 board_ahci_yesncq = 8,
120 board_ahci_nosntf = 9,
122 /* global controller registers */
123 HOST_CAP = 0x00, /* host capabilities */
124 HOST_CTL = 0x04, /* global host control */
125 HOST_IRQ_STAT = 0x08, /* interrupt status */
126 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
127 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
128 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
129 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
130 HOST_CAP2 = 0x24, /* host capabilities, extended */
133 HOST_RESET = (1 << 0), /* reset controller; self-clear */
134 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
135 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
138 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
139 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
140 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
141 HOST_CAP_PART = (1 << 13), /* Partial state capable */
142 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
143 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
144 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
145 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
146 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
147 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
148 HOST_CAP_LED = (1 << 25), /* Supports activity LED */
149 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
150 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
151 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
152 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
153 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
154 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
157 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
158 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
159 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
161 /* registers for each SATA port */
162 PORT_LST_ADDR = 0x00, /* command list DMA addr */
163 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
164 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
165 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
166 PORT_IRQ_STAT = 0x10, /* interrupt status */
167 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
168 PORT_CMD = 0x18, /* port command */
169 PORT_TFDATA = 0x20, /* taskfile data */
170 PORT_SIG = 0x24, /* device TF signature */
171 PORT_CMD_ISSUE = 0x38, /* command issue */
172 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
173 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
174 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
175 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
176 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
177 PORT_FBS = 0x40, /* FIS-based Switching */
179 /* PORT_IRQ_{STAT,MASK} bits */
180 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
181 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
182 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
183 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
184 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
185 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
186 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
187 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
189 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
190 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
191 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
192 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
193 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
194 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
195 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
196 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
197 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
199 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
205 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
207 PORT_IRQ_HBUS_DATA_ERR,
208 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
209 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
210 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
213 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
214 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
215 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
216 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
217 PORT_CMD_PMP = (1 << 17), /* PMP attached */
218 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
219 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
220 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
221 PORT_CMD_CLO = (1 << 3), /* Command list override */
222 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
223 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
224 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
226 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
227 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
228 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
229 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
231 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
232 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
233 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
234 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
235 PORT_FBS_SDE = (1 << 2), /* FBS single device error */
236 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
237 PORT_FBS_EN = (1 << 0), /* Enable FBS */
239 /* hpriv->flags bits */
240 AHCI_HFLAG_NO_NCQ = (1 << 0),
241 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
242 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
243 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
244 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
245 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
246 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
247 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
248 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
249 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
250 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
251 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
253 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
257 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
258 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
259 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
262 ICH_MAP = 0x90, /* ICH MAP register */
269 EM_CTL_RST = (1 << 9), /* Reset */
270 EM_CTL_TM = (1 << 8), /* Transmit Message */
271 EM_CTL_ALHD = (1 << 26), /* Activity LED */
274 struct ahci_cmd_hdr {
289 struct ahci_em_priv {
290 enum sw_activity blink_policy;
291 struct timer_list timer;
292 unsigned long saved_activity;
293 unsigned long activity;
294 unsigned long led_state;
297 struct ahci_host_priv {
298 void __iomem * mmio; /* bus-independant mem map */
299 unsigned int flags; /* AHCI_HFLAG_* */
300 u32 cap; /* cap to use */
301 u32 cap2; /* cap2 to use */
302 u32 port_map; /* port map to use */
303 u32 saved_cap; /* saved initial cap */
304 u32 saved_cap2; /* saved initial cap2 */
305 u32 saved_port_map; /* saved initial port_map */
306 u32 em_loc; /* enclosure management location */
309 struct ahci_port_priv {
310 struct ata_link *active_link;
311 struct ahci_cmd_hdr *cmd_slot;
312 dma_addr_t cmd_slot_dma;
314 dma_addr_t cmd_tbl_dma;
316 dma_addr_t rx_fis_dma;
317 /* for NCQ spurious interrupt analysis */
318 unsigned int ncq_saw_d2h:1;
319 unsigned int ncq_saw_dmas:1;
320 unsigned int ncq_saw_sdb:1;
321 u32 intr_mask; /* interrupts to enable */
322 bool fbs_supported; /* set iff FBS is supported */
323 bool fbs_enabled; /* set iff FBS is enabled */
324 int fbs_last_dev; /* save FBS.DEV of last FIS */
325 /* enclosure management info per PM slot */
326 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
329 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
330 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
331 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
332 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
333 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
334 static int ahci_port_start(struct ata_port *ap);
335 static void ahci_port_stop(struct ata_port *ap);
336 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
337 static void ahci_qc_prep(struct ata_queued_cmd *qc);
338 static void ahci_freeze(struct ata_port *ap);
339 static void ahci_thaw(struct ata_port *ap);
340 static void ahci_enable_fbs(struct ata_port *ap);
341 static void ahci_disable_fbs(struct ata_port *ap);
342 static void ahci_pmp_attach(struct ata_port *ap);
343 static void ahci_pmp_detach(struct ata_port *ap);
344 static int ahci_softreset(struct ata_link *link, unsigned int *class,
345 unsigned long deadline);
346 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline);
348 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
350 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline);
352 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
353 unsigned long deadline);
354 static void ahci_postreset(struct ata_link *link, unsigned int *class);
355 static void ahci_error_handler(struct ata_port *ap);
356 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
357 static int ahci_port_resume(struct ata_port *ap);
358 static void ahci_dev_config(struct ata_device *dev);
359 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
362 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
363 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
364 static int ahci_pci_device_resume(struct pci_dev *pdev);
366 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
367 static ssize_t ahci_activity_store(struct ata_device *dev,
368 enum sw_activity val);
369 static void ahci_init_sw_activity(struct ata_link *link);
371 static ssize_t ahci_show_host_caps(struct device *dev,
372 struct device_attribute *attr, char *buf);
373 static ssize_t ahci_show_host_cap2(struct device *dev,
374 struct device_attribute *attr, char *buf);
375 static ssize_t ahci_show_host_version(struct device *dev,
376 struct device_attribute *attr, char *buf);
377 static ssize_t ahci_show_port_cmd(struct device *dev,
378 struct device_attribute *attr, char *buf);
380 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
381 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
382 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
383 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
385 static struct device_attribute *ahci_shost_attrs[] = {
386 &dev_attr_link_power_management_policy,
387 &dev_attr_em_message_type,
388 &dev_attr_em_message,
389 &dev_attr_ahci_host_caps,
390 &dev_attr_ahci_host_cap2,
391 &dev_attr_ahci_host_version,
392 &dev_attr_ahci_port_cmd,
396 static struct device_attribute *ahci_sdev_attrs[] = {
397 &dev_attr_sw_activity,
398 &dev_attr_unload_heads,
402 static struct scsi_host_template ahci_sht = {
403 ATA_NCQ_SHT(DRV_NAME),
404 .can_queue = AHCI_MAX_CMDS - 1,
405 .sg_tablesize = AHCI_MAX_SG,
406 .dma_boundary = AHCI_DMA_BOUNDARY,
407 .shost_attrs = ahci_shost_attrs,
408 .sdev_attrs = ahci_sdev_attrs,
411 static struct ata_port_operations ahci_ops = {
412 .inherits = &sata_pmp_port_ops,
414 .qc_defer = ahci_pmp_qc_defer,
415 .qc_prep = ahci_qc_prep,
416 .qc_issue = ahci_qc_issue,
417 .qc_fill_rtf = ahci_qc_fill_rtf,
419 .freeze = ahci_freeze,
421 .softreset = ahci_softreset,
422 .hardreset = ahci_hardreset,
423 .postreset = ahci_postreset,
424 .pmp_softreset = ahci_softreset,
425 .error_handler = ahci_error_handler,
426 .post_internal_cmd = ahci_post_internal_cmd,
427 .dev_config = ahci_dev_config,
429 .scr_read = ahci_scr_read,
430 .scr_write = ahci_scr_write,
431 .pmp_attach = ahci_pmp_attach,
432 .pmp_detach = ahci_pmp_detach,
434 .enable_pm = ahci_enable_alpm,
435 .disable_pm = ahci_disable_alpm,
436 .em_show = ahci_led_show,
437 .em_store = ahci_led_store,
438 .sw_activity_show = ahci_activity_show,
439 .sw_activity_store = ahci_activity_store,
441 .port_suspend = ahci_port_suspend,
442 .port_resume = ahci_port_resume,
444 .port_start = ahci_port_start,
445 .port_stop = ahci_port_stop,
448 static struct ata_port_operations ahci_vt8251_ops = {
449 .inherits = &ahci_ops,
450 .hardreset = ahci_vt8251_hardreset,
453 static struct ata_port_operations ahci_p5wdh_ops = {
454 .inherits = &ahci_ops,
455 .hardreset = ahci_p5wdh_hardreset,
458 static struct ata_port_operations ahci_sb600_ops = {
459 .inherits = &ahci_ops,
460 .softreset = ahci_sb600_softreset,
461 .pmp_softreset = ahci_sb600_softreset,
464 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
466 static const struct ata_port_info ahci_port_info[] = {
469 .flags = AHCI_FLAG_COMMON,
470 .pio_mask = ATA_PIO4,
471 .udma_mask = ATA_UDMA6,
472 .port_ops = &ahci_ops,
474 [board_ahci_vt8251] =
476 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
477 .flags = AHCI_FLAG_COMMON,
478 .pio_mask = ATA_PIO4,
479 .udma_mask = ATA_UDMA6,
480 .port_ops = &ahci_vt8251_ops,
482 [board_ahci_ign_iferr] =
484 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
485 .flags = AHCI_FLAG_COMMON,
486 .pio_mask = ATA_PIO4,
487 .udma_mask = ATA_UDMA6,
488 .port_ops = &ahci_ops,
492 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
493 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
494 AHCI_HFLAG_32BIT_ONLY),
495 .flags = AHCI_FLAG_COMMON,
496 .pio_mask = ATA_PIO4,
497 .udma_mask = ATA_UDMA6,
498 .port_ops = &ahci_sb600_ops,
502 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
503 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
504 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
505 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
506 .pio_mask = ATA_PIO4,
507 .udma_mask = ATA_UDMA6,
508 .port_ops = &ahci_ops,
510 [board_ahci_sb700] = /* for SB700 and SB800 */
512 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
513 .flags = AHCI_FLAG_COMMON,
514 .pio_mask = ATA_PIO4,
515 .udma_mask = ATA_UDMA6,
516 .port_ops = &ahci_sb600_ops,
520 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
521 .flags = AHCI_FLAG_COMMON,
522 .pio_mask = ATA_PIO4,
523 .udma_mask = ATA_UDMA6,
524 .port_ops = &ahci_ops,
528 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
529 .flags = AHCI_FLAG_COMMON,
530 .pio_mask = ATA_PIO4,
531 .udma_mask = ATA_UDMA6,
532 .port_ops = &ahci_ops,
534 [board_ahci_yesncq] =
536 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
537 .flags = AHCI_FLAG_COMMON,
538 .pio_mask = ATA_PIO4,
539 .udma_mask = ATA_UDMA6,
540 .port_ops = &ahci_ops,
542 [board_ahci_nosntf] =
544 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
545 .flags = AHCI_FLAG_COMMON,
546 .pio_mask = ATA_PIO4,
547 .udma_mask = ATA_UDMA6,
548 .port_ops = &ahci_ops,
552 static const struct pci_device_id ahci_pci_tbl[] = {
554 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
555 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
556 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
557 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
558 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
559 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
560 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
561 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
562 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
563 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
564 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
565 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
566 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
567 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
568 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
569 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
570 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
571 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
572 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
573 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
574 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
575 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
576 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
577 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
578 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
579 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
580 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
581 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
582 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
583 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
584 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
585 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
586 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
587 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
588 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
589 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
590 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
591 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
592 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
593 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
594 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
595 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
596 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
597 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
598 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
599 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
601 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
602 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
603 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
606 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
607 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
608 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
609 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
610 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
611 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
612 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
615 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
616 /* AMD is using RAID class only for ahci controllers */
617 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
618 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
621 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
622 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
625 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
626 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
627 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
628 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
629 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
630 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
631 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
632 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
633 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
634 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
635 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
636 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
637 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
638 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
639 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
640 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
641 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
642 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
643 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
644 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
645 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */
646 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_yesncq }, /* Linux ID */
647 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_yesncq }, /* Linux ID */
648 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_yesncq }, /* Linux ID */
649 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_yesncq }, /* Linux ID */
650 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_yesncq }, /* Linux ID */
651 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_yesncq }, /* Linux ID */
652 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_yesncq }, /* Linux ID */
653 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_yesncq }, /* Linux ID */
654 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_yesncq }, /* Linux ID */
655 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_yesncq }, /* Linux ID */
656 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_yesncq }, /* Linux ID */
657 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_yesncq }, /* Linux ID */
658 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_yesncq }, /* Linux ID */
659 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_yesncq }, /* Linux ID */
660 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_yesncq }, /* Linux ID */
661 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
662 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
663 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
664 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
665 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
666 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
667 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
668 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
669 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
670 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
671 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
672 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
673 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
674 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
675 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
676 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
677 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
678 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
679 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
680 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
681 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
682 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
683 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
684 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
685 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
686 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
687 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
688 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
689 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
690 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
691 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
692 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
693 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
694 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
695 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
696 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
697 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
698 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
699 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
700 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
701 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
702 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
703 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
704 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
705 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
706 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
707 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
708 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
711 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
712 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
713 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
716 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
717 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
720 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
722 /* Generic, PCI class code for AHCI */
723 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
724 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
726 { } /* terminate list */
730 static struct pci_driver ahci_pci_driver = {
732 .id_table = ahci_pci_tbl,
733 .probe = ahci_init_one,
734 .remove = ata_pci_remove_one,
736 .suspend = ahci_pci_device_suspend,
737 .resume = ahci_pci_device_resume,
741 static int ahci_em_messages = 1;
742 module_param(ahci_em_messages, int, 0444);
743 /* add other LED protocol types when they become supported */
744 MODULE_PARM_DESC(ahci_em_messages,
745 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
747 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
748 static int marvell_enable;
750 static int marvell_enable = 1;
752 module_param(marvell_enable, int, 0644);
753 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
756 static inline int ahci_nr_ports(u32 cap)
758 return (cap & 0x1f) + 1;
761 static inline void __iomem *__ahci_port_base(struct ata_host *host,
762 unsigned int port_no)
764 struct ahci_host_priv *hpriv = host->private_data;
765 void __iomem *mmio = hpriv->mmio;
767 return mmio + 0x100 + (port_no * 0x80);
770 static inline void __iomem *ahci_port_base(struct ata_port *ap)
772 return __ahci_port_base(ap->host, ap->port_no);
775 static void ahci_enable_ahci(void __iomem *mmio)
780 /* turn on AHCI_EN */
781 tmp = readl(mmio + HOST_CTL);
782 if (tmp & HOST_AHCI_EN)
785 /* Some controllers need AHCI_EN to be written multiple times.
786 * Try a few times before giving up.
788 for (i = 0; i < 5; i++) {
790 writel(tmp, mmio + HOST_CTL);
791 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
792 if (tmp & HOST_AHCI_EN)
800 static ssize_t ahci_show_host_caps(struct device *dev,
801 struct device_attribute *attr, char *buf)
803 struct Scsi_Host *shost = class_to_shost(dev);
804 struct ata_port *ap = ata_shost_to_port(shost);
805 struct ahci_host_priv *hpriv = ap->host->private_data;
807 return sprintf(buf, "%x\n", hpriv->cap);
810 static ssize_t ahci_show_host_cap2(struct device *dev,
811 struct device_attribute *attr, char *buf)
813 struct Scsi_Host *shost = class_to_shost(dev);
814 struct ata_port *ap = ata_shost_to_port(shost);
815 struct ahci_host_priv *hpriv = ap->host->private_data;
817 return sprintf(buf, "%x\n", hpriv->cap2);
820 static ssize_t ahci_show_host_version(struct device *dev,
821 struct device_attribute *attr, char *buf)
823 struct Scsi_Host *shost = class_to_shost(dev);
824 struct ata_port *ap = ata_shost_to_port(shost);
825 struct ahci_host_priv *hpriv = ap->host->private_data;
826 void __iomem *mmio = hpriv->mmio;
828 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
831 static ssize_t ahci_show_port_cmd(struct device *dev,
832 struct device_attribute *attr, char *buf)
834 struct Scsi_Host *shost = class_to_shost(dev);
835 struct ata_port *ap = ata_shost_to_port(shost);
836 void __iomem *port_mmio = ahci_port_base(ap);
838 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
842 * ahci_save_initial_config - Save and fixup initial config values
843 * @dev: target AHCI device
844 * @hpriv: host private area to store config values
845 * @force_port_map: force port map to a specified value
846 * @mask_port_map: mask out particular bits from port map
848 * Some registers containing configuration info might be setup by
849 * BIOS and might be cleared on reset. This function saves the
850 * initial values of those registers into @hpriv such that they
851 * can be restored after controller reset.
853 * If inconsistent, config values are fixed up by this function.
858 static void ahci_save_initial_config(struct device *dev,
859 struct ahci_host_priv *hpriv,
860 unsigned int force_port_map,
861 unsigned int mask_port_map)
863 void __iomem *mmio = hpriv->mmio;
864 u32 cap, cap2, vers, port_map;
867 /* make sure AHCI mode is enabled before accessing CAP */
868 ahci_enable_ahci(mmio);
870 /* Values prefixed with saved_ are written back to host after
871 * reset. Values without are used for driver operation.
873 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
874 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
876 /* CAP2 register is only defined for AHCI 1.2 and later */
877 vers = readl(mmio + HOST_VERSION);
878 if ((vers >> 16) > 1 ||
879 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
880 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
882 hpriv->saved_cap2 = cap2 = 0;
884 /* some chips have errata preventing 64bit use */
885 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
886 dev_printk(KERN_INFO, dev,
887 "controller can't do 64bit DMA, forcing 32bit\n");
891 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
892 dev_printk(KERN_INFO, dev,
893 "controller can't do NCQ, turning off CAP_NCQ\n");
894 cap &= ~HOST_CAP_NCQ;
897 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
898 dev_printk(KERN_INFO, dev,
899 "controller can do NCQ, turning on CAP_NCQ\n");
903 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
904 dev_printk(KERN_INFO, dev,
905 "controller can't do PMP, turning off CAP_PMP\n");
906 cap &= ~HOST_CAP_PMP;
909 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
910 dev_printk(KERN_INFO, dev,
911 "controller can't do SNTF, turning off CAP_SNTF\n");
912 cap &= ~HOST_CAP_SNTF;
915 if (force_port_map && port_map != force_port_map) {
916 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
917 port_map, force_port_map);
918 port_map = force_port_map;
922 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
924 port_map & mask_port_map);
925 port_map &= mask_port_map;
928 /* cross check port_map and cap.n_ports */
932 for (i = 0; i < AHCI_MAX_PORTS; i++)
933 if (port_map & (1 << i))
936 /* If PI has more ports than n_ports, whine, clear
937 * port_map and let it be generated from n_ports.
939 if (map_ports > ahci_nr_ports(cap)) {
940 dev_printk(KERN_WARNING, dev,
941 "implemented port map (0x%x) contains more "
942 "ports than nr_ports (%u), using nr_ports\n",
943 port_map, ahci_nr_ports(cap));
948 /* fabricate port_map from cap.nr_ports */
950 port_map = (1 << ahci_nr_ports(cap)) - 1;
951 dev_printk(KERN_WARNING, dev,
952 "forcing PORTS_IMPL to 0x%x\n", port_map);
954 /* write the fixed up value to the PI register */
955 hpriv->saved_port_map = port_map;
958 /* record values to use during operation */
961 hpriv->port_map = port_map;
964 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
965 struct ahci_host_priv *hpriv)
967 unsigned int force_port_map = 0;
968 unsigned int mask_port_map = 0;
970 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
971 dev_info(&pdev->dev, "JMB361 has only one port\n");
976 * Temporary Marvell 6145 hack: PATA port presence
977 * is asserted through the standard AHCI port
978 * presence register, as bit 4 (counting from 0)
980 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
981 if (pdev->device == 0x6121)
986 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
989 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
994 * ahci_restore_initial_config - Restore initial config
995 * @host: target ATA host
997 * Restore initial config stored by ahci_save_initial_config().
1002 static void ahci_restore_initial_config(struct ata_host *host)
1004 struct ahci_host_priv *hpriv = host->private_data;
1005 void __iomem *mmio = hpriv->mmio;
1007 writel(hpriv->saved_cap, mmio + HOST_CAP);
1008 if (hpriv->saved_cap2)
1009 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
1010 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
1011 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1014 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1016 static const int offset[] = {
1017 [SCR_STATUS] = PORT_SCR_STAT,
1018 [SCR_CONTROL] = PORT_SCR_CTL,
1019 [SCR_ERROR] = PORT_SCR_ERR,
1020 [SCR_ACTIVE] = PORT_SCR_ACT,
1021 [SCR_NOTIFICATION] = PORT_SCR_NTF,
1023 struct ahci_host_priv *hpriv = ap->host->private_data;
1025 if (sc_reg < ARRAY_SIZE(offset) &&
1026 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
1027 return offset[sc_reg];
1031 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1033 void __iomem *port_mmio = ahci_port_base(link->ap);
1034 int offset = ahci_scr_offset(link->ap, sc_reg);
1037 *val = readl(port_mmio + offset);
1043 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1045 void __iomem *port_mmio = ahci_port_base(link->ap);
1046 int offset = ahci_scr_offset(link->ap, sc_reg);
1049 writel(val, port_mmio + offset);
1055 static void ahci_start_engine(struct ata_port *ap)
1057 void __iomem *port_mmio = ahci_port_base(ap);
1061 tmp = readl(port_mmio + PORT_CMD);
1062 tmp |= PORT_CMD_START;
1063 writel(tmp, port_mmio + PORT_CMD);
1064 readl(port_mmio + PORT_CMD); /* flush */
1067 static int ahci_stop_engine(struct ata_port *ap)
1069 void __iomem *port_mmio = ahci_port_base(ap);
1072 tmp = readl(port_mmio + PORT_CMD);
1074 /* check if the HBA is idle */
1075 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
1078 /* setting HBA to idle */
1079 tmp &= ~PORT_CMD_START;
1080 writel(tmp, port_mmio + PORT_CMD);
1082 /* wait for engine to stop. This could be as long as 500 msec */
1083 tmp = ata_wait_register(port_mmio + PORT_CMD,
1084 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
1085 if (tmp & PORT_CMD_LIST_ON)
1091 static void ahci_start_fis_rx(struct ata_port *ap)
1093 void __iomem *port_mmio = ahci_port_base(ap);
1094 struct ahci_host_priv *hpriv = ap->host->private_data;
1095 struct ahci_port_priv *pp = ap->private_data;
1098 /* set FIS registers */
1099 if (hpriv->cap & HOST_CAP_64)
1100 writel((pp->cmd_slot_dma >> 16) >> 16,
1101 port_mmio + PORT_LST_ADDR_HI);
1102 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
1104 if (hpriv->cap & HOST_CAP_64)
1105 writel((pp->rx_fis_dma >> 16) >> 16,
1106 port_mmio + PORT_FIS_ADDR_HI);
1107 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
1109 /* enable FIS reception */
1110 tmp = readl(port_mmio + PORT_CMD);
1111 tmp |= PORT_CMD_FIS_RX;
1112 writel(tmp, port_mmio + PORT_CMD);
1115 readl(port_mmio + PORT_CMD);
1118 static int ahci_stop_fis_rx(struct ata_port *ap)
1120 void __iomem *port_mmio = ahci_port_base(ap);
1123 /* disable FIS reception */
1124 tmp = readl(port_mmio + PORT_CMD);
1125 tmp &= ~PORT_CMD_FIS_RX;
1126 writel(tmp, port_mmio + PORT_CMD);
1128 /* wait for completion, spec says 500ms, give it 1000 */
1129 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1130 PORT_CMD_FIS_ON, 10, 1000);
1131 if (tmp & PORT_CMD_FIS_ON)
1137 static void ahci_power_up(struct ata_port *ap)
1139 struct ahci_host_priv *hpriv = ap->host->private_data;
1140 void __iomem *port_mmio = ahci_port_base(ap);
1143 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1145 /* spin up device */
1146 if (hpriv->cap & HOST_CAP_SSS) {
1147 cmd |= PORT_CMD_SPIN_UP;
1148 writel(cmd, port_mmio + PORT_CMD);
1152 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1155 static void ahci_disable_alpm(struct ata_port *ap)
1157 struct ahci_host_priv *hpriv = ap->host->private_data;
1158 void __iomem *port_mmio = ahci_port_base(ap);
1160 struct ahci_port_priv *pp = ap->private_data;
1162 /* IPM bits should be disabled by libata-core */
1163 /* get the existing command bits */
1164 cmd = readl(port_mmio + PORT_CMD);
1166 /* disable ALPM and ASP */
1167 cmd &= ~PORT_CMD_ASP;
1168 cmd &= ~PORT_CMD_ALPE;
1170 /* force the interface back to active */
1171 cmd |= PORT_CMD_ICC_ACTIVE;
1173 /* write out new cmd value */
1174 writel(cmd, port_mmio + PORT_CMD);
1175 cmd = readl(port_mmio + PORT_CMD);
1177 /* wait 10ms to be sure we've come out of any low power state */
1180 /* clear out any PhyRdy stuff from interrupt status */
1181 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1183 /* go ahead and clean out PhyRdy Change from Serror too */
1184 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1187 * Clear flag to indicate that we should ignore all PhyRdy
1190 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1193 * Enable interrupts on Phy Ready.
1195 pp->intr_mask |= PORT_IRQ_PHYRDY;
1196 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1199 * don't change the link pm policy - we can be called
1200 * just to turn of link pm temporarily
1204 static int ahci_enable_alpm(struct ata_port *ap,
1205 enum link_pm policy)
1207 struct ahci_host_priv *hpriv = ap->host->private_data;
1208 void __iomem *port_mmio = ahci_port_base(ap);
1210 struct ahci_port_priv *pp = ap->private_data;
1213 /* Make sure the host is capable of link power management */
1214 if (!(hpriv->cap & HOST_CAP_ALPM))
1218 case MAX_PERFORMANCE:
1221 * if we came here with NOT_AVAILABLE,
1222 * it just means this is the first time we
1223 * have tried to enable - default to max performance,
1224 * and let the user go to lower power modes on request.
1226 ahci_disable_alpm(ap);
1229 /* configure HBA to enter SLUMBER */
1233 /* configure HBA to enter PARTIAL */
1241 * Disable interrupts on Phy Ready. This keeps us from
1242 * getting woken up due to spurious phy ready interrupts
1243 * TBD - Hot plug should be done via polling now, is
1244 * that even supported?
1246 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1247 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1250 * Set a flag to indicate that we should ignore all PhyRdy
1251 * state changes since these can happen now whenever we
1254 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1256 /* get the existing command bits */
1257 cmd = readl(port_mmio + PORT_CMD);
1260 * Set ASP based on Policy
1265 * Setting this bit will instruct the HBA to aggressively
1266 * enter a lower power link state when it's appropriate and
1267 * based on the value set above for ASP
1269 cmd |= PORT_CMD_ALPE;
1271 /* write out new cmd value */
1272 writel(cmd, port_mmio + PORT_CMD);
1273 cmd = readl(port_mmio + PORT_CMD);
1275 /* IPM bits should be set by libata-core */
1280 static void ahci_power_down(struct ata_port *ap)
1282 struct ahci_host_priv *hpriv = ap->host->private_data;
1283 void __iomem *port_mmio = ahci_port_base(ap);
1286 if (!(hpriv->cap & HOST_CAP_SSS))
1289 /* put device into listen mode, first set PxSCTL.DET to 0 */
1290 scontrol = readl(port_mmio + PORT_SCR_CTL);
1292 writel(scontrol, port_mmio + PORT_SCR_CTL);
1294 /* then set PxCMD.SUD to 0 */
1295 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1296 cmd &= ~PORT_CMD_SPIN_UP;
1297 writel(cmd, port_mmio + PORT_CMD);
1301 static void ahci_start_port(struct ata_port *ap)
1303 struct ahci_port_priv *pp = ap->private_data;
1304 struct ata_link *link;
1305 struct ahci_em_priv *emp;
1309 /* enable FIS reception */
1310 ahci_start_fis_rx(ap);
1313 ahci_start_engine(ap);
1316 if (ap->flags & ATA_FLAG_EM) {
1317 ata_for_each_link(link, ap, EDGE) {
1318 emp = &pp->em_priv[link->pmp];
1320 /* EM Transmit bit maybe busy during init */
1321 for (i = 0; i < EM_MAX_RETRY; i++) {
1322 rc = ahci_transmit_led_message(ap,
1333 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1334 ata_for_each_link(link, ap, EDGE)
1335 ahci_init_sw_activity(link);
1339 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1344 rc = ahci_stop_engine(ap);
1346 *emsg = "failed to stop engine";
1350 /* disable FIS reception */
1351 rc = ahci_stop_fis_rx(ap);
1353 *emsg = "failed stop FIS RX";
1360 static int ahci_reset_controller(struct ata_host *host)
1362 struct ahci_host_priv *hpriv = host->private_data;
1363 void __iomem *mmio = hpriv->mmio;
1366 /* we must be in AHCI mode, before using anything
1367 * AHCI-specific, such as HOST_RESET.
1369 ahci_enable_ahci(mmio);
1371 /* global controller reset */
1372 if (!ahci_skip_host_reset) {
1373 tmp = readl(mmio + HOST_CTL);
1374 if ((tmp & HOST_RESET) == 0) {
1375 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1376 readl(mmio + HOST_CTL); /* flush */
1380 * to perform host reset, OS should set HOST_RESET
1381 * and poll until this bit is read to be "0".
1382 * reset must complete within 1 second, or
1383 * the hardware should be considered fried.
1385 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1386 HOST_RESET, 10, 1000);
1388 if (tmp & HOST_RESET) {
1389 dev_printk(KERN_ERR, host->dev,
1390 "controller reset failed (0x%x)\n", tmp);
1394 /* turn on AHCI mode */
1395 ahci_enable_ahci(mmio);
1397 /* Some registers might be cleared on reset. Restore
1400 ahci_restore_initial_config(host);
1402 dev_printk(KERN_INFO, host->dev,
1403 "skipping global host reset\n");
1408 static int ahci_pci_reset_controller(struct ata_host *host)
1410 struct pci_dev *pdev = to_pci_dev(host->dev);
1412 ahci_reset_controller(host);
1414 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1415 struct ahci_host_priv *hpriv = host->private_data;
1419 pci_read_config_word(pdev, 0x92, &tmp16);
1420 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1421 tmp16 |= hpriv->port_map;
1422 pci_write_config_word(pdev, 0x92, tmp16);
1429 static void ahci_sw_activity(struct ata_link *link)
1431 struct ata_port *ap = link->ap;
1432 struct ahci_port_priv *pp = ap->private_data;
1433 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1435 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1439 if (!timer_pending(&emp->timer))
1440 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1443 static void ahci_sw_activity_blink(unsigned long arg)
1445 struct ata_link *link = (struct ata_link *)arg;
1446 struct ata_port *ap = link->ap;
1447 struct ahci_port_priv *pp = ap->private_data;
1448 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1449 unsigned long led_message = emp->led_state;
1450 u32 activity_led_state;
1451 unsigned long flags;
1453 led_message &= EM_MSG_LED_VALUE;
1454 led_message |= ap->port_no | (link->pmp << 8);
1456 /* check to see if we've had activity. If so,
1457 * toggle state of LED and reset timer. If not,
1458 * turn LED to desired idle state.
1460 spin_lock_irqsave(ap->lock, flags);
1461 if (emp->saved_activity != emp->activity) {
1462 emp->saved_activity = emp->activity;
1463 /* get the current LED state */
1464 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1466 if (activity_led_state)
1467 activity_led_state = 0;
1469 activity_led_state = 1;
1471 /* clear old state */
1472 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1475 led_message |= (activity_led_state << 16);
1476 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1478 /* switch to idle */
1479 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1480 if (emp->blink_policy == BLINK_OFF)
1481 led_message |= (1 << 16);
1483 spin_unlock_irqrestore(ap->lock, flags);
1484 ahci_transmit_led_message(ap, led_message, 4);
1487 static void ahci_init_sw_activity(struct ata_link *link)
1489 struct ata_port *ap = link->ap;
1490 struct ahci_port_priv *pp = ap->private_data;
1491 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1493 /* init activity stats, setup timer */
1494 emp->saved_activity = emp->activity = 0;
1495 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1497 /* check our blink policy and set flag for link if it's enabled */
1498 if (emp->blink_policy)
1499 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1502 static int ahci_reset_em(struct ata_host *host)
1504 struct ahci_host_priv *hpriv = host->private_data;
1505 void __iomem *mmio = hpriv->mmio;
1508 em_ctl = readl(mmio + HOST_EM_CTL);
1509 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1512 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1516 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1519 struct ahci_host_priv *hpriv = ap->host->private_data;
1520 struct ahci_port_priv *pp = ap->private_data;
1521 void __iomem *mmio = hpriv->mmio;
1523 u32 message[] = {0, 0};
1524 unsigned long flags;
1526 struct ahci_em_priv *emp;
1528 /* get the slot number from the message */
1529 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1530 if (pmp < EM_MAX_SLOTS)
1531 emp = &pp->em_priv[pmp];
1535 spin_lock_irqsave(ap->lock, flags);
1538 * if we are still busy transmitting a previous message,
1541 em_ctl = readl(mmio + HOST_EM_CTL);
1542 if (em_ctl & EM_CTL_TM) {
1543 spin_unlock_irqrestore(ap->lock, flags);
1548 * create message header - this is all zero except for
1549 * the message size, which is 4 bytes.
1551 message[0] |= (4 << 8);
1553 /* ignore 0:4 of byte zero, fill in port info yourself */
1554 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1556 /* write message to EM_LOC */
1557 writel(message[0], mmio + hpriv->em_loc);
1558 writel(message[1], mmio + hpriv->em_loc+4);
1560 /* save off new led state for port/slot */
1561 emp->led_state = state;
1564 * tell hardware to transmit the message
1566 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1568 spin_unlock_irqrestore(ap->lock, flags);
1572 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1574 struct ahci_port_priv *pp = ap->private_data;
1575 struct ata_link *link;
1576 struct ahci_em_priv *emp;
1579 ata_for_each_link(link, ap, EDGE) {
1580 emp = &pp->em_priv[link->pmp];
1581 rc += sprintf(buf, "%lx\n", emp->led_state);
1586 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1591 struct ahci_port_priv *pp = ap->private_data;
1592 struct ahci_em_priv *emp;
1594 state = simple_strtoul(buf, NULL, 0);
1596 /* get the slot number from the message */
1597 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1598 if (pmp < EM_MAX_SLOTS)
1599 emp = &pp->em_priv[pmp];
1603 /* mask off the activity bits if we are in sw_activity
1604 * mode, user should turn off sw_activity before setting
1605 * activity led through em_message
1607 if (emp->blink_policy)
1608 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1610 return ahci_transmit_led_message(ap, state, size);
1613 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1615 struct ata_link *link = dev->link;
1616 struct ata_port *ap = link->ap;
1617 struct ahci_port_priv *pp = ap->private_data;
1618 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1619 u32 port_led_state = emp->led_state;
1621 /* save the desired Activity LED behavior */
1624 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1626 /* set the LED to OFF */
1627 port_led_state &= EM_MSG_LED_VALUE_OFF;
1628 port_led_state |= (ap->port_no | (link->pmp << 8));
1629 ahci_transmit_led_message(ap, port_led_state, 4);
1631 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1632 if (val == BLINK_OFF) {
1633 /* set LED to ON for idle */
1634 port_led_state &= EM_MSG_LED_VALUE_OFF;
1635 port_led_state |= (ap->port_no | (link->pmp << 8));
1636 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1637 ahci_transmit_led_message(ap, port_led_state, 4);
1640 emp->blink_policy = val;
1644 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1646 struct ata_link *link = dev->link;
1647 struct ata_port *ap = link->ap;
1648 struct ahci_port_priv *pp = ap->private_data;
1649 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1651 /* display the saved value of activity behavior for this
1654 return sprintf(buf, "%d\n", emp->blink_policy);
1657 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1658 int port_no, void __iomem *mmio,
1659 void __iomem *port_mmio)
1661 const char *emsg = NULL;
1665 /* make sure port is not active */
1666 rc = ahci_deinit_port(ap, &emsg);
1668 dev_warn(dev, "%s (%d)\n", emsg, rc);
1671 tmp = readl(port_mmio + PORT_SCR_ERR);
1672 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1673 writel(tmp, port_mmio + PORT_SCR_ERR);
1675 /* clear port IRQ */
1676 tmp = readl(port_mmio + PORT_IRQ_STAT);
1677 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1679 writel(tmp, port_mmio + PORT_IRQ_STAT);
1681 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1684 static void ahci_init_controller(struct ata_host *host)
1686 struct ahci_host_priv *hpriv = host->private_data;
1687 struct pci_dev *pdev = to_pci_dev(host->dev);
1688 void __iomem *mmio = hpriv->mmio;
1690 void __iomem *port_mmio;
1694 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1695 if (pdev->device == 0x6121)
1699 port_mmio = __ahci_port_base(host, mv);
1701 writel(0, port_mmio + PORT_IRQ_MASK);
1703 /* clear port IRQ */
1704 tmp = readl(port_mmio + PORT_IRQ_STAT);
1705 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1707 writel(tmp, port_mmio + PORT_IRQ_STAT);
1710 for (i = 0; i < host->n_ports; i++) {
1711 struct ata_port *ap = host->ports[i];
1713 port_mmio = ahci_port_base(ap);
1714 if (ata_port_is_dummy(ap))
1717 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1720 tmp = readl(mmio + HOST_CTL);
1721 VPRINTK("HOST_CTL 0x%x\n", tmp);
1722 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1723 tmp = readl(mmio + HOST_CTL);
1724 VPRINTK("HOST_CTL 0x%x\n", tmp);
1727 static void ahci_dev_config(struct ata_device *dev)
1729 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1731 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1732 dev->max_sectors = 255;
1733 ata_dev_printk(dev, KERN_INFO,
1734 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1738 static unsigned int ahci_dev_classify(struct ata_port *ap)
1740 void __iomem *port_mmio = ahci_port_base(ap);
1741 struct ata_taskfile tf;
1744 tmp = readl(port_mmio + PORT_SIG);
1745 tf.lbah = (tmp >> 24) & 0xff;
1746 tf.lbam = (tmp >> 16) & 0xff;
1747 tf.lbal = (tmp >> 8) & 0xff;
1748 tf.nsect = (tmp) & 0xff;
1750 return ata_dev_classify(&tf);
1753 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1756 dma_addr_t cmd_tbl_dma;
1758 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1760 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1761 pp->cmd_slot[tag].status = 0;
1762 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1763 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1766 static int ahci_kick_engine(struct ata_port *ap)
1768 void __iomem *port_mmio = ahci_port_base(ap);
1769 struct ahci_host_priv *hpriv = ap->host->private_data;
1770 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1775 rc = ahci_stop_engine(ap);
1780 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1782 busy = status & (ATA_BUSY | ATA_DRQ);
1783 if (!busy && !sata_pmp_attached(ap)) {
1788 if (!(hpriv->cap & HOST_CAP_CLO)) {
1794 tmp = readl(port_mmio + PORT_CMD);
1795 tmp |= PORT_CMD_CLO;
1796 writel(tmp, port_mmio + PORT_CMD);
1799 tmp = ata_wait_register(port_mmio + PORT_CMD,
1800 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1801 if (tmp & PORT_CMD_CLO)
1804 /* restart engine */
1806 ahci_start_engine(ap);
1810 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1811 struct ata_taskfile *tf, int is_cmd, u16 flags,
1812 unsigned long timeout_msec)
1814 const u32 cmd_fis_len = 5; /* five dwords */
1815 struct ahci_port_priv *pp = ap->private_data;
1816 void __iomem *port_mmio = ahci_port_base(ap);
1817 u8 *fis = pp->cmd_tbl;
1820 /* prep the command */
1821 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1822 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1825 writel(1, port_mmio + PORT_CMD_ISSUE);
1828 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1831 ahci_kick_engine(ap);
1835 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1840 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1841 int pmp, unsigned long deadline,
1842 int (*check_ready)(struct ata_link *link))
1844 struct ata_port *ap = link->ap;
1845 struct ahci_host_priv *hpriv = ap->host->private_data;
1846 const char *reason = NULL;
1847 unsigned long now, msecs;
1848 struct ata_taskfile tf;
1853 /* prepare for SRST (AHCI-1.1 10.4.1) */
1854 rc = ahci_kick_engine(ap);
1855 if (rc && rc != -EOPNOTSUPP)
1856 ata_link_printk(link, KERN_WARNING,
1857 "failed to reset engine (errno=%d)\n", rc);
1859 ata_tf_init(link->device, &tf);
1861 /* issue the first D2H Register FIS */
1864 if (time_after(now, deadline))
1865 msecs = jiffies_to_msecs(deadline - now);
1868 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1869 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1871 reason = "1st FIS failed";
1875 /* spec says at least 5us, but be generous and sleep for 1ms */
1878 /* issue the second D2H Register FIS */
1879 tf.ctl &= ~ATA_SRST;
1880 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1882 /* wait for link to become ready */
1883 rc = ata_wait_after_reset(link, deadline, check_ready);
1884 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1886 * Workaround for cases where link online status can't
1887 * be trusted. Treat device readiness timeout as link
1890 ata_link_printk(link, KERN_INFO,
1891 "device not ready, treating as offline\n");
1892 *class = ATA_DEV_NONE;
1894 /* link occupied, -ENODEV too is an error */
1895 reason = "device not ready";
1898 *class = ahci_dev_classify(ap);
1900 DPRINTK("EXIT, class=%u\n", *class);
1904 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1908 static int ahci_check_ready(struct ata_link *link)
1910 void __iomem *port_mmio = ahci_port_base(link->ap);
1911 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1913 return ata_check_ready(status);
1916 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1917 unsigned long deadline)
1919 int pmp = sata_srst_pmp(link);
1923 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1926 static int ahci_sb600_check_ready(struct ata_link *link)
1928 void __iomem *port_mmio = ahci_port_base(link->ap);
1929 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1930 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1933 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1934 * which can save timeout delay.
1936 if (irq_status & PORT_IRQ_BAD_PMP)
1939 return ata_check_ready(status);
1942 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1943 unsigned long deadline)
1945 struct ata_port *ap = link->ap;
1946 void __iomem *port_mmio = ahci_port_base(ap);
1947 int pmp = sata_srst_pmp(link);
1953 rc = ahci_do_softreset(link, class, pmp, deadline,
1954 ahci_sb600_check_ready);
1957 * Soft reset fails on some ATI chips with IPMS set when PMP
1958 * is enabled but SATA HDD/ODD is connected to SATA port,
1959 * do soft reset again to port 0.
1962 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1963 if (irq_sts & PORT_IRQ_BAD_PMP) {
1964 ata_link_printk(link, KERN_WARNING,
1965 "applying SB600 PMP SRST workaround "
1967 rc = ahci_do_softreset(link, class, 0, deadline,
1975 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1976 unsigned long deadline)
1978 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1979 struct ata_port *ap = link->ap;
1980 struct ahci_port_priv *pp = ap->private_data;
1981 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1982 struct ata_taskfile tf;
1988 ahci_stop_engine(ap);
1990 /* clear D2H reception area to properly wait for D2H FIS */
1991 ata_tf_init(link->device, &tf);
1993 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1995 rc = sata_link_hardreset(link, timing, deadline, &online,
1998 ahci_start_engine(ap);
2001 *class = ahci_dev_classify(ap);
2003 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
2007 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
2008 unsigned long deadline)
2010 struct ata_port *ap = link->ap;
2016 ahci_stop_engine(ap);
2018 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
2019 deadline, &online, NULL);
2021 ahci_start_engine(ap);
2023 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
2025 /* vt8251 doesn't clear BSY on signature FIS reception,
2026 * request follow-up softreset.
2028 return online ? -EAGAIN : rc;
2031 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
2032 unsigned long deadline)
2034 struct ata_port *ap = link->ap;
2035 struct ahci_port_priv *pp = ap->private_data;
2036 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2037 struct ata_taskfile tf;
2041 ahci_stop_engine(ap);
2043 /* clear D2H reception area to properly wait for D2H FIS */
2044 ata_tf_init(link->device, &tf);
2046 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
2048 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
2049 deadline, &online, NULL);
2051 ahci_start_engine(ap);
2053 /* The pseudo configuration device on SIMG4726 attached to
2054 * ASUS P5W-DH Deluxe doesn't send signature FIS after
2055 * hardreset if no device is attached to the first downstream
2056 * port && the pseudo device locks up on SRST w/ PMP==0. To
2057 * work around this, wait for !BSY only briefly. If BSY isn't
2058 * cleared, perform CLO and proceed to IDENTIFY (achieved by
2059 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
2061 * Wait for two seconds. Devices attached to downstream port
2062 * which can't process the following IDENTIFY after this will
2063 * have to be reset again. For most cases, this should
2064 * suffice while making probing snappish enough.
2067 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
2070 ahci_kick_engine(ap);
2075 static void ahci_postreset(struct ata_link *link, unsigned int *class)
2077 struct ata_port *ap = link->ap;
2078 void __iomem *port_mmio = ahci_port_base(ap);
2081 ata_std_postreset(link, class);
2083 /* Make sure port's ATAPI bit is set appropriately */
2084 new_tmp = tmp = readl(port_mmio + PORT_CMD);
2085 if (*class == ATA_DEV_ATAPI)
2086 new_tmp |= PORT_CMD_ATAPI;
2088 new_tmp &= ~PORT_CMD_ATAPI;
2089 if (new_tmp != tmp) {
2090 writel(new_tmp, port_mmio + PORT_CMD);
2091 readl(port_mmio + PORT_CMD); /* flush */
2095 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
2097 struct scatterlist *sg;
2098 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
2104 * Next, the S/G list.
2106 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2107 dma_addr_t addr = sg_dma_address(sg);
2108 u32 sg_len = sg_dma_len(sg);
2110 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
2111 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
2112 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
2118 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
2120 struct ata_port *ap = qc->ap;
2121 struct ahci_port_priv *pp = ap->private_data;
2123 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
2124 return ata_std_qc_defer(qc);
2126 return sata_pmp_qc_defer_cmd_switch(qc);
2129 static void ahci_qc_prep(struct ata_queued_cmd *qc)
2131 struct ata_port *ap = qc->ap;
2132 struct ahci_port_priv *pp = ap->private_data;
2133 int is_atapi = ata_is_atapi(qc->tf.protocol);
2136 const u32 cmd_fis_len = 5; /* five dwords */
2137 unsigned int n_elem;
2140 * Fill in command table information. First, the header,
2141 * a SATA Register - Host to Device command FIS.
2143 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2145 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
2147 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2148 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
2152 if (qc->flags & ATA_QCFLAG_DMAMAP)
2153 n_elem = ahci_fill_sg(qc, cmd_tbl);
2156 * Fill in command slot information.
2158 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
2159 if (qc->tf.flags & ATA_TFLAG_WRITE)
2160 opts |= AHCI_CMD_WRITE;
2162 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
2164 ahci_fill_cmd_slot(pp, qc->tag, opts);
2167 static void ahci_fbs_dec_intr(struct ata_port *ap)
2169 struct ahci_port_priv *pp = ap->private_data;
2170 void __iomem *port_mmio = ahci_port_base(ap);
2171 u32 fbs = readl(port_mmio + PORT_FBS);
2175 BUG_ON(!pp->fbs_enabled);
2177 /* time to wait for DEC is not specified by AHCI spec,
2178 * add a retry loop for safety.
2180 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
2181 fbs = readl(port_mmio + PORT_FBS);
2182 while ((fbs & PORT_FBS_DEC) && retries--) {
2184 fbs = readl(port_mmio + PORT_FBS);
2187 if (fbs & PORT_FBS_DEC)
2188 dev_printk(KERN_ERR, ap->host->dev,
2189 "failed to clear device error\n");
2192 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
2194 struct ahci_host_priv *hpriv = ap->host->private_data;
2195 struct ahci_port_priv *pp = ap->private_data;
2196 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2197 struct ata_link *link = NULL;
2198 struct ata_queued_cmd *active_qc;
2199 struct ata_eh_info *active_ehi;
2200 bool fbs_need_dec = false;
2203 /* determine active link with error */
2204 if (pp->fbs_enabled) {
2205 void __iomem *port_mmio = ahci_port_base(ap);
2206 u32 fbs = readl(port_mmio + PORT_FBS);
2207 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
2209 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
2210 ata_link_online(&ap->pmp_link[pmp])) {
2211 link = &ap->pmp_link[pmp];
2212 fbs_need_dec = true;
2216 ata_for_each_link(link, ap, EDGE)
2217 if (ata_link_active(link))
2223 active_qc = ata_qc_from_tag(ap, link->active_tag);
2224 active_ehi = &link->eh_info;
2226 /* record irq stat */
2227 ata_ehi_clear_desc(host_ehi);
2228 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
2230 /* AHCI needs SError cleared; otherwise, it might lock up */
2231 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2232 ahci_scr_write(&ap->link, SCR_ERROR, serror);
2233 host_ehi->serror |= serror;
2235 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
2236 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
2237 irq_stat &= ~PORT_IRQ_IF_ERR;
2239 if (irq_stat & PORT_IRQ_TF_ERR) {
2240 /* If qc is active, charge it; otherwise, the active
2241 * link. There's no active qc on NCQ errors. It will
2242 * be determined by EH by reading log page 10h.
2245 active_qc->err_mask |= AC_ERR_DEV;
2247 active_ehi->err_mask |= AC_ERR_DEV;
2249 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2250 host_ehi->serror &= ~SERR_INTERNAL;
2253 if (irq_stat & PORT_IRQ_UNK_FIS) {
2254 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2256 active_ehi->err_mask |= AC_ERR_HSM;
2257 active_ehi->action |= ATA_EH_RESET;
2258 ata_ehi_push_desc(active_ehi,
2259 "unknown FIS %08x %08x %08x %08x" ,
2260 unk[0], unk[1], unk[2], unk[3]);
2263 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2264 active_ehi->err_mask |= AC_ERR_HSM;
2265 active_ehi->action |= ATA_EH_RESET;
2266 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2269 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2270 host_ehi->err_mask |= AC_ERR_HOST_BUS;
2271 host_ehi->action |= ATA_EH_RESET;
2272 ata_ehi_push_desc(host_ehi, "host bus error");
2275 if (irq_stat & PORT_IRQ_IF_ERR) {
2277 active_ehi->err_mask |= AC_ERR_DEV;
2279 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2280 host_ehi->action |= ATA_EH_RESET;
2283 ata_ehi_push_desc(host_ehi, "interface fatal error");
2286 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2287 ata_ehi_hotplugged(host_ehi);
2288 ata_ehi_push_desc(host_ehi, "%s",
2289 irq_stat & PORT_IRQ_CONNECT ?
2290 "connection status changed" : "PHY RDY changed");
2293 /* okay, let's hand over to EH */
2295 if (irq_stat & PORT_IRQ_FREEZE)
2296 ata_port_freeze(ap);
2297 else if (fbs_need_dec) {
2298 ata_link_abort(link);
2299 ahci_fbs_dec_intr(ap);
2304 static void ahci_port_intr(struct ata_port *ap)
2306 void __iomem *port_mmio = ahci_port_base(ap);
2307 struct ata_eh_info *ehi = &ap->link.eh_info;
2308 struct ahci_port_priv *pp = ap->private_data;
2309 struct ahci_host_priv *hpriv = ap->host->private_data;
2310 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2311 u32 status, qc_active = 0;
2314 status = readl(port_mmio + PORT_IRQ_STAT);
2315 writel(status, port_mmio + PORT_IRQ_STAT);
2317 /* ignore BAD_PMP while resetting */
2318 if (unlikely(resetting))
2319 status &= ~PORT_IRQ_BAD_PMP;
2321 /* If we are getting PhyRdy, this is
2322 * just a power state change, we should
2323 * clear out this, plus the PhyRdy/Comm
2324 * Wake bits from Serror
2326 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2327 (status & PORT_IRQ_PHYRDY)) {
2328 status &= ~PORT_IRQ_PHYRDY;
2329 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2332 if (unlikely(status & PORT_IRQ_ERROR)) {
2333 ahci_error_intr(ap, status);
2337 if (status & PORT_IRQ_SDB_FIS) {
2338 /* If SNotification is available, leave notification
2339 * handling to sata_async_notification(). If not,
2340 * emulate it by snooping SDB FIS RX area.
2342 * Snooping FIS RX area is probably cheaper than
2343 * poking SNotification but some constrollers which
2344 * implement SNotification, ICH9 for example, don't
2345 * store AN SDB FIS into receive area.
2347 if (hpriv->cap & HOST_CAP_SNTF)
2348 sata_async_notification(ap);
2350 /* If the 'N' bit in word 0 of the FIS is set,
2351 * we just received asynchronous notification.
2352 * Tell libata about it.
2354 * Lack of SNotification should not appear in
2355 * ahci 1.2, so the workaround is unnecessary
2356 * when FBS is enabled.
2358 if (pp->fbs_enabled)
2361 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2362 u32 f0 = le32_to_cpu(f[0]);
2364 sata_async_notification(ap);
2369 /* pp->active_link is not reliable once FBS is enabled, both
2370 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
2371 * NCQ and non-NCQ commands may be in flight at the same time.
2373 if (pp->fbs_enabled) {
2374 if (ap->qc_active) {
2375 qc_active = readl(port_mmio + PORT_SCR_ACT);
2376 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
2379 /* pp->active_link is valid iff any command is in flight */
2380 if (ap->qc_active && pp->active_link->sactive)
2381 qc_active = readl(port_mmio + PORT_SCR_ACT);
2383 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2386 rc = ata_qc_complete_multiple(ap, qc_active);
2388 /* while resetting, invalid completions are expected */
2389 if (unlikely(rc < 0 && !resetting)) {
2390 ehi->err_mask |= AC_ERR_HSM;
2391 ehi->action |= ATA_EH_RESET;
2392 ata_port_freeze(ap);
2396 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2398 struct ata_host *host = dev_instance;
2399 struct ahci_host_priv *hpriv;
2400 unsigned int i, handled = 0;
2402 u32 irq_stat, irq_masked;
2406 hpriv = host->private_data;
2409 /* sigh. 0xffffffff is a valid return from h/w */
2410 irq_stat = readl(mmio + HOST_IRQ_STAT);
2414 irq_masked = irq_stat & hpriv->port_map;
2416 spin_lock(&host->lock);
2418 for (i = 0; i < host->n_ports; i++) {
2419 struct ata_port *ap;
2421 if (!(irq_masked & (1 << i)))
2424 ap = host->ports[i];
2427 VPRINTK("port %u\n", i);
2429 VPRINTK("port %u (no irq)\n", i);
2430 if (ata_ratelimit())
2431 dev_printk(KERN_WARNING, host->dev,
2432 "interrupt on disabled port %u\n", i);
2438 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2439 * it should be cleared after all the port events are cleared;
2440 * otherwise, it will raise a spurious interrupt after each
2441 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2444 * Also, use the unmasked value to clear interrupt as spurious
2445 * pending event on a dummy port might cause screaming IRQ.
2447 writel(irq_stat, mmio + HOST_IRQ_STAT);
2449 spin_unlock(&host->lock);
2453 return IRQ_RETVAL(handled);
2456 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2458 struct ata_port *ap = qc->ap;
2459 void __iomem *port_mmio = ahci_port_base(ap);
2460 struct ahci_port_priv *pp = ap->private_data;
2462 /* Keep track of the currently active link. It will be used
2463 * in completion path to determine whether NCQ phase is in
2466 pp->active_link = qc->dev->link;
2468 if (qc->tf.protocol == ATA_PROT_NCQ)
2469 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2471 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2472 u32 fbs = readl(port_mmio + PORT_FBS);
2473 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2474 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2475 writel(fbs, port_mmio + PORT_FBS);
2476 pp->fbs_last_dev = qc->dev->link->pmp;
2479 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2481 ahci_sw_activity(qc->dev->link);
2486 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2488 struct ahci_port_priv *pp = qc->ap->private_data;
2489 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2491 if (pp->fbs_enabled)
2492 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2494 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2498 static void ahci_freeze(struct ata_port *ap)
2500 void __iomem *port_mmio = ahci_port_base(ap);
2503 writel(0, port_mmio + PORT_IRQ_MASK);
2506 static void ahci_thaw(struct ata_port *ap)
2508 struct ahci_host_priv *hpriv = ap->host->private_data;
2509 void __iomem *mmio = hpriv->mmio;
2510 void __iomem *port_mmio = ahci_port_base(ap);
2512 struct ahci_port_priv *pp = ap->private_data;
2515 tmp = readl(port_mmio + PORT_IRQ_STAT);
2516 writel(tmp, port_mmio + PORT_IRQ_STAT);
2517 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2519 /* turn IRQ back on */
2520 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2523 static void ahci_error_handler(struct ata_port *ap)
2525 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2526 /* restart engine */
2527 ahci_stop_engine(ap);
2528 ahci_start_engine(ap);
2531 sata_pmp_error_handler(ap);
2534 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2536 struct ata_port *ap = qc->ap;
2538 /* make DMA engine forget about the failed command */
2539 if (qc->flags & ATA_QCFLAG_FAILED)
2540 ahci_kick_engine(ap);
2543 static void ahci_enable_fbs(struct ata_port *ap)
2545 struct ahci_port_priv *pp = ap->private_data;
2546 void __iomem *port_mmio = ahci_port_base(ap);
2550 if (!pp->fbs_supported)
2553 fbs = readl(port_mmio + PORT_FBS);
2554 if (fbs & PORT_FBS_EN) {
2555 pp->fbs_enabled = true;
2556 pp->fbs_last_dev = -1; /* initialization */
2560 rc = ahci_stop_engine(ap);
2564 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2565 fbs = readl(port_mmio + PORT_FBS);
2566 if (fbs & PORT_FBS_EN) {
2567 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
2568 pp->fbs_enabled = true;
2569 pp->fbs_last_dev = -1; /* initialization */
2571 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
2573 ahci_start_engine(ap);
2576 static void ahci_disable_fbs(struct ata_port *ap)
2578 struct ahci_port_priv *pp = ap->private_data;
2579 void __iomem *port_mmio = ahci_port_base(ap);
2583 if (!pp->fbs_supported)
2586 fbs = readl(port_mmio + PORT_FBS);
2587 if ((fbs & PORT_FBS_EN) == 0) {
2588 pp->fbs_enabled = false;
2592 rc = ahci_stop_engine(ap);
2596 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2597 fbs = readl(port_mmio + PORT_FBS);
2598 if (fbs & PORT_FBS_EN)
2599 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
2601 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
2602 pp->fbs_enabled = false;
2605 ahci_start_engine(ap);
2608 static void ahci_pmp_attach(struct ata_port *ap)
2610 void __iomem *port_mmio = ahci_port_base(ap);
2611 struct ahci_port_priv *pp = ap->private_data;
2614 cmd = readl(port_mmio + PORT_CMD);
2615 cmd |= PORT_CMD_PMP;
2616 writel(cmd, port_mmio + PORT_CMD);
2618 ahci_enable_fbs(ap);
2620 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2621 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2624 static void ahci_pmp_detach(struct ata_port *ap)
2626 void __iomem *port_mmio = ahci_port_base(ap);
2627 struct ahci_port_priv *pp = ap->private_data;
2630 ahci_disable_fbs(ap);
2632 cmd = readl(port_mmio + PORT_CMD);
2633 cmd &= ~PORT_CMD_PMP;
2634 writel(cmd, port_mmio + PORT_CMD);
2636 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2637 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2640 static int ahci_port_resume(struct ata_port *ap)
2643 ahci_start_port(ap);
2645 if (sata_pmp_attached(ap))
2646 ahci_pmp_attach(ap);
2648 ahci_pmp_detach(ap);
2654 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2656 const char *emsg = NULL;
2659 rc = ahci_deinit_port(ap, &emsg);
2661 ahci_power_down(ap);
2663 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2664 ahci_start_port(ap);
2670 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2672 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2673 struct ahci_host_priv *hpriv = host->private_data;
2674 void __iomem *mmio = hpriv->mmio;
2677 if (mesg.event & PM_EVENT_SUSPEND &&
2678 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2679 dev_printk(KERN_ERR, &pdev->dev,
2680 "BIOS update required for suspend/resume\n");
2684 if (mesg.event & PM_EVENT_SLEEP) {
2685 /* AHCI spec rev1.1 section 8.3.3:
2686 * Software must disable interrupts prior to requesting a
2687 * transition of the HBA to D3 state.
2689 ctl = readl(mmio + HOST_CTL);
2690 ctl &= ~HOST_IRQ_EN;
2691 writel(ctl, mmio + HOST_CTL);
2692 readl(mmio + HOST_CTL); /* flush */
2695 return ata_pci_device_suspend(pdev, mesg);
2698 static int ahci_pci_device_resume(struct pci_dev *pdev)
2700 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2703 rc = ata_pci_device_do_resume(pdev);
2707 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2708 rc = ahci_pci_reset_controller(host);
2712 ahci_init_controller(host);
2715 ata_host_resume(host);
2721 static int ahci_port_start(struct ata_port *ap)
2723 struct ahci_host_priv *hpriv = ap->host->private_data;
2724 struct device *dev = ap->host->dev;
2725 struct ahci_port_priv *pp;
2728 size_t dma_sz, rx_fis_sz;
2730 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2734 /* check FBS capability */
2735 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2736 void __iomem *port_mmio = ahci_port_base(ap);
2737 u32 cmd = readl(port_mmio + PORT_CMD);
2738 if (cmd & PORT_CMD_FBSCP)
2739 pp->fbs_supported = true;
2741 dev_printk(KERN_WARNING, dev,
2742 "The port is not capable of FBS\n");
2745 if (pp->fbs_supported) {
2746 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2747 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2749 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2750 rx_fis_sz = AHCI_RX_FIS_SZ;
2753 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2756 memset(mem, 0, dma_sz);
2759 * First item in chunk of DMA memory: 32-slot command table,
2760 * 32 bytes each in size
2763 pp->cmd_slot_dma = mem_dma;
2765 mem += AHCI_CMD_SLOT_SZ;
2766 mem_dma += AHCI_CMD_SLOT_SZ;
2769 * Second item: Received-FIS area
2772 pp->rx_fis_dma = mem_dma;
2775 mem_dma += rx_fis_sz;
2778 * Third item: data area for storing a single command
2779 * and its scatter-gather table
2782 pp->cmd_tbl_dma = mem_dma;
2785 * Save off initial list of interrupts to be enabled.
2786 * This could be changed later
2788 pp->intr_mask = DEF_PORT_IRQ;
2790 ap->private_data = pp;
2792 /* engage engines, captain */
2793 return ahci_port_resume(ap);
2796 static void ahci_port_stop(struct ata_port *ap)
2798 const char *emsg = NULL;
2801 /* de-initialize port */
2802 rc = ahci_deinit_port(ap, &emsg);
2804 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2807 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2812 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2813 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2815 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2817 dev_printk(KERN_ERR, &pdev->dev,
2818 "64-bit DMA enable failed\n");
2823 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2825 dev_printk(KERN_ERR, &pdev->dev,
2826 "32-bit DMA enable failed\n");
2829 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2831 dev_printk(KERN_ERR, &pdev->dev,
2832 "32-bit consistent DMA enable failed\n");
2839 static void ahci_print_info(struct ata_host *host)
2841 struct ahci_host_priv *hpriv = host->private_data;
2842 struct pci_dev *pdev = to_pci_dev(host->dev);
2843 void __iomem *mmio = hpriv->mmio;
2844 u32 vers, cap, cap2, impl, speed;
2845 const char *speed_s;
2849 vers = readl(mmio + HOST_VERSION);
2852 impl = hpriv->port_map;
2854 speed = (cap >> 20) & 0xf;
2857 else if (speed == 2)
2859 else if (speed == 3)
2864 pci_read_config_word(pdev, 0x0a, &cc);
2865 if (cc == PCI_CLASS_STORAGE_IDE)
2867 else if (cc == PCI_CLASS_STORAGE_SATA)
2869 else if (cc == PCI_CLASS_STORAGE_RAID)
2874 dev_printk(KERN_INFO, &pdev->dev,
2875 "AHCI %02x%02x.%02x%02x "
2876 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2879 (vers >> 24) & 0xff,
2880 (vers >> 16) & 0xff,
2884 ((cap >> 8) & 0x1f) + 1,
2890 dev_printk(KERN_INFO, &pdev->dev,
2897 cap & HOST_CAP_64 ? "64bit " : "",
2898 cap & HOST_CAP_NCQ ? "ncq " : "",
2899 cap & HOST_CAP_SNTF ? "sntf " : "",
2900 cap & HOST_CAP_MPS ? "ilck " : "",
2901 cap & HOST_CAP_SSS ? "stag " : "",
2902 cap & HOST_CAP_ALPM ? "pm " : "",
2903 cap & HOST_CAP_LED ? "led " : "",
2904 cap & HOST_CAP_CLO ? "clo " : "",
2905 cap & HOST_CAP_ONLY ? "only " : "",
2906 cap & HOST_CAP_PMP ? "pmp " : "",
2907 cap & HOST_CAP_FBS ? "fbs " : "",
2908 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2909 cap & HOST_CAP_SSC ? "slum " : "",
2910 cap & HOST_CAP_PART ? "part " : "",
2911 cap & HOST_CAP_CCC ? "ccc " : "",
2912 cap & HOST_CAP_EMS ? "ems " : "",
2913 cap & HOST_CAP_SXS ? "sxs " : "",
2914 cap2 & HOST_CAP2_APST ? "apst " : "",
2915 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2916 cap2 & HOST_CAP2_BOH ? "boh " : ""
2920 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2921 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2922 * support PMP and the 4726 either directly exports the device
2923 * attached to the first downstream port or acts as a hardware storage
2924 * controller and emulate a single ATA device (can be RAID 0/1 or some
2925 * other configuration).
2927 * When there's no device attached to the first downstream port of the
2928 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2929 * configure the 4726. However, ATA emulation of the device is very
2930 * lame. It doesn't send signature D2H Reg FIS after the initial
2931 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2933 * The following function works around the problem by always using
2934 * hardreset on the port and not depending on receiving signature FIS
2935 * afterward. If signature FIS isn't received soon, ATA class is
2936 * assumed without follow-up softreset.
2938 static void ahci_p5wdh_workaround(struct ata_host *host)
2940 static struct dmi_system_id sysids[] = {
2942 .ident = "P5W DH Deluxe",
2944 DMI_MATCH(DMI_SYS_VENDOR,
2945 "ASUSTEK COMPUTER INC"),
2946 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2951 struct pci_dev *pdev = to_pci_dev(host->dev);
2953 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2954 dmi_check_system(sysids)) {
2955 struct ata_port *ap = host->ports[1];
2957 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2958 "Deluxe on-board SIMG4726 workaround\n");
2960 ap->ops = &ahci_p5wdh_ops;
2961 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2965 /* only some SB600 ahci controllers can do 64bit DMA */
2966 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
2968 static const struct dmi_system_id sysids[] = {
2970 * The oldest version known to be broken is 0901 and
2971 * working is 1501 which was released on 2007-10-26.
2972 * Enable 64bit DMA on 1501 and anything newer.
2974 * Please read bko#9412 for more info.
2977 .ident = "ASUS M2A-VM",
2979 DMI_MATCH(DMI_BOARD_VENDOR,
2980 "ASUSTeK Computer INC."),
2981 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2983 .driver_data = "20071026", /* yyyymmdd */
2986 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
2987 * support 64bit DMA.
2989 * BIOS versions earlier than 1.5 had the Manufacturer DMI
2990 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
2991 * This spelling mistake was fixed in BIOS version 1.5, so
2992 * 1.5 and later have the Manufacturer as
2993 * "MICRO-STAR INTERNATIONAL CO.,LTD".
2994 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
2996 * BIOS versions earlier than 1.9 had a Board Product Name
2997 * DMI field of "MS-7376". This was changed to be
2998 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
2999 * match on DMI_BOARD_NAME of "MS-7376".
3002 .ident = "MSI K9A2 Platinum",
3004 DMI_MATCH(DMI_BOARD_VENDOR,
3005 "MICRO-STAR INTER"),
3006 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
3011 const struct dmi_system_id *match;
3012 int year, month, date;
3015 match = dmi_first_match(sysids);
3016 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
3020 if (!match->driver_data)
3023 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
3024 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
3026 if (strcmp(buf, match->driver_data) >= 0)
3029 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
3030 "forcing 32bit DMA, update BIOS\n", match->ident);
3035 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
3040 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
3042 static const struct dmi_system_id broken_systems[] = {
3044 .ident = "HP Compaq nx6310",
3046 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3047 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
3049 /* PCI slot number of the controller */
3050 .driver_data = (void *)0x1FUL,
3053 .ident = "HP Compaq 6720s",
3055 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3056 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
3058 /* PCI slot number of the controller */
3059 .driver_data = (void *)0x1FUL,
3062 { } /* terminate list */
3064 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
3067 unsigned long slot = (unsigned long)dmi->driver_data;
3068 /* apply the quirk only to on-board controllers */
3069 return slot == PCI_SLOT(pdev->devfn);
3075 static bool ahci_broken_suspend(struct pci_dev *pdev)
3077 static const struct dmi_system_id sysids[] = {
3079 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
3080 * to the harddisk doesn't become online after
3081 * resuming from STR. Warn and fail suspend.
3083 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
3085 * Use dates instead of versions to match as HP is
3086 * apparently recycling both product and version
3089 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
3094 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3095 DMI_MATCH(DMI_PRODUCT_NAME,
3096 "HP Pavilion dv4 Notebook PC"),
3098 .driver_data = "20090105", /* F.30 */
3103 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3104 DMI_MATCH(DMI_PRODUCT_NAME,
3105 "HP Pavilion dv5 Notebook PC"),
3107 .driver_data = "20090506", /* F.16 */
3112 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3113 DMI_MATCH(DMI_PRODUCT_NAME,
3114 "HP Pavilion dv6 Notebook PC"),
3116 .driver_data = "20090423", /* F.21 */
3121 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3122 DMI_MATCH(DMI_PRODUCT_NAME,
3123 "HP HDX18 Notebook PC"),
3125 .driver_data = "20090430", /* F.23 */
3128 * Acer eMachines G725 has the same problem. BIOS
3129 * V1.03 is known to be broken. V3.04 is known to
3130 * work. Inbetween, there are V1.06, V2.06 and V3.03
3131 * that we don't have much idea about. For now,
3132 * blacklist anything older than V3.04.
3134 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
3139 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
3140 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
3142 .driver_data = "20091216", /* V3.04 */
3144 { } /* terminate list */
3146 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3147 int year, month, date;
3150 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
3153 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
3154 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
3156 return strcmp(buf, dmi->driver_data) < 0;
3159 static bool ahci_broken_online(struct pci_dev *pdev)
3161 #define ENCODE_BUSDEVFN(bus, slot, func) \
3162 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
3163 static const struct dmi_system_id sysids[] = {
3165 * There are several gigabyte boards which use
3166 * SIMG5723s configured as hardware RAID. Certain
3167 * 5723 firmware revisions shipped there keep the link
3168 * online but fail to answer properly to SRST or
3169 * IDENTIFY when no device is attached downstream
3170 * causing libata to retry quite a few times leading
3171 * to excessive detection delay.
3173 * As these firmwares respond to the second reset try
3174 * with invalid device signature, considering unknown
3175 * sig as offline works around the problem acceptably.
3178 .ident = "EP45-DQ6",
3180 DMI_MATCH(DMI_BOARD_VENDOR,
3181 "Gigabyte Technology Co., Ltd."),
3182 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
3184 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
3187 .ident = "EP45-DS5",
3189 DMI_MATCH(DMI_BOARD_VENDOR,
3190 "Gigabyte Technology Co., Ltd."),
3191 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
3193 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
3195 { } /* terminate list */
3197 #undef ENCODE_BUSDEVFN
3198 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3204 val = (unsigned long)dmi->driver_data;
3206 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
3209 #ifdef CONFIG_ATA_ACPI
3210 static void ahci_gtf_filter_workaround(struct ata_host *host)
3212 static const struct dmi_system_id sysids[] = {
3214 * Aspire 3810T issues a bunch of SATA enable commands
3215 * via _GTF including an invalid one and one which is
3216 * rejected by the device. Among the successful ones
3217 * is FPDMA non-zero offset enable which when enabled
3218 * only on the drive side leads to NCQ command
3219 * failures. Filter it out.
3222 .ident = "Aspire 3810T",
3224 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
3225 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
3227 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
3231 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3232 unsigned int filter;
3238 filter = (unsigned long)dmi->driver_data;
3239 dev_printk(KERN_INFO, host->dev,
3240 "applying extra ACPI _GTF filter 0x%x for %s\n",
3241 filter, dmi->ident);
3243 for (i = 0; i < host->n_ports; i++) {
3244 struct ata_port *ap = host->ports[i];
3245 struct ata_link *link;
3246 struct ata_device *dev;
3248 ata_for_each_link(link, ap, EDGE)
3249 ata_for_each_dev(dev, link, ALL)
3250 dev->gtf_filter |= filter;
3254 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
3258 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3260 static int printed_version;
3261 unsigned int board_id = ent->driver_data;
3262 struct ata_port_info pi = ahci_port_info[board_id];
3263 const struct ata_port_info *ppi[] = { &pi, NULL };
3264 struct device *dev = &pdev->dev;
3265 struct ahci_host_priv *hpriv;
3266 struct ata_host *host;
3271 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
3273 if (!printed_version++)
3274 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
3276 /* The AHCI driver can only drive the SATA ports, the PATA driver
3277 can drive them all so if both drivers are selected make sure
3278 AHCI stays out of the way */
3279 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
3282 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
3283 * At the moment, we can only use the AHCI mode. Let the users know
3284 * that for SAS drives they're out of luck.
3286 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
3287 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
3288 "can only drive SATA devices with this driver\n");
3290 /* acquire resources */
3291 rc = pcim_enable_device(pdev);
3295 /* AHCI controllers often implement SFF compatible interface.
3296 * Grab all PCI BARs just in case.
3298 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
3300 pcim_pin_device(pdev);
3304 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
3305 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
3308 /* ICH6s share the same PCI ID for both piix and ahci
3309 * modes. Enabling ahci mode while MAP indicates
3310 * combined mode is a bad idea. Yield to ata_piix.
3312 pci_read_config_byte(pdev, ICH_MAP, &map);
3314 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
3315 "combined mode, can't enable AHCI mode\n");
3320 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
3323 hpriv->flags |= (unsigned long)pi.private_data;
3325 /* MCP65 revision A1 and A2 can't do MSI */
3326 if (board_id == board_ahci_mcp65 &&
3327 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
3328 hpriv->flags |= AHCI_HFLAG_NO_MSI;
3330 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
3331 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
3332 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
3334 /* only some SB600s can do 64bit DMA */
3335 if (ahci_sb600_enable_64bit(pdev))
3336 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
3338 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
3341 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
3343 /* save initial config */
3344 ahci_pci_save_initial_config(pdev, hpriv);
3347 if (hpriv->cap & HOST_CAP_NCQ) {
3348 pi.flags |= ATA_FLAG_NCQ;
3349 /* Auto-activate optimization is supposed to be supported on
3350 all AHCI controllers indicating NCQ support, but it seems
3351 to be broken at least on some NVIDIA MCP79 chipsets.
3352 Until we get info on which NVIDIA chipsets don't have this
3353 issue, if any, disable AA on all NVIDIA AHCIs. */
3354 if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
3355 pi.flags |= ATA_FLAG_FPDMA_AA;
3358 if (hpriv->cap & HOST_CAP_PMP)
3359 pi.flags |= ATA_FLAG_PMP;
3361 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
3363 void __iomem *mmio = hpriv->mmio;
3364 u32 em_loc = readl(mmio + HOST_EM_LOC);
3365 u32 em_ctl = readl(mmio + HOST_EM_CTL);
3367 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
3369 /* we only support LED message type right now */
3370 if ((messages & 0x01) && (ahci_em_messages == 1)) {
3372 hpriv->em_loc = ((em_loc >> 16) * 4);
3373 pi.flags |= ATA_FLAG_EM;
3374 if (!(em_ctl & EM_CTL_ALHD))
3375 pi.flags |= ATA_FLAG_SW_ACTIVITY;
3379 if (ahci_broken_system_poweroff(pdev)) {
3380 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
3381 dev_info(&pdev->dev,
3382 "quirky BIOS, skipping spindown on poweroff\n");
3385 if (ahci_broken_suspend(pdev)) {
3386 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
3387 dev_printk(KERN_WARNING, &pdev->dev,
3388 "BIOS update required for suspend/resume\n");
3391 if (ahci_broken_online(pdev)) {
3392 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
3393 dev_info(&pdev->dev,
3394 "online status unreliable, applying workaround\n");
3397 /* CAP.NP sometimes indicate the index of the last enabled
3398 * port, at other times, that of the last possible port, so
3399 * determining the maximum port number requires looking at
3400 * both CAP.NP and port_map.
3402 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
3404 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3407 host->private_data = hpriv;
3409 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
3410 host->flags |= ATA_HOST_PARALLEL_SCAN;
3412 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
3414 if (pi.flags & ATA_FLAG_EM)
3415 ahci_reset_em(host);
3417 for (i = 0; i < host->n_ports; i++) {
3418 struct ata_port *ap = host->ports[i];
3420 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3421 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3422 0x100 + ap->port_no * 0x80, "port");
3424 /* set initial link pm policy */
3425 ap->pm_policy = NOT_AVAILABLE;
3427 /* set enclosure management message type */
3428 if (ap->flags & ATA_FLAG_EM)
3429 ap->em_message_type = ahci_em_messages;
3432 /* disabled/not-implemented port */
3433 if (!(hpriv->port_map & (1 << i)))
3434 ap->ops = &ata_dummy_port_ops;
3437 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3438 ahci_p5wdh_workaround(host);
3440 /* apply gtf filter quirk */
3441 ahci_gtf_filter_workaround(host);
3443 /* initialize adapter */
3444 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
3448 rc = ahci_pci_reset_controller(host);
3452 ahci_init_controller(host);
3453 ahci_print_info(host);
3455 pci_set_master(pdev);
3456 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3460 static int __init ahci_init(void)
3462 return pci_register_driver(&ahci_pci_driver);
3465 static void __exit ahci_exit(void)
3467 pci_unregister_driver(&ahci_pci_driver);
3471 MODULE_AUTHOR("Jeff Garzik");
3472 MODULE_DESCRIPTION("AHCI SATA low-level driver");
3473 MODULE_LICENSE("GPL");
3474 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
3475 MODULE_VERSION(DRV_VERSION);
3477 module_init(ahci_init);
3478 module_exit(ahci_exit);