2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
62 /* board IDs by feature in alphabetical order */
70 /* board IDs for specific chipsets in alphabetical order */
77 board_ahci_sb700, /* for SB700 and SB800 */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
98 static int ahci_pci_device_resume(struct pci_dev *pdev);
101 static struct scsi_host_template ahci_sht = {
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
120 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
225 static const struct pci_device_id ahci_pci_tbl[] = {
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
288 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
289 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
291 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
292 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
293 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
294 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
296 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
297 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
299 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
300 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
304 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
305 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
309 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
311 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
313 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
319 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
320 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
321 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
322 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
323 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
328 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
338 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
340 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
341 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
342 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
344 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
348 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
349 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
353 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
354 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
355 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
356 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
357 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
358 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
359 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
360 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
361 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
363 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
364 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
365 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
366 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
367 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
368 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
369 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
370 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
371 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
372 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
374 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
375 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
376 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
380 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
386 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
387 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
388 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
389 /* JMicron 362B and 362C have an AHCI function with IDE class code */
390 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
391 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
392 /* May need to update quirk_jmicron_async_suspend() for additions */
395 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
396 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
397 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
398 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
399 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
405 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
406 /* AMD is using RAID class only for ahci controllers */
407 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
408 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
411 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
412 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
415 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
418 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
436 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
437 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
438 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
476 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
477 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
488 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
489 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
490 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
502 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
503 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
505 /* ST Microelectronics */
506 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
509 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
510 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
511 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
512 .class = PCI_CLASS_STORAGE_SATA_AHCI,
513 .class_mask = 0xffffff,
514 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
515 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
516 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
517 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
518 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
521 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
522 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
523 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
525 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
527 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
529 .driver_data = board_ahci_yes_fbs },
530 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
531 .driver_data = board_ahci_yes_fbs },
532 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
533 .driver_data = board_ahci_yes_fbs },
534 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
535 .driver_data = board_ahci_yes_fbs },
536 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
537 .driver_data = board_ahci_yes_fbs },
540 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
541 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
544 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
545 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
546 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
547 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
548 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
549 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
552 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
553 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
555 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
556 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
559 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
561 /* Generic, PCI class code for AHCI */
562 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
563 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
565 { } /* terminate list */
569 static struct pci_driver ahci_pci_driver = {
571 .id_table = ahci_pci_tbl,
572 .probe = ahci_init_one,
573 .remove = ata_pci_remove_one,
575 .suspend = ahci_pci_device_suspend,
576 .resume = ahci_pci_device_resume,
580 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
581 static int marvell_enable;
583 static int marvell_enable = 1;
585 module_param(marvell_enable, int, 0644);
586 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
589 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
590 struct ahci_host_priv *hpriv)
592 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
593 dev_info(&pdev->dev, "JMB361 has only one port\n");
594 hpriv->force_port_map = 1;
598 * Temporary Marvell 6145 hack: PATA port presence
599 * is asserted through the standard AHCI port
600 * presence register, as bit 4 (counting from 0)
602 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
603 if (pdev->device == 0x6121)
604 hpriv->mask_port_map = 0x3;
606 hpriv->mask_port_map = 0xf;
608 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
611 ahci_save_initial_config(&pdev->dev, hpriv);
614 static int ahci_pci_reset_controller(struct ata_host *host)
616 struct pci_dev *pdev = to_pci_dev(host->dev);
618 ahci_reset_controller(host);
620 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
621 struct ahci_host_priv *hpriv = host->private_data;
625 pci_read_config_word(pdev, 0x92, &tmp16);
626 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
627 tmp16 |= hpriv->port_map;
628 pci_write_config_word(pdev, 0x92, tmp16);
635 static void ahci_pci_init_controller(struct ata_host *host)
637 struct ahci_host_priv *hpriv = host->private_data;
638 struct pci_dev *pdev = to_pci_dev(host->dev);
639 void __iomem *port_mmio;
643 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
644 if (pdev->device == 0x6121)
648 port_mmio = __ahci_port_base(host, mv);
650 writel(0, port_mmio + PORT_IRQ_MASK);
653 tmp = readl(port_mmio + PORT_IRQ_STAT);
654 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
656 writel(tmp, port_mmio + PORT_IRQ_STAT);
659 ahci_init_controller(host);
662 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
663 unsigned long deadline)
665 struct ata_port *ap = link->ap;
666 struct ahci_host_priv *hpriv = ap->host->private_data;
672 ahci_stop_engine(ap);
674 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
675 deadline, &online, NULL);
677 hpriv->start_engine(ap);
679 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
681 /* vt8251 doesn't clear BSY on signature FIS reception,
682 * request follow-up softreset.
684 return online ? -EAGAIN : rc;
687 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
688 unsigned long deadline)
690 struct ata_port *ap = link->ap;
691 struct ahci_port_priv *pp = ap->private_data;
692 struct ahci_host_priv *hpriv = ap->host->private_data;
693 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
694 struct ata_taskfile tf;
698 ahci_stop_engine(ap);
700 /* clear D2H reception area to properly wait for D2H FIS */
701 ata_tf_init(link->device, &tf);
702 tf.command = ATA_BUSY;
703 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
705 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
706 deadline, &online, NULL);
708 hpriv->start_engine(ap);
710 /* The pseudo configuration device on SIMG4726 attached to
711 * ASUS P5W-DH Deluxe doesn't send signature FIS after
712 * hardreset if no device is attached to the first downstream
713 * port && the pseudo device locks up on SRST w/ PMP==0. To
714 * work around this, wait for !BSY only briefly. If BSY isn't
715 * cleared, perform CLO and proceed to IDENTIFY (achieved by
716 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
718 * Wait for two seconds. Devices attached to downstream port
719 * which can't process the following IDENTIFY after this will
720 * have to be reset again. For most cases, this should
721 * suffice while making probing snappish enough.
724 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
727 ahci_kick_engine(ap);
733 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
735 * It has been observed with some SSDs that the timing of events in the
736 * link synchronization phase can leave the port in a state that can not
737 * be recovered by a SATA-hard-reset alone. The failing signature is
738 * SStatus.DET stuck at 1 ("Device presence detected but Phy
739 * communication not established"). It was found that unloading and
740 * reloading the driver when this problem occurs allows the drive
741 * connection to be recovered (DET advanced to 0x3). The critical
742 * component of reloading the driver is that the port state machines are
743 * reset by bouncing "port enable" in the AHCI PCS configuration
744 * register. So, reproduce that effect by bouncing a port whenever we
745 * see DET==1 after a reset.
747 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
748 unsigned long deadline)
750 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
751 struct ata_port *ap = link->ap;
752 struct ahci_port_priv *pp = ap->private_data;
753 struct ahci_host_priv *hpriv = ap->host->private_data;
754 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
755 unsigned long tmo = deadline - jiffies;
756 struct ata_taskfile tf;
762 ahci_stop_engine(ap);
764 for (i = 0; i < 2; i++) {
767 int port = ap->port_no;
768 struct ata_host *host = ap->host;
769 struct pci_dev *pdev = to_pci_dev(host->dev);
771 /* clear D2H reception area to properly wait for D2H FIS */
772 ata_tf_init(link->device, &tf);
773 tf.command = ATA_BUSY;
774 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
776 rc = sata_link_hardreset(link, timing, deadline, &online,
779 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
780 (sstatus & 0xf) != 1)
783 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
786 pci_read_config_word(pdev, 0x92, &val);
788 pci_write_config_word(pdev, 0x92, val);
789 ata_msleep(ap, 1000);
791 pci_write_config_word(pdev, 0x92, val);
795 hpriv->start_engine(ap);
798 *class = ahci_dev_classify(ap);
800 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
806 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
808 struct ata_host *host = pci_get_drvdata(pdev);
809 struct ahci_host_priv *hpriv = host->private_data;
810 void __iomem *mmio = hpriv->mmio;
813 if (mesg.event & PM_EVENT_SUSPEND &&
814 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
816 "BIOS update required for suspend/resume\n");
820 if (mesg.event & PM_EVENT_SLEEP) {
821 /* AHCI spec rev1.1 section 8.3.3:
822 * Software must disable interrupts prior to requesting a
823 * transition of the HBA to D3 state.
825 ctl = readl(mmio + HOST_CTL);
827 writel(ctl, mmio + HOST_CTL);
828 readl(mmio + HOST_CTL); /* flush */
831 return ata_pci_device_suspend(pdev, mesg);
834 static int ahci_pci_device_resume(struct pci_dev *pdev)
836 struct ata_host *host = pci_get_drvdata(pdev);
839 rc = ata_pci_device_do_resume(pdev);
843 /* Apple BIOS helpfully mangles the registers on resume */
844 if (is_mcp89_apple(pdev))
845 ahci_mcp89_apple_enable(pdev);
847 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
848 rc = ahci_pci_reset_controller(host);
852 ahci_pci_init_controller(host);
855 ata_host_resume(host);
861 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
866 * If the device fixup already set the dma_mask to some non-standard
867 * value, don't extend it here. This happens on STA2X11, for example.
869 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
873 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
874 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
876 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
879 "64-bit DMA enable failed\n");
884 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
886 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
889 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
892 "32-bit consistent DMA enable failed\n");
899 static void ahci_pci_print_info(struct ata_host *host)
901 struct pci_dev *pdev = to_pci_dev(host->dev);
905 pci_read_config_word(pdev, 0x0a, &cc);
906 if (cc == PCI_CLASS_STORAGE_IDE)
908 else if (cc == PCI_CLASS_STORAGE_SATA)
910 else if (cc == PCI_CLASS_STORAGE_RAID)
915 ahci_print_info(host, scc_s);
918 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
919 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
920 * support PMP and the 4726 either directly exports the device
921 * attached to the first downstream port or acts as a hardware storage
922 * controller and emulate a single ATA device (can be RAID 0/1 or some
923 * other configuration).
925 * When there's no device attached to the first downstream port of the
926 * 4726, "Config Disk" appears, which is a pseudo ATA device to
927 * configure the 4726. However, ATA emulation of the device is very
928 * lame. It doesn't send signature D2H Reg FIS after the initial
929 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
931 * The following function works around the problem by always using
932 * hardreset on the port and not depending on receiving signature FIS
933 * afterward. If signature FIS isn't received soon, ATA class is
934 * assumed without follow-up softreset.
936 static void ahci_p5wdh_workaround(struct ata_host *host)
938 static const struct dmi_system_id sysids[] = {
940 .ident = "P5W DH Deluxe",
942 DMI_MATCH(DMI_SYS_VENDOR,
943 "ASUSTEK COMPUTER INC"),
944 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
949 struct pci_dev *pdev = to_pci_dev(host->dev);
951 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
952 dmi_check_system(sysids)) {
953 struct ata_port *ap = host->ports[1];
956 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
958 ap->ops = &ahci_p5wdh_ops;
959 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
964 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
965 * booting in BIOS compatibility mode. We restore the registers but not ID.
967 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
971 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
973 pci_read_config_dword(pdev, 0xf8, &val);
975 /* the following changes the device ID, but appears not to affect function */
976 /* val = (val & ~0xf0000000) | 0x80000000; */
977 pci_write_config_dword(pdev, 0xf8, val);
979 pci_read_config_dword(pdev, 0x54c, &val);
981 pci_write_config_dword(pdev, 0x54c, val);
983 pci_read_config_dword(pdev, 0x4a4, &val);
986 pci_write_config_dword(pdev, 0x4a4, val);
988 pci_read_config_dword(pdev, 0x54c, &val);
990 pci_write_config_dword(pdev, 0x54c, val);
992 pci_read_config_dword(pdev, 0xf8, &val);
994 pci_write_config_dword(pdev, 0xf8, val);
997 static bool is_mcp89_apple(struct pci_dev *pdev)
999 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1000 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1001 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1002 pdev->subsystem_device == 0xcb89;
1005 /* only some SB600 ahci controllers can do 64bit DMA */
1006 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1008 static const struct dmi_system_id sysids[] = {
1010 * The oldest version known to be broken is 0901 and
1011 * working is 1501 which was released on 2007-10-26.
1012 * Enable 64bit DMA on 1501 and anything newer.
1014 * Please read bko#9412 for more info.
1017 .ident = "ASUS M2A-VM",
1019 DMI_MATCH(DMI_BOARD_VENDOR,
1020 "ASUSTeK Computer INC."),
1021 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1023 .driver_data = "20071026", /* yyyymmdd */
1026 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1027 * support 64bit DMA.
1029 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1030 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1031 * This spelling mistake was fixed in BIOS version 1.5, so
1032 * 1.5 and later have the Manufacturer as
1033 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1034 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1036 * BIOS versions earlier than 1.9 had a Board Product Name
1037 * DMI field of "MS-7376". This was changed to be
1038 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1039 * match on DMI_BOARD_NAME of "MS-7376".
1042 .ident = "MSI K9A2 Platinum",
1044 DMI_MATCH(DMI_BOARD_VENDOR,
1045 "MICRO-STAR INTER"),
1046 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1050 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1053 * This board also had the typo mentioned above in the
1054 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1055 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1058 .ident = "MSI K9AGM2",
1060 DMI_MATCH(DMI_BOARD_VENDOR,
1061 "MICRO-STAR INTER"),
1062 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1066 * All BIOS versions for the Asus M3A support 64bit DMA.
1067 * (all release versions from 0301 to 1206 were tested)
1070 .ident = "ASUS M3A",
1072 DMI_MATCH(DMI_BOARD_VENDOR,
1073 "ASUSTeK Computer INC."),
1074 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1079 const struct dmi_system_id *match;
1080 int year, month, date;
1083 match = dmi_first_match(sysids);
1084 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1088 if (!match->driver_data)
1091 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1092 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1094 if (strcmp(buf, match->driver_data) >= 0)
1097 dev_warn(&pdev->dev,
1098 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1104 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1108 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1110 static const struct dmi_system_id broken_systems[] = {
1112 .ident = "HP Compaq nx6310",
1114 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1115 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1117 /* PCI slot number of the controller */
1118 .driver_data = (void *)0x1FUL,
1121 .ident = "HP Compaq 6720s",
1123 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1124 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1126 /* PCI slot number of the controller */
1127 .driver_data = (void *)0x1FUL,
1130 { } /* terminate list */
1132 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1135 unsigned long slot = (unsigned long)dmi->driver_data;
1136 /* apply the quirk only to on-board controllers */
1137 return slot == PCI_SLOT(pdev->devfn);
1143 static bool ahci_broken_suspend(struct pci_dev *pdev)
1145 static const struct dmi_system_id sysids[] = {
1147 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1148 * to the harddisk doesn't become online after
1149 * resuming from STR. Warn and fail suspend.
1151 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1153 * Use dates instead of versions to match as HP is
1154 * apparently recycling both product and version
1157 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1162 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1163 DMI_MATCH(DMI_PRODUCT_NAME,
1164 "HP Pavilion dv4 Notebook PC"),
1166 .driver_data = "20090105", /* F.30 */
1171 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1172 DMI_MATCH(DMI_PRODUCT_NAME,
1173 "HP Pavilion dv5 Notebook PC"),
1175 .driver_data = "20090506", /* F.16 */
1180 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1181 DMI_MATCH(DMI_PRODUCT_NAME,
1182 "HP Pavilion dv6 Notebook PC"),
1184 .driver_data = "20090423", /* F.21 */
1189 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1190 DMI_MATCH(DMI_PRODUCT_NAME,
1191 "HP HDX18 Notebook PC"),
1193 .driver_data = "20090430", /* F.23 */
1196 * Acer eMachines G725 has the same problem. BIOS
1197 * V1.03 is known to be broken. V3.04 is known to
1198 * work. Between, there are V1.06, V2.06 and V3.03
1199 * that we don't have much idea about. For now,
1200 * blacklist anything older than V3.04.
1202 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1207 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1208 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1210 .driver_data = "20091216", /* V3.04 */
1212 { } /* terminate list */
1214 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1215 int year, month, date;
1218 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1221 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1222 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1224 return strcmp(buf, dmi->driver_data) < 0;
1227 static bool ahci_broken_online(struct pci_dev *pdev)
1229 #define ENCODE_BUSDEVFN(bus, slot, func) \
1230 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1231 static const struct dmi_system_id sysids[] = {
1233 * There are several gigabyte boards which use
1234 * SIMG5723s configured as hardware RAID. Certain
1235 * 5723 firmware revisions shipped there keep the link
1236 * online but fail to answer properly to SRST or
1237 * IDENTIFY when no device is attached downstream
1238 * causing libata to retry quite a few times leading
1239 * to excessive detection delay.
1241 * As these firmwares respond to the second reset try
1242 * with invalid device signature, considering unknown
1243 * sig as offline works around the problem acceptably.
1246 .ident = "EP45-DQ6",
1248 DMI_MATCH(DMI_BOARD_VENDOR,
1249 "Gigabyte Technology Co., Ltd."),
1250 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1252 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1255 .ident = "EP45-DS5",
1257 DMI_MATCH(DMI_BOARD_VENDOR,
1258 "Gigabyte Technology Co., Ltd."),
1259 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1261 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1263 { } /* terminate list */
1265 #undef ENCODE_BUSDEVFN
1266 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1272 val = (unsigned long)dmi->driver_data;
1274 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1277 static bool ahci_broken_devslp(struct pci_dev *pdev)
1279 /* device with broken DEVSLP but still showing SDS capability */
1280 static const struct pci_device_id ids[] = {
1281 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1285 return pci_match_id(ids, pdev);
1288 #ifdef CONFIG_ATA_ACPI
1289 static void ahci_gtf_filter_workaround(struct ata_host *host)
1291 static const struct dmi_system_id sysids[] = {
1293 * Aspire 3810T issues a bunch of SATA enable commands
1294 * via _GTF including an invalid one and one which is
1295 * rejected by the device. Among the successful ones
1296 * is FPDMA non-zero offset enable which when enabled
1297 * only on the drive side leads to NCQ command
1298 * failures. Filter it out.
1301 .ident = "Aspire 3810T",
1303 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1304 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1306 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 unsigned int filter;
1317 filter = (unsigned long)dmi->driver_data;
1318 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1319 filter, dmi->ident);
1321 for (i = 0; i < host->n_ports; i++) {
1322 struct ata_port *ap = host->ports[i];
1323 struct ata_link *link;
1324 struct ata_device *dev;
1326 ata_for_each_link(link, ap, EDGE)
1327 ata_for_each_dev(dev, link, ALL)
1328 dev->gtf_filter |= filter;
1332 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1337 * ahci_init_msix() only implements single MSI-X support, not multiple
1338 * MSI-X per-port interrupts. This is needed for host controllers that only
1339 * have MSI-X support implemented, but no MSI or intx.
1341 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1342 struct ahci_host_priv *hpriv)
1345 struct msix_entry entry = {};
1347 /* Do not init MSI-X if MSI is disabled for the device */
1348 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1351 nvec = pci_msix_vec_count(pdev);
1361 * There can be more than one vector (e.g. for error detection or
1362 * hdd hotplug). Only the first vector (entry.entry = 0) is used.
1364 rc = pci_enable_msix_exact(pdev, &entry, 1);
1368 hpriv->irq = entry.vector;
1373 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1379 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1380 struct ahci_host_priv *hpriv)
1384 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1387 nvec = pci_msi_vec_count(pdev);
1392 * If number of MSIs is less than number of ports then Sharing Last
1393 * Message mode could be enforced. In this case assume that advantage
1394 * of multipe MSIs is negated and use single MSI mode instead.
1399 rc = pci_enable_msi_exact(pdev, nvec);
1405 /* fallback to single MSI mode if the controller enforced MRSM mode */
1406 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1407 pci_disable_msi(pdev);
1408 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1413 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1420 rc = pci_enable_msi(pdev);
1424 hpriv->irq = pdev->irq;
1429 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1430 struct ahci_host_priv *hpriv)
1434 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1439 * Currently, MSI-X support only implements single IRQ mode and
1440 * exists for controllers which can't do other types of IRQ. Only
1441 * set it up if MSI fails.
1443 nvec = ahci_init_msix(pdev, n_ports, hpriv);
1447 /* lagacy intx interrupts */
1449 hpriv->irq = pdev->irq;
1454 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1456 unsigned int board_id = ent->driver_data;
1457 struct ata_port_info pi = ahci_port_info[board_id];
1458 const struct ata_port_info *ppi[] = { &pi, NULL };
1459 struct device *dev = &pdev->dev;
1460 struct ahci_host_priv *hpriv;
1461 struct ata_host *host;
1463 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1467 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1469 ata_print_version_once(&pdev->dev, DRV_VERSION);
1471 /* The AHCI driver can only drive the SATA ports, the PATA driver
1472 can drive them all so if both drivers are selected make sure
1473 AHCI stays out of the way */
1474 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1477 /* Apple BIOS on MCP89 prevents us using AHCI */
1478 if (is_mcp89_apple(pdev))
1479 ahci_mcp89_apple_enable(pdev);
1481 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1482 * At the moment, we can only use the AHCI mode. Let the users know
1483 * that for SAS drives they're out of luck.
1485 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1486 dev_info(&pdev->dev,
1487 "PDC42819 can only drive SATA devices with this driver\n");
1489 /* Some devices use non-standard BARs */
1490 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1491 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1492 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1493 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1494 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1495 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1497 /* acquire resources */
1498 rc = pcim_enable_device(pdev);
1502 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1503 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1506 /* ICH6s share the same PCI ID for both piix and ahci
1507 * modes. Enabling ahci mode while MAP indicates
1508 * combined mode is a bad idea. Yield to ata_piix.
1510 pci_read_config_byte(pdev, ICH_MAP, &map);
1512 dev_info(&pdev->dev,
1513 "controller is in combined mode, can't enable AHCI mode\n");
1518 /* AHCI controllers often implement SFF compatible interface.
1519 * Grab all PCI BARs just in case.
1521 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1523 pcim_pin_device(pdev);
1527 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1530 hpriv->flags |= (unsigned long)pi.private_data;
1532 /* MCP65 revision A1 and A2 can't do MSI */
1533 if (board_id == board_ahci_mcp65 &&
1534 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1535 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1537 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1538 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1539 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1541 /* only some SB600s can do 64bit DMA */
1542 if (ahci_sb600_enable_64bit(pdev))
1543 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1545 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1547 /* must set flag prior to save config in order to take effect */
1548 if (ahci_broken_devslp(pdev))
1549 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1551 /* save initial config */
1552 ahci_pci_save_initial_config(pdev, hpriv);
1555 if (hpriv->cap & HOST_CAP_NCQ) {
1556 pi.flags |= ATA_FLAG_NCQ;
1558 * Auto-activate optimization is supposed to be
1559 * supported on all AHCI controllers indicating NCQ
1560 * capability, but it seems to be broken on some
1561 * chipsets including NVIDIAs.
1563 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1564 pi.flags |= ATA_FLAG_FPDMA_AA;
1567 * All AHCI controllers should be forward-compatible
1568 * with the new auxiliary field. This code should be
1569 * conditionalized if any buggy AHCI controllers are
1572 pi.flags |= ATA_FLAG_FPDMA_AUX;
1575 if (hpriv->cap & HOST_CAP_PMP)
1576 pi.flags |= ATA_FLAG_PMP;
1578 ahci_set_em_messages(hpriv, &pi);
1580 if (ahci_broken_system_poweroff(pdev)) {
1581 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1582 dev_info(&pdev->dev,
1583 "quirky BIOS, skipping spindown on poweroff\n");
1586 if (ahci_broken_suspend(pdev)) {
1587 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1588 dev_warn(&pdev->dev,
1589 "BIOS update required for suspend/resume\n");
1592 if (ahci_broken_online(pdev)) {
1593 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1594 dev_info(&pdev->dev,
1595 "online status unreliable, applying workaround\n");
1598 /* CAP.NP sometimes indicate the index of the last enabled
1599 * port, at other times, that of the last possible port, so
1600 * determining the maximum port number requires looking at
1601 * both CAP.NP and port_map.
1603 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1605 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1608 host->private_data = hpriv;
1610 ahci_init_interrupts(pdev, n_ports, hpriv);
1612 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1613 host->flags |= ATA_HOST_PARALLEL_SCAN;
1615 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1617 if (pi.flags & ATA_FLAG_EM)
1618 ahci_reset_em(host);
1620 for (i = 0; i < host->n_ports; i++) {
1621 struct ata_port *ap = host->ports[i];
1623 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1624 ata_port_pbar_desc(ap, ahci_pci_bar,
1625 0x100 + ap->port_no * 0x80, "port");
1627 /* set enclosure management message type */
1628 if (ap->flags & ATA_FLAG_EM)
1629 ap->em_message_type = hpriv->em_msg_type;
1632 /* disabled/not-implemented port */
1633 if (!(hpriv->port_map & (1 << i)))
1634 ap->ops = &ata_dummy_port_ops;
1637 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1638 ahci_p5wdh_workaround(host);
1640 /* apply gtf filter quirk */
1641 ahci_gtf_filter_workaround(host);
1643 /* initialize adapter */
1644 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1648 rc = ahci_pci_reset_controller(host);
1652 ahci_pci_init_controller(host);
1653 ahci_pci_print_info(host);
1655 pci_set_master(pdev);
1657 return ahci_host_activate(host, &ahci_sht);
1660 module_pci_driver(ahci_pci_driver);
1662 MODULE_AUTHOR("Jeff Garzik");
1663 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1664 MODULE_LICENSE("GPL");
1665 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1666 MODULE_VERSION(DRV_VERSION);