2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
60 /* board IDs by feature in alphabetical order */
66 /* board IDs for specific chipsets in alphabetical order */
72 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
88 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89 static int ahci_pci_device_resume(struct pci_dev *pdev);
92 static struct scsi_host_template ahci_sht = {
96 static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
101 static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
106 static const struct ata_port_info ahci_port_info[] = {
109 .flags = AHCI_FLAG_COMMON,
110 .pio_mask = ATA_PIO4,
111 .udma_mask = ATA_UDMA6,
112 .port_ops = &ahci_ops,
114 [board_ahci_ign_iferr] = {
115 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
116 .flags = AHCI_FLAG_COMMON,
117 .pio_mask = ATA_PIO4,
118 .udma_mask = ATA_UDMA6,
119 .port_ops = &ahci_ops,
121 [board_ahci_nosntf] = {
122 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_yes_fbs] = {
129 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
136 [board_ahci_mcp65] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
144 [board_ahci_mcp77] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
151 [board_ahci_mcp89] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
160 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
161 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
166 [board_ahci_sb600] = {
167 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
168 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
169 AHCI_HFLAG_32BIT_ONLY),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_pmp_retry_srst_ops,
175 [board_ahci_sb700] = { /* for SB700 and SB800 */
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
177 .flags = AHCI_FLAG_COMMON,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_pmp_retry_srst_ops,
182 [board_ahci_vt8251] = {
183 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
187 .port_ops = &ahci_vt8251_ops,
191 static const struct pci_device_id ahci_pci_tbl[] = {
193 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
194 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
195 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
196 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
197 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
198 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
199 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
200 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
203 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
204 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
205 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
207 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
209 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
214 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
221 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
223 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
224 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
225 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
226 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
228 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
229 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
230 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
231 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
232 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
233 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
236 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
240 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
241 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
244 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
247 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
252 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
254 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
260 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
262 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
268 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
269 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
270 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
271 /* JMicron 362B and 362C have an AHCI function with IDE class code */
272 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
273 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
391 { PCI_DEVICE(0x1b4b, 0x9123),
392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
397 { PCI_DEVICE(0x1b4b, 0x917a),
398 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
399 { PCI_DEVICE(0x1b4b, 0x9192),
400 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
401 { PCI_DEVICE(0x1b4b, 0x91a3),
402 .driver_data = board_ahci_yes_fbs },
405 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
408 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
410 /* Generic, PCI class code for AHCI */
411 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
412 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
414 { } /* terminate list */
418 static struct pci_driver ahci_pci_driver = {
420 .id_table = ahci_pci_tbl,
421 .probe = ahci_init_one,
422 .remove = ata_pci_remove_one,
424 .suspend = ahci_pci_device_suspend,
425 .resume = ahci_pci_device_resume,
429 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
430 static int marvell_enable;
432 static int marvell_enable = 1;
434 module_param(marvell_enable, int, 0644);
435 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
438 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
439 struct ahci_host_priv *hpriv)
441 unsigned int force_port_map = 0;
442 unsigned int mask_port_map = 0;
444 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
445 dev_info(&pdev->dev, "JMB361 has only one port\n");
450 * Temporary Marvell 6145 hack: PATA port presence
451 * is asserted through the standard AHCI port
452 * presence register, as bit 4 (counting from 0)
454 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
455 if (pdev->device == 0x6121)
460 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
463 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
467 static int ahci_pci_reset_controller(struct ata_host *host)
469 struct pci_dev *pdev = to_pci_dev(host->dev);
471 ahci_reset_controller(host);
473 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
474 struct ahci_host_priv *hpriv = host->private_data;
478 pci_read_config_word(pdev, 0x92, &tmp16);
479 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
480 tmp16 |= hpriv->port_map;
481 pci_write_config_word(pdev, 0x92, tmp16);
488 static void ahci_pci_init_controller(struct ata_host *host)
490 struct ahci_host_priv *hpriv = host->private_data;
491 struct pci_dev *pdev = to_pci_dev(host->dev);
492 void __iomem *port_mmio;
496 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
497 if (pdev->device == 0x6121)
501 port_mmio = __ahci_port_base(host, mv);
503 writel(0, port_mmio + PORT_IRQ_MASK);
506 tmp = readl(port_mmio + PORT_IRQ_STAT);
507 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
509 writel(tmp, port_mmio + PORT_IRQ_STAT);
512 ahci_init_controller(host);
515 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
516 unsigned long deadline)
518 struct ata_port *ap = link->ap;
524 ahci_stop_engine(ap);
526 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
527 deadline, &online, NULL);
529 ahci_start_engine(ap);
531 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
533 /* vt8251 doesn't clear BSY on signature FIS reception,
534 * request follow-up softreset.
536 return online ? -EAGAIN : rc;
539 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
540 unsigned long deadline)
542 struct ata_port *ap = link->ap;
543 struct ahci_port_priv *pp = ap->private_data;
544 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
545 struct ata_taskfile tf;
549 ahci_stop_engine(ap);
551 /* clear D2H reception area to properly wait for D2H FIS */
552 ata_tf_init(link->device, &tf);
554 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
556 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
557 deadline, &online, NULL);
559 ahci_start_engine(ap);
561 /* The pseudo configuration device on SIMG4726 attached to
562 * ASUS P5W-DH Deluxe doesn't send signature FIS after
563 * hardreset if no device is attached to the first downstream
564 * port && the pseudo device locks up on SRST w/ PMP==0. To
565 * work around this, wait for !BSY only briefly. If BSY isn't
566 * cleared, perform CLO and proceed to IDENTIFY (achieved by
567 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
569 * Wait for two seconds. Devices attached to downstream port
570 * which can't process the following IDENTIFY after this will
571 * have to be reset again. For most cases, this should
572 * suffice while making probing snappish enough.
575 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
578 ahci_kick_engine(ap);
584 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
586 struct ata_host *host = dev_get_drvdata(&pdev->dev);
587 struct ahci_host_priv *hpriv = host->private_data;
588 void __iomem *mmio = hpriv->mmio;
591 if (mesg.event & PM_EVENT_SUSPEND &&
592 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
594 "BIOS update required for suspend/resume\n");
598 if (mesg.event & PM_EVENT_SLEEP) {
599 /* AHCI spec rev1.1 section 8.3.3:
600 * Software must disable interrupts prior to requesting a
601 * transition of the HBA to D3 state.
603 ctl = readl(mmio + HOST_CTL);
605 writel(ctl, mmio + HOST_CTL);
606 readl(mmio + HOST_CTL); /* flush */
609 return ata_pci_device_suspend(pdev, mesg);
612 static int ahci_pci_device_resume(struct pci_dev *pdev)
614 struct ata_host *host = dev_get_drvdata(&pdev->dev);
617 rc = ata_pci_device_do_resume(pdev);
621 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
622 rc = ahci_pci_reset_controller(host);
626 ahci_pci_init_controller(host);
629 ata_host_resume(host);
635 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
640 * If the device fixup already set the dma_mask to some non-standard
641 * value, don't extend it here. This happens on STA2X11, for example.
643 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
647 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
648 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
650 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
653 "64-bit DMA enable failed\n");
658 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
660 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
663 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
666 "32-bit consistent DMA enable failed\n");
673 static void ahci_pci_print_info(struct ata_host *host)
675 struct pci_dev *pdev = to_pci_dev(host->dev);
679 pci_read_config_word(pdev, 0x0a, &cc);
680 if (cc == PCI_CLASS_STORAGE_IDE)
682 else if (cc == PCI_CLASS_STORAGE_SATA)
684 else if (cc == PCI_CLASS_STORAGE_RAID)
689 ahci_print_info(host, scc_s);
692 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
693 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
694 * support PMP and the 4726 either directly exports the device
695 * attached to the first downstream port or acts as a hardware storage
696 * controller and emulate a single ATA device (can be RAID 0/1 or some
697 * other configuration).
699 * When there's no device attached to the first downstream port of the
700 * 4726, "Config Disk" appears, which is a pseudo ATA device to
701 * configure the 4726. However, ATA emulation of the device is very
702 * lame. It doesn't send signature D2H Reg FIS after the initial
703 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
705 * The following function works around the problem by always using
706 * hardreset on the port and not depending on receiving signature FIS
707 * afterward. If signature FIS isn't received soon, ATA class is
708 * assumed without follow-up softreset.
710 static void ahci_p5wdh_workaround(struct ata_host *host)
712 static struct dmi_system_id sysids[] = {
714 .ident = "P5W DH Deluxe",
716 DMI_MATCH(DMI_SYS_VENDOR,
717 "ASUSTEK COMPUTER INC"),
718 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
723 struct pci_dev *pdev = to_pci_dev(host->dev);
725 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
726 dmi_check_system(sysids)) {
727 struct ata_port *ap = host->ports[1];
730 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
732 ap->ops = &ahci_p5wdh_ops;
733 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
737 /* only some SB600 ahci controllers can do 64bit DMA */
738 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
740 static const struct dmi_system_id sysids[] = {
742 * The oldest version known to be broken is 0901 and
743 * working is 1501 which was released on 2007-10-26.
744 * Enable 64bit DMA on 1501 and anything newer.
746 * Please read bko#9412 for more info.
749 .ident = "ASUS M2A-VM",
751 DMI_MATCH(DMI_BOARD_VENDOR,
752 "ASUSTeK Computer INC."),
753 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
755 .driver_data = "20071026", /* yyyymmdd */
758 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
761 * BIOS versions earlier than 1.5 had the Manufacturer DMI
762 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
763 * This spelling mistake was fixed in BIOS version 1.5, so
764 * 1.5 and later have the Manufacturer as
765 * "MICRO-STAR INTERNATIONAL CO.,LTD".
766 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
768 * BIOS versions earlier than 1.9 had a Board Product Name
769 * DMI field of "MS-7376". This was changed to be
770 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
771 * match on DMI_BOARD_NAME of "MS-7376".
774 .ident = "MSI K9A2 Platinum",
776 DMI_MATCH(DMI_BOARD_VENDOR,
778 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
782 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
785 * This board also had the typo mentioned above in the
786 * Manufacturer DMI field (fixed in BIOS version 1.5), so
787 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
790 .ident = "MSI K9AGM2",
792 DMI_MATCH(DMI_BOARD_VENDOR,
794 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
798 * All BIOS versions for the Asus M3A support 64bit DMA.
799 * (all release versions from 0301 to 1206 were tested)
804 DMI_MATCH(DMI_BOARD_VENDOR,
805 "ASUSTeK Computer INC."),
806 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
811 const struct dmi_system_id *match;
812 int year, month, date;
815 match = dmi_first_match(sysids);
816 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
820 if (!match->driver_data)
823 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
824 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
826 if (strcmp(buf, match->driver_data) >= 0)
830 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
836 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
840 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
842 static const struct dmi_system_id broken_systems[] = {
844 .ident = "HP Compaq nx6310",
846 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
847 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
849 /* PCI slot number of the controller */
850 .driver_data = (void *)0x1FUL,
853 .ident = "HP Compaq 6720s",
855 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
856 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
858 /* PCI slot number of the controller */
859 .driver_data = (void *)0x1FUL,
862 { } /* terminate list */
864 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
867 unsigned long slot = (unsigned long)dmi->driver_data;
868 /* apply the quirk only to on-board controllers */
869 return slot == PCI_SLOT(pdev->devfn);
875 static bool ahci_broken_suspend(struct pci_dev *pdev)
877 static const struct dmi_system_id sysids[] = {
879 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
880 * to the harddisk doesn't become online after
881 * resuming from STR. Warn and fail suspend.
883 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
885 * Use dates instead of versions to match as HP is
886 * apparently recycling both product and version
889 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
894 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
895 DMI_MATCH(DMI_PRODUCT_NAME,
896 "HP Pavilion dv4 Notebook PC"),
898 .driver_data = "20090105", /* F.30 */
903 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
904 DMI_MATCH(DMI_PRODUCT_NAME,
905 "HP Pavilion dv5 Notebook PC"),
907 .driver_data = "20090506", /* F.16 */
912 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
913 DMI_MATCH(DMI_PRODUCT_NAME,
914 "HP Pavilion dv6 Notebook PC"),
916 .driver_data = "20090423", /* F.21 */
921 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
922 DMI_MATCH(DMI_PRODUCT_NAME,
923 "HP HDX18 Notebook PC"),
925 .driver_data = "20090430", /* F.23 */
928 * Acer eMachines G725 has the same problem. BIOS
929 * V1.03 is known to be broken. V3.04 is known to
930 * work. Between, there are V1.06, V2.06 and V3.03
931 * that we don't have much idea about. For now,
932 * blacklist anything older than V3.04.
934 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
939 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
940 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
942 .driver_data = "20091216", /* V3.04 */
944 { } /* terminate list */
946 const struct dmi_system_id *dmi = dmi_first_match(sysids);
947 int year, month, date;
950 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
953 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
954 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
956 return strcmp(buf, dmi->driver_data) < 0;
959 static bool ahci_broken_online(struct pci_dev *pdev)
961 #define ENCODE_BUSDEVFN(bus, slot, func) \
962 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
963 static const struct dmi_system_id sysids[] = {
965 * There are several gigabyte boards which use
966 * SIMG5723s configured as hardware RAID. Certain
967 * 5723 firmware revisions shipped there keep the link
968 * online but fail to answer properly to SRST or
969 * IDENTIFY when no device is attached downstream
970 * causing libata to retry quite a few times leading
971 * to excessive detection delay.
973 * As these firmwares respond to the second reset try
974 * with invalid device signature, considering unknown
975 * sig as offline works around the problem acceptably.
980 DMI_MATCH(DMI_BOARD_VENDOR,
981 "Gigabyte Technology Co., Ltd."),
982 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
984 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
989 DMI_MATCH(DMI_BOARD_VENDOR,
990 "Gigabyte Technology Co., Ltd."),
991 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
993 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
995 { } /* terminate list */
997 #undef ENCODE_BUSDEVFN
998 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1004 val = (unsigned long)dmi->driver_data;
1006 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1009 #ifdef CONFIG_ATA_ACPI
1010 static void ahci_gtf_filter_workaround(struct ata_host *host)
1012 static const struct dmi_system_id sysids[] = {
1014 * Aspire 3810T issues a bunch of SATA enable commands
1015 * via _GTF including an invalid one and one which is
1016 * rejected by the device. Among the successful ones
1017 * is FPDMA non-zero offset enable which when enabled
1018 * only on the drive side leads to NCQ command
1019 * failures. Filter it out.
1022 .ident = "Aspire 3810T",
1024 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1025 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1027 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1031 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1032 unsigned int filter;
1038 filter = (unsigned long)dmi->driver_data;
1039 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1040 filter, dmi->ident);
1042 for (i = 0; i < host->n_ports; i++) {
1043 struct ata_port *ap = host->ports[i];
1044 struct ata_link *link;
1045 struct ata_device *dev;
1047 ata_for_each_link(link, ap, EDGE)
1048 ata_for_each_dev(dev, link, ALL)
1049 dev->gtf_filter |= filter;
1053 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1057 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1059 unsigned int board_id = ent->driver_data;
1060 struct ata_port_info pi = ahci_port_info[board_id];
1061 const struct ata_port_info *ppi[] = { &pi, NULL };
1062 struct device *dev = &pdev->dev;
1063 struct ahci_host_priv *hpriv;
1064 struct ata_host *host;
1066 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1070 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1072 ata_print_version_once(&pdev->dev, DRV_VERSION);
1074 /* The AHCI driver can only drive the SATA ports, the PATA driver
1075 can drive them all so if both drivers are selected make sure
1076 AHCI stays out of the way */
1077 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1081 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1082 * ahci, use ata_generic instead.
1084 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1085 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1086 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1087 pdev->subsystem_device == 0xcb89)
1090 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1091 * At the moment, we can only use the AHCI mode. Let the users know
1092 * that for SAS drives they're out of luck.
1094 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1095 dev_info(&pdev->dev,
1096 "PDC42819 can only drive SATA devices with this driver\n");
1098 /* The Connext uses non-standard BAR */
1099 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1100 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1102 /* acquire resources */
1103 rc = pcim_enable_device(pdev);
1107 /* AHCI controllers often implement SFF compatible interface.
1108 * Grab all PCI BARs just in case.
1110 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1112 pcim_pin_device(pdev);
1116 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1117 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1120 /* ICH6s share the same PCI ID for both piix and ahci
1121 * modes. Enabling ahci mode while MAP indicates
1122 * combined mode is a bad idea. Yield to ata_piix.
1124 pci_read_config_byte(pdev, ICH_MAP, &map);
1126 dev_info(&pdev->dev,
1127 "controller is in combined mode, can't enable AHCI mode\n");
1132 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1135 hpriv->flags |= (unsigned long)pi.private_data;
1137 /* MCP65 revision A1 and A2 can't do MSI */
1138 if (board_id == board_ahci_mcp65 &&
1139 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1140 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1142 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1143 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1144 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1146 /* only some SB600s can do 64bit DMA */
1147 if (ahci_sb600_enable_64bit(pdev))
1148 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1150 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1153 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1155 /* save initial config */
1156 ahci_pci_save_initial_config(pdev, hpriv);
1159 if (hpriv->cap & HOST_CAP_NCQ) {
1160 pi.flags |= ATA_FLAG_NCQ;
1162 * Auto-activate optimization is supposed to be
1163 * supported on all AHCI controllers indicating NCQ
1164 * capability, but it seems to be broken on some
1165 * chipsets including NVIDIAs.
1167 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1168 pi.flags |= ATA_FLAG_FPDMA_AA;
1171 if (hpriv->cap & HOST_CAP_PMP)
1172 pi.flags |= ATA_FLAG_PMP;
1174 ahci_set_em_messages(hpriv, &pi);
1176 if (ahci_broken_system_poweroff(pdev)) {
1177 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1178 dev_info(&pdev->dev,
1179 "quirky BIOS, skipping spindown on poweroff\n");
1182 if (ahci_broken_suspend(pdev)) {
1183 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1184 dev_warn(&pdev->dev,
1185 "BIOS update required for suspend/resume\n");
1188 if (ahci_broken_online(pdev)) {
1189 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1190 dev_info(&pdev->dev,
1191 "online status unreliable, applying workaround\n");
1194 /* CAP.NP sometimes indicate the index of the last enabled
1195 * port, at other times, that of the last possible port, so
1196 * determining the maximum port number requires looking at
1197 * both CAP.NP and port_map.
1199 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1201 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1204 host->private_data = hpriv;
1206 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1207 host->flags |= ATA_HOST_PARALLEL_SCAN;
1209 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1211 if (pi.flags & ATA_FLAG_EM)
1212 ahci_reset_em(host);
1214 for (i = 0; i < host->n_ports; i++) {
1215 struct ata_port *ap = host->ports[i];
1217 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1218 ata_port_pbar_desc(ap, ahci_pci_bar,
1219 0x100 + ap->port_no * 0x80, "port");
1221 /* set enclosure management message type */
1222 if (ap->flags & ATA_FLAG_EM)
1223 ap->em_message_type = hpriv->em_msg_type;
1226 /* disabled/not-implemented port */
1227 if (!(hpriv->port_map & (1 << i)))
1228 ap->ops = &ata_dummy_port_ops;
1231 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1232 ahci_p5wdh_workaround(host);
1234 /* apply gtf filter quirk */
1235 ahci_gtf_filter_workaround(host);
1237 /* initialize adapter */
1238 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1242 rc = ahci_pci_reset_controller(host);
1246 ahci_pci_init_controller(host);
1247 ahci_pci_print_info(host);
1249 pci_set_master(pdev);
1250 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1254 module_pci_driver(ahci_pci_driver);
1256 MODULE_AUTHOR("Jeff Garzik");
1257 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1258 MODULE_LICENSE("GPL");
1259 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1260 MODULE_VERSION(DRV_VERSION);