2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
60 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87 static bool is_mcp89_apple(struct pci_dev *pdev);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
95 static struct scsi_host_template ahci_sht = {
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
109 static const struct ata_port_info ahci_port_info[] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
131 [board_ahci_nosntf] = {
132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
138 [board_ahci_yes_fbs] = {
139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
146 [board_ahci_mcp65] = {
147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
154 [board_ahci_mcp77] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
161 [board_ahci_mcp89] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
176 [board_ahci_sb600] = {
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
185 [board_ahci_sb700] = { /* for SB700 and SB800 */
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
192 [board_ahci_vt8251] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_vt8251_ops,
201 static const struct pci_device_id ahci_pci_tbl[] = {
203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
309 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
310 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
311 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
312 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
313 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
314 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
315 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
317 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
318 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
319 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
320 /* JMicron 362B and 362C have an AHCI function with IDE class code */
321 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
322 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
325 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
326 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
331 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
334 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
335 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
336 /* AMD is using RAID class only for ahci controllers */
337 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
338 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
341 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
342 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
345 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
353 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
417 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
428 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
431 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
432 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
433 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
435 /* ST Microelectronics */
436 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
439 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
440 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
442 .class = PCI_CLASS_STORAGE_SATA_AHCI,
443 .class_mask = 0xffffff,
444 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
447 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
448 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
449 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
451 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
452 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
453 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
454 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
455 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
457 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
459 .driver_data = board_ahci_yes_fbs },
460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
461 .driver_data = board_ahci_yes_fbs },
462 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
463 .driver_data = board_ahci_yes_fbs },
464 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
465 .driver_data = board_ahci_yes_fbs },
468 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
469 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
472 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
473 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
474 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
475 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
478 * Samsung SSDs found on some macbooks. NCQ times out.
479 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
481 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
484 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
486 /* Generic, PCI class code for AHCI */
487 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
488 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
490 { } /* terminate list */
494 static struct pci_driver ahci_pci_driver = {
496 .id_table = ahci_pci_tbl,
497 .probe = ahci_init_one,
498 .remove = ata_pci_remove_one,
500 .suspend = ahci_pci_device_suspend,
501 .resume = ahci_pci_device_resume,
505 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
506 static int marvell_enable;
508 static int marvell_enable = 1;
510 module_param(marvell_enable, int, 0644);
511 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
514 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
515 struct ahci_host_priv *hpriv)
517 unsigned int force_port_map = 0;
518 unsigned int mask_port_map = 0;
520 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
521 dev_info(&pdev->dev, "JMB361 has only one port\n");
526 * Temporary Marvell 6145 hack: PATA port presence
527 * is asserted through the standard AHCI port
528 * presence register, as bit 4 (counting from 0)
530 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
531 if (pdev->device == 0x6121)
536 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
539 ahci_save_initial_config(&pdev->dev, hpriv);
542 static int ahci_pci_reset_controller(struct ata_host *host)
544 struct pci_dev *pdev = to_pci_dev(host->dev);
546 ahci_reset_controller(host);
548 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
549 struct ahci_host_priv *hpriv = host->private_data;
553 pci_read_config_word(pdev, 0x92, &tmp16);
554 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
555 tmp16 |= hpriv->port_map;
556 pci_write_config_word(pdev, 0x92, tmp16);
563 static void ahci_pci_init_controller(struct ata_host *host)
565 struct ahci_host_priv *hpriv = host->private_data;
566 struct pci_dev *pdev = to_pci_dev(host->dev);
567 void __iomem *port_mmio;
571 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
572 if (pdev->device == 0x6121)
576 port_mmio = __ahci_port_base(host, mv);
578 writel(0, port_mmio + PORT_IRQ_MASK);
581 tmp = readl(port_mmio + PORT_IRQ_STAT);
582 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
584 writel(tmp, port_mmio + PORT_IRQ_STAT);
587 ahci_init_controller(host);
590 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline)
593 struct ata_port *ap = link->ap;
594 struct ahci_host_priv *hpriv = ap->host->private_data;
600 ahci_stop_engine(ap);
602 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
603 deadline, &online, NULL);
605 hpriv->start_engine(ap);
607 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
609 /* vt8251 doesn't clear BSY on signature FIS reception,
610 * request follow-up softreset.
612 return online ? -EAGAIN : rc;
615 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
616 unsigned long deadline)
618 struct ata_port *ap = link->ap;
619 struct ahci_port_priv *pp = ap->private_data;
620 struct ahci_host_priv *hpriv = ap->host->private_data;
621 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
622 struct ata_taskfile tf;
626 ahci_stop_engine(ap);
628 /* clear D2H reception area to properly wait for D2H FIS */
629 ata_tf_init(link->device, &tf);
630 tf.command = ATA_BUSY;
631 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
633 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
634 deadline, &online, NULL);
636 hpriv->start_engine(ap);
638 /* The pseudo configuration device on SIMG4726 attached to
639 * ASUS P5W-DH Deluxe doesn't send signature FIS after
640 * hardreset if no device is attached to the first downstream
641 * port && the pseudo device locks up on SRST w/ PMP==0. To
642 * work around this, wait for !BSY only briefly. If BSY isn't
643 * cleared, perform CLO and proceed to IDENTIFY (achieved by
644 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
646 * Wait for two seconds. Devices attached to downstream port
647 * which can't process the following IDENTIFY after this will
648 * have to be reset again. For most cases, this should
649 * suffice while making probing snappish enough.
652 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
655 ahci_kick_engine(ap);
661 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
663 struct ata_host *host = pci_get_drvdata(pdev);
664 struct ahci_host_priv *hpriv = host->private_data;
665 void __iomem *mmio = hpriv->mmio;
668 if (mesg.event & PM_EVENT_SUSPEND &&
669 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
671 "BIOS update required for suspend/resume\n");
675 if (mesg.event & PM_EVENT_SLEEP) {
676 /* AHCI spec rev1.1 section 8.3.3:
677 * Software must disable interrupts prior to requesting a
678 * transition of the HBA to D3 state.
680 ctl = readl(mmio + HOST_CTL);
682 writel(ctl, mmio + HOST_CTL);
683 readl(mmio + HOST_CTL); /* flush */
686 return ata_pci_device_suspend(pdev, mesg);
689 static int ahci_pci_device_resume(struct pci_dev *pdev)
691 struct ata_host *host = pci_get_drvdata(pdev);
694 rc = ata_pci_device_do_resume(pdev);
698 /* Apple BIOS helpfully mangles the registers on resume */
699 if (is_mcp89_apple(pdev))
700 ahci_mcp89_apple_enable(pdev);
702 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
703 rc = ahci_pci_reset_controller(host);
707 ahci_pci_init_controller(host);
710 ata_host_resume(host);
716 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
721 * If the device fixup already set the dma_mask to some non-standard
722 * value, don't extend it here. This happens on STA2X11, for example.
724 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
728 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
729 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
731 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
734 "64-bit DMA enable failed\n");
739 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
741 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
744 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
747 "32-bit consistent DMA enable failed\n");
754 static void ahci_pci_print_info(struct ata_host *host)
756 struct pci_dev *pdev = to_pci_dev(host->dev);
760 pci_read_config_word(pdev, 0x0a, &cc);
761 if (cc == PCI_CLASS_STORAGE_IDE)
763 else if (cc == PCI_CLASS_STORAGE_SATA)
765 else if (cc == PCI_CLASS_STORAGE_RAID)
770 ahci_print_info(host, scc_s);
773 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
774 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
775 * support PMP and the 4726 either directly exports the device
776 * attached to the first downstream port or acts as a hardware storage
777 * controller and emulate a single ATA device (can be RAID 0/1 or some
778 * other configuration).
780 * When there's no device attached to the first downstream port of the
781 * 4726, "Config Disk" appears, which is a pseudo ATA device to
782 * configure the 4726. However, ATA emulation of the device is very
783 * lame. It doesn't send signature D2H Reg FIS after the initial
784 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
786 * The following function works around the problem by always using
787 * hardreset on the port and not depending on receiving signature FIS
788 * afterward. If signature FIS isn't received soon, ATA class is
789 * assumed without follow-up softreset.
791 static void ahci_p5wdh_workaround(struct ata_host *host)
793 static const struct dmi_system_id sysids[] = {
795 .ident = "P5W DH Deluxe",
797 DMI_MATCH(DMI_SYS_VENDOR,
798 "ASUSTEK COMPUTER INC"),
799 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
804 struct pci_dev *pdev = to_pci_dev(host->dev);
806 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
807 dmi_check_system(sysids)) {
808 struct ata_port *ap = host->ports[1];
811 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
813 ap->ops = &ahci_p5wdh_ops;
814 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
819 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
820 * booting in BIOS compatibility mode. We restore the registers but not ID.
822 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
826 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
828 pci_read_config_dword(pdev, 0xf8, &val);
830 /* the following changes the device ID, but appears not to affect function */
831 /* val = (val & ~0xf0000000) | 0x80000000; */
832 pci_write_config_dword(pdev, 0xf8, val);
834 pci_read_config_dword(pdev, 0x54c, &val);
836 pci_write_config_dword(pdev, 0x54c, val);
838 pci_read_config_dword(pdev, 0x4a4, &val);
841 pci_write_config_dword(pdev, 0x4a4, val);
843 pci_read_config_dword(pdev, 0x54c, &val);
845 pci_write_config_dword(pdev, 0x54c, val);
847 pci_read_config_dword(pdev, 0xf8, &val);
849 pci_write_config_dword(pdev, 0xf8, val);
852 static bool is_mcp89_apple(struct pci_dev *pdev)
854 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
855 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
856 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
857 pdev->subsystem_device == 0xcb89;
860 /* only some SB600 ahci controllers can do 64bit DMA */
861 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
863 static const struct dmi_system_id sysids[] = {
865 * The oldest version known to be broken is 0901 and
866 * working is 1501 which was released on 2007-10-26.
867 * Enable 64bit DMA on 1501 and anything newer.
869 * Please read bko#9412 for more info.
872 .ident = "ASUS M2A-VM",
874 DMI_MATCH(DMI_BOARD_VENDOR,
875 "ASUSTeK Computer INC."),
876 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
878 .driver_data = "20071026", /* yyyymmdd */
881 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
884 * BIOS versions earlier than 1.5 had the Manufacturer DMI
885 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
886 * This spelling mistake was fixed in BIOS version 1.5, so
887 * 1.5 and later have the Manufacturer as
888 * "MICRO-STAR INTERNATIONAL CO.,LTD".
889 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
891 * BIOS versions earlier than 1.9 had a Board Product Name
892 * DMI field of "MS-7376". This was changed to be
893 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
894 * match on DMI_BOARD_NAME of "MS-7376".
897 .ident = "MSI K9A2 Platinum",
899 DMI_MATCH(DMI_BOARD_VENDOR,
901 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
905 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
908 * This board also had the typo mentioned above in the
909 * Manufacturer DMI field (fixed in BIOS version 1.5), so
910 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
913 .ident = "MSI K9AGM2",
915 DMI_MATCH(DMI_BOARD_VENDOR,
917 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
921 * All BIOS versions for the Asus M3A support 64bit DMA.
922 * (all release versions from 0301 to 1206 were tested)
927 DMI_MATCH(DMI_BOARD_VENDOR,
928 "ASUSTeK Computer INC."),
929 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
934 const struct dmi_system_id *match;
935 int year, month, date;
938 match = dmi_first_match(sysids);
939 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
943 if (!match->driver_data)
946 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
947 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
949 if (strcmp(buf, match->driver_data) >= 0)
953 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
959 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
963 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
965 static const struct dmi_system_id broken_systems[] = {
967 .ident = "HP Compaq nx6310",
969 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
970 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
972 /* PCI slot number of the controller */
973 .driver_data = (void *)0x1FUL,
976 .ident = "HP Compaq 6720s",
978 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
979 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
981 /* PCI slot number of the controller */
982 .driver_data = (void *)0x1FUL,
985 { } /* terminate list */
987 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
990 unsigned long slot = (unsigned long)dmi->driver_data;
991 /* apply the quirk only to on-board controllers */
992 return slot == PCI_SLOT(pdev->devfn);
998 static bool ahci_broken_suspend(struct pci_dev *pdev)
1000 static const struct dmi_system_id sysids[] = {
1002 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1003 * to the harddisk doesn't become online after
1004 * resuming from STR. Warn and fail suspend.
1006 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1008 * Use dates instead of versions to match as HP is
1009 * apparently recycling both product and version
1012 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1017 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1018 DMI_MATCH(DMI_PRODUCT_NAME,
1019 "HP Pavilion dv4 Notebook PC"),
1021 .driver_data = "20090105", /* F.30 */
1026 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1027 DMI_MATCH(DMI_PRODUCT_NAME,
1028 "HP Pavilion dv5 Notebook PC"),
1030 .driver_data = "20090506", /* F.16 */
1035 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1036 DMI_MATCH(DMI_PRODUCT_NAME,
1037 "HP Pavilion dv6 Notebook PC"),
1039 .driver_data = "20090423", /* F.21 */
1044 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1045 DMI_MATCH(DMI_PRODUCT_NAME,
1046 "HP HDX18 Notebook PC"),
1048 .driver_data = "20090430", /* F.23 */
1051 * Acer eMachines G725 has the same problem. BIOS
1052 * V1.03 is known to be broken. V3.04 is known to
1053 * work. Between, there are V1.06, V2.06 and V3.03
1054 * that we don't have much idea about. For now,
1055 * blacklist anything older than V3.04.
1057 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1062 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1065 .driver_data = "20091216", /* V3.04 */
1067 { } /* terminate list */
1069 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1070 int year, month, date;
1073 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1076 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1077 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1079 return strcmp(buf, dmi->driver_data) < 0;
1082 static bool ahci_broken_online(struct pci_dev *pdev)
1084 #define ENCODE_BUSDEVFN(bus, slot, func) \
1085 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1086 static const struct dmi_system_id sysids[] = {
1088 * There are several gigabyte boards which use
1089 * SIMG5723s configured as hardware RAID. Certain
1090 * 5723 firmware revisions shipped there keep the link
1091 * online but fail to answer properly to SRST or
1092 * IDENTIFY when no device is attached downstream
1093 * causing libata to retry quite a few times leading
1094 * to excessive detection delay.
1096 * As these firmwares respond to the second reset try
1097 * with invalid device signature, considering unknown
1098 * sig as offline works around the problem acceptably.
1101 .ident = "EP45-DQ6",
1103 DMI_MATCH(DMI_BOARD_VENDOR,
1104 "Gigabyte Technology Co., Ltd."),
1105 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1107 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1110 .ident = "EP45-DS5",
1112 DMI_MATCH(DMI_BOARD_VENDOR,
1113 "Gigabyte Technology Co., Ltd."),
1114 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1116 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1118 { } /* terminate list */
1120 #undef ENCODE_BUSDEVFN
1121 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1127 val = (unsigned long)dmi->driver_data;
1129 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1132 static bool ahci_broken_devslp(struct pci_dev *pdev)
1134 /* device with broken DEVSLP but still showing SDS capability */
1135 static const struct pci_device_id ids[] = {
1136 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1140 return pci_match_id(ids, pdev);
1143 #ifdef CONFIG_ATA_ACPI
1144 static void ahci_gtf_filter_workaround(struct ata_host *host)
1146 static const struct dmi_system_id sysids[] = {
1148 * Aspire 3810T issues a bunch of SATA enable commands
1149 * via _GTF including an invalid one and one which is
1150 * rejected by the device. Among the successful ones
1151 * is FPDMA non-zero offset enable which when enabled
1152 * only on the drive side leads to NCQ command
1153 * failures. Filter it out.
1156 .ident = "Aspire 3810T",
1158 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1159 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1161 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1165 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1166 unsigned int filter;
1172 filter = (unsigned long)dmi->driver_data;
1173 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1174 filter, dmi->ident);
1176 for (i = 0; i < host->n_ports; i++) {
1177 struct ata_port *ap = host->ports[i];
1178 struct ata_link *link;
1179 struct ata_device *dev;
1181 ata_for_each_link(link, ap, EDGE)
1182 ata_for_each_dev(dev, link, ALL)
1183 dev->gtf_filter |= filter;
1187 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1191 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1192 struct ahci_host_priv *hpriv)
1196 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1199 nvec = pci_msi_vec_count(pdev);
1204 * If number of MSIs is less than number of ports then Sharing Last
1205 * Message mode could be enforced. In this case assume that advantage
1206 * of multipe MSIs is negated and use single MSI mode instead.
1211 rc = pci_enable_msi_exact(pdev, nvec);
1217 /* fallback to single MSI mode if the controller enforced MRSM mode */
1218 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1219 pci_disable_msi(pdev);
1220 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1225 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1230 if (pci_enable_msi(pdev))
1239 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1241 unsigned int board_id = ent->driver_data;
1242 struct ata_port_info pi = ahci_port_info[board_id];
1243 const struct ata_port_info *ppi[] = { &pi, NULL };
1244 struct device *dev = &pdev->dev;
1245 struct ahci_host_priv *hpriv;
1246 struct ata_host *host;
1248 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1252 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1254 ata_print_version_once(&pdev->dev, DRV_VERSION);
1256 /* The AHCI driver can only drive the SATA ports, the PATA driver
1257 can drive them all so if both drivers are selected make sure
1258 AHCI stays out of the way */
1259 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1262 /* Apple BIOS on MCP89 prevents us using AHCI */
1263 if (is_mcp89_apple(pdev))
1264 ahci_mcp89_apple_enable(pdev);
1266 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1267 * At the moment, we can only use the AHCI mode. Let the users know
1268 * that for SAS drives they're out of luck.
1270 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1271 dev_info(&pdev->dev,
1272 "PDC42819 can only drive SATA devices with this driver\n");
1274 /* Both Connext and Enmotus devices use non-standard BARs */
1275 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1276 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1277 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1278 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1281 * The JMicron chip 361/363 contains one SATA controller and one
1282 * PATA controller,for powering on these both controllers, we must
1283 * follow the sequence one by one, otherwise one of them can not be
1284 * powered on successfully, so here we disable the async suspend
1285 * method for these chips.
1287 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1288 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1289 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1290 device_disable_async_suspend(&pdev->dev);
1292 /* acquire resources */
1293 rc = pcim_enable_device(pdev);
1297 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1298 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1301 /* ICH6s share the same PCI ID for both piix and ahci
1302 * modes. Enabling ahci mode while MAP indicates
1303 * combined mode is a bad idea. Yield to ata_piix.
1305 pci_read_config_byte(pdev, ICH_MAP, &map);
1307 dev_info(&pdev->dev,
1308 "controller is in combined mode, can't enable AHCI mode\n");
1313 /* AHCI controllers often implement SFF compatible interface.
1314 * Grab all PCI BARs just in case.
1316 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1318 pcim_pin_device(pdev);
1322 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1325 hpriv->flags |= (unsigned long)pi.private_data;
1327 /* MCP65 revision A1 and A2 can't do MSI */
1328 if (board_id == board_ahci_mcp65 &&
1329 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1330 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1332 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1333 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1334 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1336 /* only some SB600s can do 64bit DMA */
1337 if (ahci_sb600_enable_64bit(pdev))
1338 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1340 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1342 /* must set flag prior to save config in order to take effect */
1343 if (ahci_broken_devslp(pdev))
1344 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1346 /* save initial config */
1347 ahci_pci_save_initial_config(pdev, hpriv);
1350 if (hpriv->cap & HOST_CAP_NCQ) {
1351 pi.flags |= ATA_FLAG_NCQ;
1353 * Auto-activate optimization is supposed to be
1354 * supported on all AHCI controllers indicating NCQ
1355 * capability, but it seems to be broken on some
1356 * chipsets including NVIDIAs.
1358 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1359 pi.flags |= ATA_FLAG_FPDMA_AA;
1362 * All AHCI controllers should be forward-compatible
1363 * with the new auxiliary field. This code should be
1364 * conditionalized if any buggy AHCI controllers are
1367 pi.flags |= ATA_FLAG_FPDMA_AUX;
1370 if (hpriv->cap & HOST_CAP_PMP)
1371 pi.flags |= ATA_FLAG_PMP;
1373 ahci_set_em_messages(hpriv, &pi);
1375 if (ahci_broken_system_poweroff(pdev)) {
1376 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1377 dev_info(&pdev->dev,
1378 "quirky BIOS, skipping spindown on poweroff\n");
1381 if (ahci_broken_suspend(pdev)) {
1382 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1383 dev_warn(&pdev->dev,
1384 "BIOS update required for suspend/resume\n");
1387 if (ahci_broken_online(pdev)) {
1388 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1389 dev_info(&pdev->dev,
1390 "online status unreliable, applying workaround\n");
1393 /* CAP.NP sometimes indicate the index of the last enabled
1394 * port, at other times, that of the last possible port, so
1395 * determining the maximum port number requires looking at
1396 * both CAP.NP and port_map.
1398 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1400 ahci_init_interrupts(pdev, n_ports, hpriv);
1402 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1405 host->private_data = hpriv;
1407 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1408 host->flags |= ATA_HOST_PARALLEL_SCAN;
1410 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1412 if (pi.flags & ATA_FLAG_EM)
1413 ahci_reset_em(host);
1415 for (i = 0; i < host->n_ports; i++) {
1416 struct ata_port *ap = host->ports[i];
1418 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1419 ata_port_pbar_desc(ap, ahci_pci_bar,
1420 0x100 + ap->port_no * 0x80, "port");
1422 /* set enclosure management message type */
1423 if (ap->flags & ATA_FLAG_EM)
1424 ap->em_message_type = hpriv->em_msg_type;
1427 /* disabled/not-implemented port */
1428 if (!(hpriv->port_map & (1 << i)))
1429 ap->ops = &ata_dummy_port_ops;
1432 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1433 ahci_p5wdh_workaround(host);
1435 /* apply gtf filter quirk */
1436 ahci_gtf_filter_workaround(host);
1438 /* initialize adapter */
1439 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1443 rc = ahci_pci_reset_controller(host);
1447 ahci_pci_init_controller(host);
1448 ahci_pci_print_info(host);
1450 pci_set_master(pdev);
1452 return ahci_host_activate(host, pdev->irq, &ahci_sht);
1455 module_pci_driver(ahci_pci_driver);
1457 MODULE_AUTHOR("Jeff Garzik");
1458 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1459 MODULE_LICENSE("GPL");
1460 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1461 MODULE_VERSION(DRV_VERSION);