2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 static int ahci_enable_alpm(struct ata_port *ap,
58 static void ahci_disable_alpm(struct ata_port *ap);
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_USE_CLUSTERING = 1,
68 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
70 AHCI_CMD_TBL_CDB = 0x40,
71 AHCI_CMD_TBL_HDR_SZ = 0x80,
72 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
73 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
74 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
76 AHCI_IRQ_ON_SG = (1 << 31),
77 AHCI_CMD_ATAPI = (1 << 5),
78 AHCI_CMD_WRITE = (1 << 6),
79 AHCI_CMD_PREFETCH = (1 << 7),
80 AHCI_CMD_RESET = (1 << 8),
81 AHCI_CMD_CLR_BUSY = (1 << 10),
83 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
84 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
85 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
88 board_ahci_vt8251 = 1,
89 board_ahci_ign_iferr = 2,
94 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */
96 HOST_CTL = 0x04, /* global host control */
97 HOST_IRQ_STAT = 0x08, /* interrupt status */
98 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
102 HOST_RESET = (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
107 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
108 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
109 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
110 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
111 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
112 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
113 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
114 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
116 /* registers for each SATA port */
117 PORT_LST_ADDR = 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT = 0x10, /* interrupt status */
122 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
123 PORT_CMD = 0x18, /* port command */
124 PORT_TFDATA = 0x20, /* taskfile data */
125 PORT_SIG = 0x24, /* device TF signature */
126 PORT_CMD_ISSUE = 0x38, /* command issue */
127 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
131 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
143 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
153 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
159 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
161 PORT_IRQ_HBUS_DATA_ERR,
162 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
167 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
169 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
170 PORT_CMD_PMP = (1 << 17), /* PMP attached */
171 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
174 PORT_CMD_CLO = (1 << 3), /* Command list override */
175 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
177 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
179 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
180 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ = (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
191 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
192 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
193 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
197 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
198 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
199 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
201 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
203 ICH_MAP = 0x90, /* ICH MAP register */
206 struct ahci_cmd_hdr {
221 struct ahci_host_priv {
222 unsigned int flags; /* AHCI_HFLAG_* */
223 u32 cap; /* cap to use */
224 u32 port_map; /* port map to use */
225 u32 saved_cap; /* saved initial cap */
226 u32 saved_port_map; /* saved initial port_map */
229 struct ahci_port_priv {
230 struct ata_link *active_link;
231 struct ahci_cmd_hdr *cmd_slot;
232 dma_addr_t cmd_slot_dma;
234 dma_addr_t cmd_tbl_dma;
236 dma_addr_t rx_fis_dma;
237 /* for NCQ spurious interrupt analysis */
238 unsigned int ncq_saw_d2h:1;
239 unsigned int ncq_saw_dmas:1;
240 unsigned int ncq_saw_sdb:1;
241 u32 intr_mask; /* interrupts to enable */
244 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
245 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
246 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
247 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
248 static void ahci_irq_clear(struct ata_port *ap);
249 static int ahci_port_start(struct ata_port *ap);
250 static void ahci_port_stop(struct ata_port *ap);
251 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
252 static void ahci_qc_prep(struct ata_queued_cmd *qc);
253 static u8 ahci_check_status(struct ata_port *ap);
254 static void ahci_freeze(struct ata_port *ap);
255 static void ahci_thaw(struct ata_port *ap);
256 static void ahci_pmp_attach(struct ata_port *ap);
257 static void ahci_pmp_detach(struct ata_port *ap);
258 static void ahci_error_handler(struct ata_port *ap);
259 static void ahci_vt8251_error_handler(struct ata_port *ap);
260 static void ahci_p5wdh_error_handler(struct ata_port *ap);
261 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
262 static int ahci_port_resume(struct ata_port *ap);
263 static void ahci_dev_config(struct ata_device *dev);
264 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
265 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
268 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
269 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
270 static int ahci_pci_device_resume(struct pci_dev *pdev);
273 static struct class_device_attribute *ahci_shost_attrs[] = {
274 &class_device_attr_link_power_management_policy,
278 static struct scsi_host_template ahci_sht = {
279 .module = THIS_MODULE,
281 .ioctl = ata_scsi_ioctl,
282 .queuecommand = ata_scsi_queuecmd,
283 .change_queue_depth = ata_scsi_change_queue_depth,
284 .can_queue = AHCI_MAX_CMDS - 1,
285 .this_id = ATA_SHT_THIS_ID,
286 .sg_tablesize = AHCI_MAX_SG,
287 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
288 .emulated = ATA_SHT_EMULATED,
289 .use_clustering = AHCI_USE_CLUSTERING,
290 .proc_name = DRV_NAME,
291 .dma_boundary = AHCI_DMA_BOUNDARY,
292 .slave_configure = ata_scsi_slave_config,
293 .slave_destroy = ata_scsi_slave_destroy,
294 .bios_param = ata_std_bios_param,
295 .shost_attrs = ahci_shost_attrs,
298 static const struct ata_port_operations ahci_ops = {
299 .check_status = ahci_check_status,
300 .check_altstatus = ahci_check_status,
301 .dev_select = ata_noop_dev_select,
303 .dev_config = ahci_dev_config,
305 .tf_read = ahci_tf_read,
307 .qc_defer = sata_pmp_qc_defer_cmd_switch,
308 .qc_prep = ahci_qc_prep,
309 .qc_issue = ahci_qc_issue,
311 .irq_clear = ahci_irq_clear,
313 .scr_read = ahci_scr_read,
314 .scr_write = ahci_scr_write,
316 .freeze = ahci_freeze,
319 .error_handler = ahci_error_handler,
320 .post_internal_cmd = ahci_post_internal_cmd,
322 .pmp_attach = ahci_pmp_attach,
323 .pmp_detach = ahci_pmp_detach,
326 .port_suspend = ahci_port_suspend,
327 .port_resume = ahci_port_resume,
329 .enable_pm = ahci_enable_alpm,
330 .disable_pm = ahci_disable_alpm,
332 .port_start = ahci_port_start,
333 .port_stop = ahci_port_stop,
336 static const struct ata_port_operations ahci_vt8251_ops = {
337 .check_status = ahci_check_status,
338 .check_altstatus = ahci_check_status,
339 .dev_select = ata_noop_dev_select,
341 .tf_read = ahci_tf_read,
343 .qc_defer = sata_pmp_qc_defer_cmd_switch,
344 .qc_prep = ahci_qc_prep,
345 .qc_issue = ahci_qc_issue,
347 .irq_clear = ahci_irq_clear,
349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
352 .freeze = ahci_freeze,
355 .error_handler = ahci_vt8251_error_handler,
356 .post_internal_cmd = ahci_post_internal_cmd,
358 .pmp_attach = ahci_pmp_attach,
359 .pmp_detach = ahci_pmp_detach,
362 .port_suspend = ahci_port_suspend,
363 .port_resume = ahci_port_resume,
366 .port_start = ahci_port_start,
367 .port_stop = ahci_port_stop,
370 static const struct ata_port_operations ahci_p5wdh_ops = {
371 .check_status = ahci_check_status,
372 .check_altstatus = ahci_check_status,
373 .dev_select = ata_noop_dev_select,
375 .tf_read = ahci_tf_read,
377 .qc_defer = sata_pmp_qc_defer_cmd_switch,
378 .qc_prep = ahci_qc_prep,
379 .qc_issue = ahci_qc_issue,
381 .irq_clear = ahci_irq_clear,
383 .scr_read = ahci_scr_read,
384 .scr_write = ahci_scr_write,
386 .freeze = ahci_freeze,
389 .error_handler = ahci_p5wdh_error_handler,
390 .post_internal_cmd = ahci_post_internal_cmd,
392 .pmp_attach = ahci_pmp_attach,
393 .pmp_detach = ahci_pmp_detach,
396 .port_suspend = ahci_port_suspend,
397 .port_resume = ahci_port_resume,
400 .port_start = ahci_port_start,
401 .port_stop = ahci_port_stop,
404 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
406 static const struct ata_port_info ahci_port_info[] = {
409 .flags = AHCI_FLAG_COMMON,
410 .link_flags = AHCI_LFLAG_COMMON,
411 .pio_mask = 0x1f, /* pio0-4 */
412 .udma_mask = ATA_UDMA6,
413 .port_ops = &ahci_ops,
415 /* board_ahci_vt8251 */
417 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
418 .flags = AHCI_FLAG_COMMON,
419 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
420 .pio_mask = 0x1f, /* pio0-4 */
421 .udma_mask = ATA_UDMA6,
422 .port_ops = &ahci_vt8251_ops,
424 /* board_ahci_ign_iferr */
426 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
427 .flags = AHCI_FLAG_COMMON,
428 .link_flags = AHCI_LFLAG_COMMON,
429 .pio_mask = 0x1f, /* pio0-4 */
430 .udma_mask = ATA_UDMA6,
431 .port_ops = &ahci_ops,
433 /* board_ahci_sb600 */
435 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
436 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
437 .flags = AHCI_FLAG_COMMON,
438 .link_flags = AHCI_LFLAG_COMMON,
439 .pio_mask = 0x1f, /* pio0-4 */
440 .udma_mask = ATA_UDMA6,
441 .port_ops = &ahci_ops,
445 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
447 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
448 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
449 .link_flags = AHCI_LFLAG_COMMON,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
454 /* board_ahci_sb700 */
456 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
458 .flags = AHCI_FLAG_COMMON,
459 .link_flags = AHCI_LFLAG_COMMON,
460 .pio_mask = 0x1f, /* pio0-4 */
461 .udma_mask = ATA_UDMA6,
462 .port_ops = &ahci_ops,
466 static const struct pci_device_id ahci_pci_tbl[] = {
468 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
469 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
470 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
471 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
472 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
473 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
474 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
475 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
476 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
477 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
478 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
479 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
480 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
481 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
482 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
483 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
485 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
486 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
487 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
488 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
489 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
490 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
491 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
492 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
493 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
494 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
495 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
496 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
497 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
498 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
500 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
501 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
502 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
505 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
506 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
507 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
508 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
509 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
510 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
511 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
514 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
515 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
518 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
521 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
522 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
523 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
524 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
525 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
526 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
534 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
535 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
536 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
537 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
538 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
546 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
547 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
548 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
549 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
558 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
559 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
560 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
561 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
562 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
570 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
571 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
572 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
573 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
574 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
581 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
582 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
583 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
584 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
585 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
588 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
589 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
590 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
593 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
595 /* Generic, PCI class code for AHCI */
596 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
597 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
599 { } /* terminate list */
603 static struct pci_driver ahci_pci_driver = {
605 .id_table = ahci_pci_tbl,
606 .probe = ahci_init_one,
607 .remove = ata_pci_remove_one,
609 .suspend = ahci_pci_device_suspend,
610 .resume = ahci_pci_device_resume,
615 static inline int ahci_nr_ports(u32 cap)
617 return (cap & 0x1f) + 1;
620 static inline void __iomem *__ahci_port_base(struct ata_host *host,
621 unsigned int port_no)
623 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
625 return mmio + 0x100 + (port_no * 0x80);
628 static inline void __iomem *ahci_port_base(struct ata_port *ap)
630 return __ahci_port_base(ap->host, ap->port_no);
633 static void ahci_enable_ahci(void __iomem *mmio)
637 /* turn on AHCI_EN */
638 tmp = readl(mmio + HOST_CTL);
639 if (!(tmp & HOST_AHCI_EN)) {
641 writel(tmp, mmio + HOST_CTL);
642 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
643 WARN_ON(!(tmp & HOST_AHCI_EN));
648 * ahci_save_initial_config - Save and fixup initial config values
649 * @pdev: target PCI device
650 * @hpriv: host private area to store config values
652 * Some registers containing configuration info might be setup by
653 * BIOS and might be cleared on reset. This function saves the
654 * initial values of those registers into @hpriv such that they
655 * can be restored after controller reset.
657 * If inconsistent, config values are fixed up by this function.
662 static void ahci_save_initial_config(struct pci_dev *pdev,
663 struct ahci_host_priv *hpriv)
665 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
669 /* make sure AHCI mode is enabled before accessing CAP */
670 ahci_enable_ahci(mmio);
672 /* Values prefixed with saved_ are written back to host after
673 * reset. Values without are used for driver operation.
675 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
676 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
678 /* some chips have errata preventing 64bit use */
679 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
680 dev_printk(KERN_INFO, &pdev->dev,
681 "controller can't do 64bit DMA, forcing 32bit\n");
685 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
686 dev_printk(KERN_INFO, &pdev->dev,
687 "controller can't do NCQ, turning off CAP_NCQ\n");
688 cap &= ~HOST_CAP_NCQ;
691 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
692 dev_printk(KERN_INFO, &pdev->dev,
693 "controller can't do PMP, turning off CAP_PMP\n");
694 cap &= ~HOST_CAP_PMP;
698 * Temporary Marvell 6145 hack: PATA port presence
699 * is asserted through the standard AHCI port
700 * presence register, as bit 4 (counting from 0)
702 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
703 dev_printk(KERN_ERR, &pdev->dev,
704 "MV_AHCI HACK: port_map %x -> %x\n",
706 hpriv->port_map & 0xf);
711 /* cross check port_map and cap.n_ports */
715 for (i = 0; i < AHCI_MAX_PORTS; i++)
716 if (port_map & (1 << i))
719 /* If PI has more ports than n_ports, whine, clear
720 * port_map and let it be generated from n_ports.
722 if (map_ports > ahci_nr_ports(cap)) {
723 dev_printk(KERN_WARNING, &pdev->dev,
724 "implemented port map (0x%x) contains more "
725 "ports than nr_ports (%u), using nr_ports\n",
726 port_map, ahci_nr_ports(cap));
731 /* fabricate port_map from cap.nr_ports */
733 port_map = (1 << ahci_nr_ports(cap)) - 1;
734 dev_printk(KERN_WARNING, &pdev->dev,
735 "forcing PORTS_IMPL to 0x%x\n", port_map);
737 /* write the fixed up value to the PI register */
738 hpriv->saved_port_map = port_map;
741 /* record values to use during operation */
743 hpriv->port_map = port_map;
747 * ahci_restore_initial_config - Restore initial config
748 * @host: target ATA host
750 * Restore initial config stored by ahci_save_initial_config().
755 static void ahci_restore_initial_config(struct ata_host *host)
757 struct ahci_host_priv *hpriv = host->private_data;
758 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
760 writel(hpriv->saved_cap, mmio + HOST_CAP);
761 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
762 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
765 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
767 static const int offset[] = {
768 [SCR_STATUS] = PORT_SCR_STAT,
769 [SCR_CONTROL] = PORT_SCR_CTL,
770 [SCR_ERROR] = PORT_SCR_ERR,
771 [SCR_ACTIVE] = PORT_SCR_ACT,
772 [SCR_NOTIFICATION] = PORT_SCR_NTF,
774 struct ahci_host_priv *hpriv = ap->host->private_data;
776 if (sc_reg < ARRAY_SIZE(offset) &&
777 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
778 return offset[sc_reg];
782 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
784 void __iomem *port_mmio = ahci_port_base(ap);
785 int offset = ahci_scr_offset(ap, sc_reg);
788 *val = readl(port_mmio + offset);
794 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
796 void __iomem *port_mmio = ahci_port_base(ap);
797 int offset = ahci_scr_offset(ap, sc_reg);
800 writel(val, port_mmio + offset);
806 static void ahci_start_engine(struct ata_port *ap)
808 void __iomem *port_mmio = ahci_port_base(ap);
812 tmp = readl(port_mmio + PORT_CMD);
813 tmp |= PORT_CMD_START;
814 writel(tmp, port_mmio + PORT_CMD);
815 readl(port_mmio + PORT_CMD); /* flush */
818 static int ahci_stop_engine(struct ata_port *ap)
820 void __iomem *port_mmio = ahci_port_base(ap);
823 tmp = readl(port_mmio + PORT_CMD);
825 /* check if the HBA is idle */
826 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
829 /* setting HBA to idle */
830 tmp &= ~PORT_CMD_START;
831 writel(tmp, port_mmio + PORT_CMD);
833 /* wait for engine to stop. This could be as long as 500 msec */
834 tmp = ata_wait_register(port_mmio + PORT_CMD,
835 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
836 if (tmp & PORT_CMD_LIST_ON)
842 static void ahci_start_fis_rx(struct ata_port *ap)
844 void __iomem *port_mmio = ahci_port_base(ap);
845 struct ahci_host_priv *hpriv = ap->host->private_data;
846 struct ahci_port_priv *pp = ap->private_data;
849 /* set FIS registers */
850 if (hpriv->cap & HOST_CAP_64)
851 writel((pp->cmd_slot_dma >> 16) >> 16,
852 port_mmio + PORT_LST_ADDR_HI);
853 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
855 if (hpriv->cap & HOST_CAP_64)
856 writel((pp->rx_fis_dma >> 16) >> 16,
857 port_mmio + PORT_FIS_ADDR_HI);
858 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
860 /* enable FIS reception */
861 tmp = readl(port_mmio + PORT_CMD);
862 tmp |= PORT_CMD_FIS_RX;
863 writel(tmp, port_mmio + PORT_CMD);
866 readl(port_mmio + PORT_CMD);
869 static int ahci_stop_fis_rx(struct ata_port *ap)
871 void __iomem *port_mmio = ahci_port_base(ap);
874 /* disable FIS reception */
875 tmp = readl(port_mmio + PORT_CMD);
876 tmp &= ~PORT_CMD_FIS_RX;
877 writel(tmp, port_mmio + PORT_CMD);
879 /* wait for completion, spec says 500ms, give it 1000 */
880 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
881 PORT_CMD_FIS_ON, 10, 1000);
882 if (tmp & PORT_CMD_FIS_ON)
888 static void ahci_power_up(struct ata_port *ap)
890 struct ahci_host_priv *hpriv = ap->host->private_data;
891 void __iomem *port_mmio = ahci_port_base(ap);
894 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
897 if (hpriv->cap & HOST_CAP_SSS) {
898 cmd |= PORT_CMD_SPIN_UP;
899 writel(cmd, port_mmio + PORT_CMD);
903 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
906 static void ahci_disable_alpm(struct ata_port *ap)
908 struct ahci_host_priv *hpriv = ap->host->private_data;
909 void __iomem *port_mmio = ahci_port_base(ap);
911 struct ahci_port_priv *pp = ap->private_data;
913 /* IPM bits should be disabled by libata-core */
914 /* get the existing command bits */
915 cmd = readl(port_mmio + PORT_CMD);
917 /* disable ALPM and ASP */
918 cmd &= ~PORT_CMD_ASP;
919 cmd &= ~PORT_CMD_ALPE;
921 /* force the interface back to active */
922 cmd |= PORT_CMD_ICC_ACTIVE;
924 /* write out new cmd value */
925 writel(cmd, port_mmio + PORT_CMD);
926 cmd = readl(port_mmio + PORT_CMD);
928 /* wait 10ms to be sure we've come out of any low power state */
931 /* clear out any PhyRdy stuff from interrupt status */
932 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
934 /* go ahead and clean out PhyRdy Change from Serror too */
935 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
938 * Clear flag to indicate that we should ignore all PhyRdy
941 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
944 * Enable interrupts on Phy Ready.
946 pp->intr_mask |= PORT_IRQ_PHYRDY;
947 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
950 * don't change the link pm policy - we can be called
951 * just to turn of link pm temporarily
955 static int ahci_enable_alpm(struct ata_port *ap,
958 struct ahci_host_priv *hpriv = ap->host->private_data;
959 void __iomem *port_mmio = ahci_port_base(ap);
961 struct ahci_port_priv *pp = ap->private_data;
964 /* Make sure the host is capable of link power management */
965 if (!(hpriv->cap & HOST_CAP_ALPM))
969 case MAX_PERFORMANCE:
972 * if we came here with NOT_AVAILABLE,
973 * it just means this is the first time we
974 * have tried to enable - default to max performance,
975 * and let the user go to lower power modes on request.
977 ahci_disable_alpm(ap);
980 /* configure HBA to enter SLUMBER */
984 /* configure HBA to enter PARTIAL */
992 * Disable interrupts on Phy Ready. This keeps us from
993 * getting woken up due to spurious phy ready interrupts
994 * TBD - Hot plug should be done via polling now, is
995 * that even supported?
997 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
998 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1001 * Set a flag to indicate that we should ignore all PhyRdy
1002 * state changes since these can happen now whenever we
1005 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1007 /* get the existing command bits */
1008 cmd = readl(port_mmio + PORT_CMD);
1011 * Set ASP based on Policy
1016 * Setting this bit will instruct the HBA to aggressively
1017 * enter a lower power link state when it's appropriate and
1018 * based on the value set above for ASP
1020 cmd |= PORT_CMD_ALPE;
1022 /* write out new cmd value */
1023 writel(cmd, port_mmio + PORT_CMD);
1024 cmd = readl(port_mmio + PORT_CMD);
1026 /* IPM bits should be set by libata-core */
1031 static void ahci_power_down(struct ata_port *ap)
1033 struct ahci_host_priv *hpriv = ap->host->private_data;
1034 void __iomem *port_mmio = ahci_port_base(ap);
1037 if (!(hpriv->cap & HOST_CAP_SSS))
1040 /* put device into listen mode, first set PxSCTL.DET to 0 */
1041 scontrol = readl(port_mmio + PORT_SCR_CTL);
1043 writel(scontrol, port_mmio + PORT_SCR_CTL);
1045 /* then set PxCMD.SUD to 0 */
1046 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1047 cmd &= ~PORT_CMD_SPIN_UP;
1048 writel(cmd, port_mmio + PORT_CMD);
1052 static void ahci_start_port(struct ata_port *ap)
1054 /* enable FIS reception */
1055 ahci_start_fis_rx(ap);
1058 ahci_start_engine(ap);
1061 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1066 rc = ahci_stop_engine(ap);
1068 *emsg = "failed to stop engine";
1072 /* disable FIS reception */
1073 rc = ahci_stop_fis_rx(ap);
1075 *emsg = "failed stop FIS RX";
1082 static int ahci_reset_controller(struct ata_host *host)
1084 struct pci_dev *pdev = to_pci_dev(host->dev);
1085 struct ahci_host_priv *hpriv = host->private_data;
1086 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1089 /* we must be in AHCI mode, before using anything
1090 * AHCI-specific, such as HOST_RESET.
1092 ahci_enable_ahci(mmio);
1094 /* global controller reset */
1095 if (!ahci_skip_host_reset) {
1096 tmp = readl(mmio + HOST_CTL);
1097 if ((tmp & HOST_RESET) == 0) {
1098 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1099 readl(mmio + HOST_CTL); /* flush */
1102 /* reset must complete within 1 second, or
1103 * the hardware should be considered fried.
1107 tmp = readl(mmio + HOST_CTL);
1108 if (tmp & HOST_RESET) {
1109 dev_printk(KERN_ERR, host->dev,
1110 "controller reset failed (0x%x)\n", tmp);
1114 /* turn on AHCI mode */
1115 ahci_enable_ahci(mmio);
1117 /* Some registers might be cleared on reset. Restore
1120 ahci_restore_initial_config(host);
1122 dev_printk(KERN_INFO, host->dev,
1123 "skipping global host reset\n");
1125 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1129 pci_read_config_word(pdev, 0x92, &tmp16);
1130 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1131 tmp16 |= hpriv->port_map;
1132 pci_write_config_word(pdev, 0x92, tmp16);
1139 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1140 int port_no, void __iomem *mmio,
1141 void __iomem *port_mmio)
1143 const char *emsg = NULL;
1147 /* make sure port is not active */
1148 rc = ahci_deinit_port(ap, &emsg);
1150 dev_printk(KERN_WARNING, &pdev->dev,
1151 "%s (%d)\n", emsg, rc);
1154 tmp = readl(port_mmio + PORT_SCR_ERR);
1155 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1156 writel(tmp, port_mmio + PORT_SCR_ERR);
1158 /* clear port IRQ */
1159 tmp = readl(port_mmio + PORT_IRQ_STAT);
1160 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1162 writel(tmp, port_mmio + PORT_IRQ_STAT);
1164 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1167 static void ahci_init_controller(struct ata_host *host)
1169 struct ahci_host_priv *hpriv = host->private_data;
1170 struct pci_dev *pdev = to_pci_dev(host->dev);
1171 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1173 void __iomem *port_mmio;
1176 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1177 port_mmio = __ahci_port_base(host, 4);
1179 writel(0, port_mmio + PORT_IRQ_MASK);
1181 /* clear port IRQ */
1182 tmp = readl(port_mmio + PORT_IRQ_STAT);
1183 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1185 writel(tmp, port_mmio + PORT_IRQ_STAT);
1188 for (i = 0; i < host->n_ports; i++) {
1189 struct ata_port *ap = host->ports[i];
1191 port_mmio = ahci_port_base(ap);
1192 if (ata_port_is_dummy(ap))
1195 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1198 tmp = readl(mmio + HOST_CTL);
1199 VPRINTK("HOST_CTL 0x%x\n", tmp);
1200 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1201 tmp = readl(mmio + HOST_CTL);
1202 VPRINTK("HOST_CTL 0x%x\n", tmp);
1205 static void ahci_dev_config(struct ata_device *dev)
1207 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1209 if (hpriv->flags & AHCI_HFLAG_SECT255)
1210 dev->max_sectors = 255;
1213 static unsigned int ahci_dev_classify(struct ata_port *ap)
1215 void __iomem *port_mmio = ahci_port_base(ap);
1216 struct ata_taskfile tf;
1219 tmp = readl(port_mmio + PORT_SIG);
1220 tf.lbah = (tmp >> 24) & 0xff;
1221 tf.lbam = (tmp >> 16) & 0xff;
1222 tf.lbal = (tmp >> 8) & 0xff;
1223 tf.nsect = (tmp) & 0xff;
1225 return ata_dev_classify(&tf);
1228 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1231 dma_addr_t cmd_tbl_dma;
1233 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1235 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1236 pp->cmd_slot[tag].status = 0;
1237 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1238 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1241 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1243 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1244 struct ahci_host_priv *hpriv = ap->host->private_data;
1248 /* do we need to kick the port? */
1249 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1250 if (!busy && !force_restart)
1254 rc = ahci_stop_engine(ap);
1258 /* need to do CLO? */
1264 if (!(hpriv->cap & HOST_CAP_CLO)) {
1270 tmp = readl(port_mmio + PORT_CMD);
1271 tmp |= PORT_CMD_CLO;
1272 writel(tmp, port_mmio + PORT_CMD);
1275 tmp = ata_wait_register(port_mmio + PORT_CMD,
1276 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1277 if (tmp & PORT_CMD_CLO)
1280 /* restart engine */
1282 ahci_start_engine(ap);
1286 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1287 struct ata_taskfile *tf, int is_cmd, u16 flags,
1288 unsigned long timeout_msec)
1290 const u32 cmd_fis_len = 5; /* five dwords */
1291 struct ahci_port_priv *pp = ap->private_data;
1292 void __iomem *port_mmio = ahci_port_base(ap);
1293 u8 *fis = pp->cmd_tbl;
1296 /* prep the command */
1297 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1298 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1301 writel(1, port_mmio + PORT_CMD_ISSUE);
1304 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1307 ahci_kick_engine(ap, 1);
1311 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1316 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1317 int pmp, unsigned long deadline)
1319 struct ata_port *ap = link->ap;
1320 const char *reason = NULL;
1321 unsigned long now, msecs;
1322 struct ata_taskfile tf;
1327 if (ata_link_offline(link)) {
1328 DPRINTK("PHY reports no device\n");
1329 *class = ATA_DEV_NONE;
1333 /* prepare for SRST (AHCI-1.1 10.4.1) */
1334 rc = ahci_kick_engine(ap, 1);
1335 if (rc && rc != -EOPNOTSUPP)
1336 ata_link_printk(link, KERN_WARNING,
1337 "failed to reset engine (errno=%d)\n", rc);
1339 ata_tf_init(link->device, &tf);
1341 /* issue the first D2H Register FIS */
1344 if (time_after(now, deadline))
1345 msecs = jiffies_to_msecs(deadline - now);
1348 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1349 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1351 reason = "1st FIS failed";
1355 /* spec says at least 5us, but be generous and sleep for 1ms */
1358 /* issue the second D2H Register FIS */
1359 tf.ctl &= ~ATA_SRST;
1360 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1362 /* wait a while before checking status */
1363 ata_wait_after_reset(ap, deadline);
1365 rc = ata_wait_ready(ap, deadline);
1366 /* link occupied, -ENODEV too is an error */
1368 reason = "device not ready";
1371 *class = ahci_dev_classify(ap);
1373 DPRINTK("EXIT, class=%u\n", *class);
1377 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1381 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1382 unsigned long deadline)
1386 if (link->ap->flags & ATA_FLAG_PMP)
1387 pmp = SATA_PMP_CTRL_PORT;
1389 return ahci_do_softreset(link, class, pmp, deadline);
1392 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1393 unsigned long deadline)
1395 struct ata_port *ap = link->ap;
1396 struct ahci_port_priv *pp = ap->private_data;
1397 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1398 struct ata_taskfile tf;
1403 ahci_stop_engine(ap);
1405 /* clear D2H reception area to properly wait for D2H FIS */
1406 ata_tf_init(link->device, &tf);
1408 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1410 rc = sata_std_hardreset(link, class, deadline);
1412 ahci_start_engine(ap);
1414 if (rc == 0 && ata_link_online(link))
1415 *class = ahci_dev_classify(ap);
1416 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1417 *class = ATA_DEV_NONE;
1419 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1423 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1424 unsigned long deadline)
1426 struct ata_port *ap = link->ap;
1432 ahci_stop_engine(ap);
1434 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1437 /* vt8251 needs SError cleared for the port to operate */
1438 ahci_scr_read(ap, SCR_ERROR, &serror);
1439 ahci_scr_write(ap, SCR_ERROR, serror);
1441 ahci_start_engine(ap);
1443 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1445 /* vt8251 doesn't clear BSY on signature FIS reception,
1446 * request follow-up softreset.
1448 return rc ?: -EAGAIN;
1451 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1452 unsigned long deadline)
1454 struct ata_port *ap = link->ap;
1455 struct ahci_port_priv *pp = ap->private_data;
1456 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1457 struct ata_taskfile tf;
1460 ahci_stop_engine(ap);
1462 /* clear D2H reception area to properly wait for D2H FIS */
1463 ata_tf_init(link->device, &tf);
1465 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1467 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1470 ahci_start_engine(ap);
1472 if (rc || ata_link_offline(link))
1475 /* spec mandates ">= 2ms" before checking status */
1478 /* The pseudo configuration device on SIMG4726 attached to
1479 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1480 * hardreset if no device is attached to the first downstream
1481 * port && the pseudo device locks up on SRST w/ PMP==0. To
1482 * work around this, wait for !BSY only briefly. If BSY isn't
1483 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1484 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1486 * Wait for two seconds. Devices attached to downstream port
1487 * which can't process the following IDENTIFY after this will
1488 * have to be reset again. For most cases, this should
1489 * suffice while making probing snappish enough.
1491 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1493 ahci_kick_engine(ap, 0);
1498 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1500 struct ata_port *ap = link->ap;
1501 void __iomem *port_mmio = ahci_port_base(ap);
1504 ata_std_postreset(link, class);
1506 /* Make sure port's ATAPI bit is set appropriately */
1507 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1508 if (*class == ATA_DEV_ATAPI)
1509 new_tmp |= PORT_CMD_ATAPI;
1511 new_tmp &= ~PORT_CMD_ATAPI;
1512 if (new_tmp != tmp) {
1513 writel(new_tmp, port_mmio + PORT_CMD);
1514 readl(port_mmio + PORT_CMD); /* flush */
1518 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1519 unsigned long deadline)
1521 return ahci_do_softreset(link, class, link->pmp, deadline);
1524 static u8 ahci_check_status(struct ata_port *ap)
1526 void __iomem *mmio = ap->ioaddr.cmd_addr;
1528 return readl(mmio + PORT_TFDATA) & 0xFF;
1531 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1533 struct ahci_port_priv *pp = ap->private_data;
1534 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1536 ata_tf_from_fis(d2h_fis, tf);
1539 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1541 struct scatterlist *sg;
1542 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1548 * Next, the S/G list.
1550 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1551 dma_addr_t addr = sg_dma_address(sg);
1552 u32 sg_len = sg_dma_len(sg);
1554 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1555 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1556 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1562 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1564 struct ata_port *ap = qc->ap;
1565 struct ahci_port_priv *pp = ap->private_data;
1566 int is_atapi = ata_is_atapi(qc->tf.protocol);
1569 const u32 cmd_fis_len = 5; /* five dwords */
1570 unsigned int n_elem;
1573 * Fill in command table information. First, the header,
1574 * a SATA Register - Host to Device command FIS.
1576 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1578 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1580 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1581 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1585 if (qc->flags & ATA_QCFLAG_DMAMAP)
1586 n_elem = ahci_fill_sg(qc, cmd_tbl);
1589 * Fill in command slot information.
1591 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1592 if (qc->tf.flags & ATA_TFLAG_WRITE)
1593 opts |= AHCI_CMD_WRITE;
1595 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1597 ahci_fill_cmd_slot(pp, qc->tag, opts);
1600 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1602 struct ahci_host_priv *hpriv = ap->host->private_data;
1603 struct ahci_port_priv *pp = ap->private_data;
1604 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1605 struct ata_link *link = NULL;
1606 struct ata_queued_cmd *active_qc;
1607 struct ata_eh_info *active_ehi;
1610 /* determine active link */
1611 ata_port_for_each_link(link, ap)
1612 if (ata_link_active(link))
1617 active_qc = ata_qc_from_tag(ap, link->active_tag);
1618 active_ehi = &link->eh_info;
1620 /* record irq stat */
1621 ata_ehi_clear_desc(host_ehi);
1622 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1624 /* AHCI needs SError cleared; otherwise, it might lock up */
1625 ahci_scr_read(ap, SCR_ERROR, &serror);
1626 ahci_scr_write(ap, SCR_ERROR, serror);
1627 host_ehi->serror |= serror;
1629 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1630 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1631 irq_stat &= ~PORT_IRQ_IF_ERR;
1633 if (irq_stat & PORT_IRQ_TF_ERR) {
1634 /* If qc is active, charge it; otherwise, the active
1635 * link. There's no active qc on NCQ errors. It will
1636 * be determined by EH by reading log page 10h.
1639 active_qc->err_mask |= AC_ERR_DEV;
1641 active_ehi->err_mask |= AC_ERR_DEV;
1643 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1644 host_ehi->serror &= ~SERR_INTERNAL;
1647 if (irq_stat & PORT_IRQ_UNK_FIS) {
1648 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1650 active_ehi->err_mask |= AC_ERR_HSM;
1651 active_ehi->action |= ATA_EH_SOFTRESET;
1652 ata_ehi_push_desc(active_ehi,
1653 "unknown FIS %08x %08x %08x %08x" ,
1654 unk[0], unk[1], unk[2], unk[3]);
1657 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1658 active_ehi->err_mask |= AC_ERR_HSM;
1659 active_ehi->action |= ATA_EH_SOFTRESET;
1660 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1663 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1664 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1665 host_ehi->action |= ATA_EH_SOFTRESET;
1666 ata_ehi_push_desc(host_ehi, "host bus error");
1669 if (irq_stat & PORT_IRQ_IF_ERR) {
1670 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1671 host_ehi->action |= ATA_EH_SOFTRESET;
1672 ata_ehi_push_desc(host_ehi, "interface fatal error");
1675 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1676 ata_ehi_hotplugged(host_ehi);
1677 ata_ehi_push_desc(host_ehi, "%s",
1678 irq_stat & PORT_IRQ_CONNECT ?
1679 "connection status changed" : "PHY RDY changed");
1682 /* okay, let's hand over to EH */
1684 if (irq_stat & PORT_IRQ_FREEZE)
1685 ata_port_freeze(ap);
1690 static void ahci_port_intr(struct ata_port *ap)
1692 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1693 struct ata_eh_info *ehi = &ap->link.eh_info;
1694 struct ahci_port_priv *pp = ap->private_data;
1695 struct ahci_host_priv *hpriv = ap->host->private_data;
1696 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1697 u32 status, qc_active;
1700 status = readl(port_mmio + PORT_IRQ_STAT);
1701 writel(status, port_mmio + PORT_IRQ_STAT);
1703 /* ignore BAD_PMP while resetting */
1704 if (unlikely(resetting))
1705 status &= ~PORT_IRQ_BAD_PMP;
1707 /* If we are getting PhyRdy, this is
1708 * just a power state change, we should
1709 * clear out this, plus the PhyRdy/Comm
1710 * Wake bits from Serror
1712 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1713 (status & PORT_IRQ_PHYRDY)) {
1714 status &= ~PORT_IRQ_PHYRDY;
1715 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1718 if (unlikely(status & PORT_IRQ_ERROR)) {
1719 ahci_error_intr(ap, status);
1723 if (status & PORT_IRQ_SDB_FIS) {
1724 /* If SNotification is available, leave notification
1725 * handling to sata_async_notification(). If not,
1726 * emulate it by snooping SDB FIS RX area.
1728 * Snooping FIS RX area is probably cheaper than
1729 * poking SNotification but some constrollers which
1730 * implement SNotification, ICH9 for example, don't
1731 * store AN SDB FIS into receive area.
1733 if (hpriv->cap & HOST_CAP_SNTF)
1734 sata_async_notification(ap);
1736 /* If the 'N' bit in word 0 of the FIS is set,
1737 * we just received asynchronous notification.
1738 * Tell libata about it.
1740 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1741 u32 f0 = le32_to_cpu(f[0]);
1744 sata_async_notification(ap);
1748 /* pp->active_link is valid iff any command is in flight */
1749 if (ap->qc_active && pp->active_link->sactive)
1750 qc_active = readl(port_mmio + PORT_SCR_ACT);
1752 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1754 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1756 /* while resetting, invalid completions are expected */
1757 if (unlikely(rc < 0 && !resetting)) {
1758 ehi->err_mask |= AC_ERR_HSM;
1759 ehi->action |= ATA_EH_SOFTRESET;
1760 ata_port_freeze(ap);
1764 static void ahci_irq_clear(struct ata_port *ap)
1769 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1771 struct ata_host *host = dev_instance;
1772 struct ahci_host_priv *hpriv;
1773 unsigned int i, handled = 0;
1775 u32 irq_stat, irq_ack = 0;
1779 hpriv = host->private_data;
1780 mmio = host->iomap[AHCI_PCI_BAR];
1782 /* sigh. 0xffffffff is a valid return from h/w */
1783 irq_stat = readl(mmio + HOST_IRQ_STAT);
1784 irq_stat &= hpriv->port_map;
1788 spin_lock(&host->lock);
1790 for (i = 0; i < host->n_ports; i++) {
1791 struct ata_port *ap;
1793 if (!(irq_stat & (1 << i)))
1796 ap = host->ports[i];
1799 VPRINTK("port %u\n", i);
1801 VPRINTK("port %u (no irq)\n", i);
1802 if (ata_ratelimit())
1803 dev_printk(KERN_WARNING, host->dev,
1804 "interrupt on disabled port %u\n", i);
1807 irq_ack |= (1 << i);
1811 writel(irq_ack, mmio + HOST_IRQ_STAT);
1815 spin_unlock(&host->lock);
1819 return IRQ_RETVAL(handled);
1822 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1824 struct ata_port *ap = qc->ap;
1825 void __iomem *port_mmio = ahci_port_base(ap);
1826 struct ahci_port_priv *pp = ap->private_data;
1828 /* Keep track of the currently active link. It will be used
1829 * in completion path to determine whether NCQ phase is in
1832 pp->active_link = qc->dev->link;
1834 if (qc->tf.protocol == ATA_PROT_NCQ)
1835 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1836 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1837 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1842 static void ahci_freeze(struct ata_port *ap)
1844 void __iomem *port_mmio = ahci_port_base(ap);
1847 writel(0, port_mmio + PORT_IRQ_MASK);
1850 static void ahci_thaw(struct ata_port *ap)
1852 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1853 void __iomem *port_mmio = ahci_port_base(ap);
1855 struct ahci_port_priv *pp = ap->private_data;
1858 tmp = readl(port_mmio + PORT_IRQ_STAT);
1859 writel(tmp, port_mmio + PORT_IRQ_STAT);
1860 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1862 /* turn IRQ back on */
1863 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1866 static void ahci_error_handler(struct ata_port *ap)
1868 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1869 /* restart engine */
1870 ahci_stop_engine(ap);
1871 ahci_start_engine(ap);
1874 /* perform recovery */
1875 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1876 ahci_hardreset, ahci_postreset,
1877 sata_pmp_std_prereset, ahci_pmp_softreset,
1878 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1881 static void ahci_vt8251_error_handler(struct ata_port *ap)
1883 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1884 /* restart engine */
1885 ahci_stop_engine(ap);
1886 ahci_start_engine(ap);
1889 /* perform recovery */
1890 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1894 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1896 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1897 /* restart engine */
1898 ahci_stop_engine(ap);
1899 ahci_start_engine(ap);
1902 /* perform recovery */
1903 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1907 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1909 struct ata_port *ap = qc->ap;
1911 /* make DMA engine forget about the failed command */
1912 if (qc->flags & ATA_QCFLAG_FAILED)
1913 ahci_kick_engine(ap, 1);
1916 static void ahci_pmp_attach(struct ata_port *ap)
1918 void __iomem *port_mmio = ahci_port_base(ap);
1919 struct ahci_port_priv *pp = ap->private_data;
1922 cmd = readl(port_mmio + PORT_CMD);
1923 cmd |= PORT_CMD_PMP;
1924 writel(cmd, port_mmio + PORT_CMD);
1926 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1927 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1930 static void ahci_pmp_detach(struct ata_port *ap)
1932 void __iomem *port_mmio = ahci_port_base(ap);
1933 struct ahci_port_priv *pp = ap->private_data;
1936 cmd = readl(port_mmio + PORT_CMD);
1937 cmd &= ~PORT_CMD_PMP;
1938 writel(cmd, port_mmio + PORT_CMD);
1940 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1941 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1944 static int ahci_port_resume(struct ata_port *ap)
1947 ahci_start_port(ap);
1949 if (ap->nr_pmp_links)
1950 ahci_pmp_attach(ap);
1952 ahci_pmp_detach(ap);
1958 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1960 const char *emsg = NULL;
1963 rc = ahci_deinit_port(ap, &emsg);
1965 ahci_power_down(ap);
1967 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1968 ahci_start_port(ap);
1974 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1976 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1977 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1980 if (mesg.event & PM_EVENT_SLEEP) {
1981 /* AHCI spec rev1.1 section 8.3.3:
1982 * Software must disable interrupts prior to requesting a
1983 * transition of the HBA to D3 state.
1985 ctl = readl(mmio + HOST_CTL);
1986 ctl &= ~HOST_IRQ_EN;
1987 writel(ctl, mmio + HOST_CTL);
1988 readl(mmio + HOST_CTL); /* flush */
1991 return ata_pci_device_suspend(pdev, mesg);
1994 static int ahci_pci_device_resume(struct pci_dev *pdev)
1996 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1999 rc = ata_pci_device_do_resume(pdev);
2003 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2004 rc = ahci_reset_controller(host);
2008 ahci_init_controller(host);
2011 ata_host_resume(host);
2017 static int ahci_port_start(struct ata_port *ap)
2019 struct device *dev = ap->host->dev;
2020 struct ahci_port_priv *pp;
2024 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2028 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2032 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2035 * First item in chunk of DMA memory: 32-slot command table,
2036 * 32 bytes each in size
2039 pp->cmd_slot_dma = mem_dma;
2041 mem += AHCI_CMD_SLOT_SZ;
2042 mem_dma += AHCI_CMD_SLOT_SZ;
2045 * Second item: Received-FIS area
2048 pp->rx_fis_dma = mem_dma;
2050 mem += AHCI_RX_FIS_SZ;
2051 mem_dma += AHCI_RX_FIS_SZ;
2054 * Third item: data area for storing a single command
2055 * and its scatter-gather table
2058 pp->cmd_tbl_dma = mem_dma;
2061 * Save off initial list of interrupts to be enabled.
2062 * This could be changed later
2064 pp->intr_mask = DEF_PORT_IRQ;
2066 ap->private_data = pp;
2068 /* engage engines, captain */
2069 return ahci_port_resume(ap);
2072 static void ahci_port_stop(struct ata_port *ap)
2074 const char *emsg = NULL;
2077 /* de-initialize port */
2078 rc = ahci_deinit_port(ap, &emsg);
2080 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2083 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2088 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2089 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2091 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2093 dev_printk(KERN_ERR, &pdev->dev,
2094 "64-bit DMA enable failed\n");
2099 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2101 dev_printk(KERN_ERR, &pdev->dev,
2102 "32-bit DMA enable failed\n");
2105 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2107 dev_printk(KERN_ERR, &pdev->dev,
2108 "32-bit consistent DMA enable failed\n");
2115 static void ahci_print_info(struct ata_host *host)
2117 struct ahci_host_priv *hpriv = host->private_data;
2118 struct pci_dev *pdev = to_pci_dev(host->dev);
2119 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2120 u32 vers, cap, impl, speed;
2121 const char *speed_s;
2125 vers = readl(mmio + HOST_VERSION);
2127 impl = hpriv->port_map;
2129 speed = (cap >> 20) & 0xf;
2132 else if (speed == 2)
2137 pci_read_config_word(pdev, 0x0a, &cc);
2138 if (cc == PCI_CLASS_STORAGE_IDE)
2140 else if (cc == PCI_CLASS_STORAGE_SATA)
2142 else if (cc == PCI_CLASS_STORAGE_RAID)
2147 dev_printk(KERN_INFO, &pdev->dev,
2148 "AHCI %02x%02x.%02x%02x "
2149 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2152 (vers >> 24) & 0xff,
2153 (vers >> 16) & 0xff,
2157 ((cap >> 8) & 0x1f) + 1,
2163 dev_printk(KERN_INFO, &pdev->dev,
2169 cap & (1 << 31) ? "64bit " : "",
2170 cap & (1 << 30) ? "ncq " : "",
2171 cap & (1 << 29) ? "sntf " : "",
2172 cap & (1 << 28) ? "ilck " : "",
2173 cap & (1 << 27) ? "stag " : "",
2174 cap & (1 << 26) ? "pm " : "",
2175 cap & (1 << 25) ? "led " : "",
2177 cap & (1 << 24) ? "clo " : "",
2178 cap & (1 << 19) ? "nz " : "",
2179 cap & (1 << 18) ? "only " : "",
2180 cap & (1 << 17) ? "pmp " : "",
2181 cap & (1 << 15) ? "pio " : "",
2182 cap & (1 << 14) ? "slum " : "",
2183 cap & (1 << 13) ? "part " : ""
2187 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2188 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2189 * support PMP and the 4726 either directly exports the device
2190 * attached to the first downstream port or acts as a hardware storage
2191 * controller and emulate a single ATA device (can be RAID 0/1 or some
2192 * other configuration).
2194 * When there's no device attached to the first downstream port of the
2195 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2196 * configure the 4726. However, ATA emulation of the device is very
2197 * lame. It doesn't send signature D2H Reg FIS after the initial
2198 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2200 * The following function works around the problem by always using
2201 * hardreset on the port and not depending on receiving signature FIS
2202 * afterward. If signature FIS isn't received soon, ATA class is
2203 * assumed without follow-up softreset.
2205 static void ahci_p5wdh_workaround(struct ata_host *host)
2207 static struct dmi_system_id sysids[] = {
2209 .ident = "P5W DH Deluxe",
2211 DMI_MATCH(DMI_SYS_VENDOR,
2212 "ASUSTEK COMPUTER INC"),
2213 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2218 struct pci_dev *pdev = to_pci_dev(host->dev);
2220 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2221 dmi_check_system(sysids)) {
2222 struct ata_port *ap = host->ports[1];
2224 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2225 "Deluxe on-board SIMG4726 workaround\n");
2227 ap->ops = &ahci_p5wdh_ops;
2228 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2232 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2234 static int printed_version;
2235 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2236 const struct ata_port_info *ppi[] = { &pi, NULL };
2237 struct device *dev = &pdev->dev;
2238 struct ahci_host_priv *hpriv;
2239 struct ata_host *host;
2244 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2246 if (!printed_version++)
2247 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2249 /* acquire resources */
2250 rc = pcim_enable_device(pdev);
2254 /* AHCI controllers often implement SFF compatible interface.
2255 * Grab all PCI BARs just in case.
2257 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2259 pcim_pin_device(pdev);
2263 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2264 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2267 /* ICH6s share the same PCI ID for both piix and ahci
2268 * modes. Enabling ahci mode while MAP indicates
2269 * combined mode is a bad idea. Yield to ata_piix.
2271 pci_read_config_byte(pdev, ICH_MAP, &map);
2273 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2274 "combined mode, can't enable AHCI mode\n");
2279 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2282 hpriv->flags |= (unsigned long)pi.private_data;
2284 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2287 /* save initial config */
2288 ahci_save_initial_config(pdev, hpriv);
2291 if (hpriv->cap & HOST_CAP_NCQ)
2292 pi.flags |= ATA_FLAG_NCQ;
2294 if (hpriv->cap & HOST_CAP_PMP)
2295 pi.flags |= ATA_FLAG_PMP;
2297 /* CAP.NP sometimes indicate the index of the last enabled
2298 * port, at other times, that of the last possible port, so
2299 * determining the maximum port number requires looking at
2300 * both CAP.NP and port_map.
2302 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2304 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2307 host->iomap = pcim_iomap_table(pdev);
2308 host->private_data = hpriv;
2310 for (i = 0; i < host->n_ports; i++) {
2311 struct ata_port *ap = host->ports[i];
2312 void __iomem *port_mmio = ahci_port_base(ap);
2314 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2315 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2316 0x100 + ap->port_no * 0x80, "port");
2318 /* set initial link pm policy */
2319 ap->pm_policy = NOT_AVAILABLE;
2321 /* standard SATA port setup */
2322 if (hpriv->port_map & (1 << i))
2323 ap->ioaddr.cmd_addr = port_mmio;
2325 /* disabled/not-implemented port */
2327 ap->ops = &ata_dummy_port_ops;
2330 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2331 ahci_p5wdh_workaround(host);
2333 /* initialize adapter */
2334 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2338 rc = ahci_reset_controller(host);
2342 ahci_init_controller(host);
2343 ahci_print_info(host);
2345 pci_set_master(pdev);
2346 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2350 static int __init ahci_init(void)
2352 return pci_register_driver(&ahci_pci_driver);
2355 static void __exit ahci_exit(void)
2357 pci_unregister_driver(&ahci_pci_driver);
2361 MODULE_AUTHOR("Jeff Garzik");
2362 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2363 MODULE_LICENSE("GPL");
2364 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2365 MODULE_VERSION(DRV_VERSION);
2367 module_init(ahci_init);
2368 module_exit(ahci_exit);