drivers/ata/ahci_imx.c

   1 /*
   2  * copyright (c) 2013 Freescale Semiconductor, Inc.
   3  * Freescale IMX AHCI SATA platform driver
   4  *
   5  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program. If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/ahci_platform.h>
  25 #include <linux/of_device.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  28 #include <linux/libata.h>
  29 #include "ahci.h"
  30
  31 enum {
  32         /* Timer 1-ms Register */
  33         IMX_TIMER1MS                            = 0x00e0,
  34         /* Port0 PHY Control Register */
  35         IMX_P0PHYCR                             = 0x0178,
  36         IMX_P0PHYCR_TEST_PDDQ                   = 1 << 20,
  37         IMX_P0PHYCR_CR_READ                     = 1 << 19,
  38         IMX_P0PHYCR_CR_WRITE                    = 1 << 18,
  39         IMX_P0PHYCR_CR_CAP_DATA                 = 1 << 17,
  40         IMX_P0PHYCR_CR_CAP_ADDR                 = 1 << 16,
  41         /* Port0 PHY Status Register */
  42         IMX_P0PHYSR                             = 0x017c,
  43         IMX_P0PHYSR_CR_ACK                      = 1 << 18,
  44         IMX_P0PHYSR_CR_DATA_OUT                 = 0xffff << 0,
  45         /* Lane0 Output Status Register */
  46         IMX_LANE0_OUT_STAT                      = 0x2003,
  47         IMX_LANE0_OUT_STAT_RX_PLL_STATE         = 1 << 1,
  48         /* Clock Reset Register */
  49         IMX_CLOCK_RESET                         = 0x7f3f,
  50         IMX_CLOCK_RESET_RESET                   = 1 << 0,
  51 };
  52
  53 enum ahci_imx_type {
  54         AHCI_IMX53,
  55         AHCI_IMX6Q,
  56 };
  57
  58 struct imx_ahci_priv {
  59         struct platform_device *ahci_pdev;
  60         enum ahci_imx_type type;
  61         struct clk *ahb_clk;
  62         struct regmap *gpr;
  63         bool no_device;
  64         bool first_time;
  65         u32 phy_params;
  66 };
  67
  68 static int ahci_imx_hotplug;
  69 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
  70 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
  71
  72 static void ahci_imx_host_stop(struct ata_host *host);
  73
  74 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
  75 {
  76         int timeout = 10;
  77         u32 crval;
  78         u32 srval;
  79
  80         /* Assert or deassert the bit */
  81         crval = readl(mmio + IMX_P0PHYCR);
  82         if (assert)
  83                 crval |= bit;
  84         else
  85                 crval &= ~bit;
  86         writel(crval, mmio + IMX_P0PHYCR);
  87
  88         /* Wait for the cr_ack signal */
  89         do {
  90                 srval = readl(mmio + IMX_P0PHYSR);
  91                 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
  92                         break;
  93                 usleep_range(100, 200);
  94         } while (--timeout);
  95
  96         return timeout ? 0 : -ETIMEDOUT;
  97 }
  98
  99 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
 100 {
 101         u32 crval = addr;
 102         int ret;
 103
 104         /* Supply the address on cr_data_in */
 105         writel(crval, mmio + IMX_P0PHYCR);
 106
 107         /* Assert the cr_cap_addr signal */
 108         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
 109         if (ret)
 110                 return ret;
 111
 112         /* Deassert cr_cap_addr */
 113         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
 114         if (ret)
 115                 return ret;
 116
 117         return 0;
 118 }
 119
 120 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
 121 {
 122         u32 crval = val;
 123         int ret;
 124
 125         /* Supply the data on cr_data_in */
 126         writel(crval, mmio + IMX_P0PHYCR);
 127
 128         /* Assert the cr_cap_data signal */
 129         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
 130         if (ret)
 131                 return ret;
 132
 133         /* Deassert cr_cap_data */
 134         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
 135         if (ret)
 136                 return ret;
 137
 138         if (val & IMX_CLOCK_RESET_RESET) {
 139                 /*
 140                  * In case we're resetting the phy, it's unable to acknowledge,
 141                  * so we return immediately here.
 142                  */
 143                 crval |= IMX_P0PHYCR_CR_WRITE;
 144                 writel(crval, mmio + IMX_P0PHYCR);
 145                 goto out;
 146         }
 147
 148         /* Assert the cr_write signal */
 149         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
 150         if (ret)
 151                 return ret;
 152
 153         /* Deassert cr_write */
 154         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
 155         if (ret)
 156                 return ret;
 157
 158 out:
 159         return 0;
 160 }
 161
 162 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
 163 {
 164         int ret;
 165
 166         /* Assert the cr_read signal */
 167         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
 168         if (ret)
 169                 return ret;
 170
 171         /* Capture the data from cr_data_out[] */
 172         *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
 173
 174         /* Deassert cr_read */
 175         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
 176         if (ret)
 177                 return ret;
 178
 179         return 0;
 180 }
 181
 182 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
 183 {
 184         void __iomem *mmio = hpriv->mmio;
 185         int timeout = 10;
 186         u16 val;
 187         int ret;
 188
 189         /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
 190         ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
 191         if (ret)
 192                 return ret;
 193         ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
 194         if (ret)
 195                 return ret;
 196
 197         /* Wait for PHY RX_PLL to be stable */
 198         do {
 199                 usleep_range(100, 200);
 200                 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
 201                 if (ret)
 202                         return ret;
 203                 ret = imx_phy_reg_read(&val, mmio);
 204                 if (ret)
 205                         return ret;
 206                 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
 207                         break;
 208         } while (--timeout);
 209
 210         return timeout ? 0 : -ETIMEDOUT;
 211 }
 212
 213 static int imx_sata_enable(struct ahci_host_priv *hpriv)
 214 {
 215         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 216         struct device *dev = &imxpriv->ahci_pdev->dev;
 217         int ret;
 218
 219         if (imxpriv->no_device)
 220                 return 0;
 221
 222         if (hpriv->target_pwr) {
 223                 ret = regulator_enable(hpriv->target_pwr);
 224                 if (ret)
 225                         return ret;
 226         }
 227
 228         ret = ahci_platform_enable_clks(hpriv);
 229         if (ret < 0)
 230                 goto disable_regulator;
 231
 232         if (imxpriv->type == AHCI_IMX6Q) {
 233                 /*
 234                  * set PHY Paremeters, two steps to configure the GPR13,
 235                  * one write for rest of parameters, mask of first write
 236                  * is 0x07ffffff, and the other one write for setting
 237                  * the mpll_clk_en.
 238                  */
 239                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 240                                    IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
 241                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
 242                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
 243                                    IMX6Q_GPR13_SATA_SPD_MODE_MASK |
 244                                    IMX6Q_GPR13_SATA_MPLL_SS_EN |
 245                                    IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
 246                                    IMX6Q_GPR13_SATA_TX_BOOST_MASK |
 247                                    IMX6Q_GPR13_SATA_TX_LVL_MASK |
 248                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN |
 249                                    IMX6Q_GPR13_SATA_TX_EDGE_RATE,
 250                                    imxpriv->phy_params);
 251                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 252                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 253                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 254
 255                 usleep_range(100, 200);
 256
 257                 ret = imx_sata_phy_reset(hpriv);
 258                 if (ret) {
 259                         dev_err(dev, "failed to reset phy: %d\n", ret);
 260                         goto disable_clk;
 261                 }
 262         }
 263
 264         usleep_range(1000, 2000);
 265
 266         return 0;
 267
 268 disable_clk:
 269         clk_disable_unprepare(imxpriv->sata_ref_clk);
 270 disable_regulator:
 271         if (hpriv->target_pwr)
 272                 regulator_disable(hpriv->target_pwr);
 273
 274         return ret;
 275 }
 276
 277 static void imx_sata_disable(struct ahci_host_priv *hpriv)
 278 {
 279         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 280
 281         if (imxpriv->no_device)
 282                 return;
 283
 284         if (imxpriv->type == AHCI_IMX6Q) {
 285                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 286                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 287                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 288         }
 289
 290         ahci_platform_disable_clks(hpriv);
 291
 292         if (hpriv->target_pwr)
 293                 regulator_disable(hpriv->target_pwr);
 294 }
 295
 296 static void ahci_imx_error_handler(struct ata_port *ap)
 297 {
 298         u32 reg_val;
 299         struct ata_device *dev;
 300         struct ata_host *host = dev_get_drvdata(ap->dev);
 301         struct ahci_host_priv *hpriv = host->private_data;
 302         void __iomem *mmio = hpriv->mmio;
 303         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 304
 305         ahci_error_handler(ap);
 306
 307         if (!(imxpriv->first_time) || ahci_imx_hotplug)
 308                 return;
 309
 310         imxpriv->first_time = false;
 311
 312         ata_for_each_dev(dev, &ap->link, ENABLED)
 313                 return;
 314         /*
 315          * Disable link to save power.  An imx ahci port can't be recovered
 316          * without full reset once the pddq mode is enabled making it
 317          * impossible to use as part of libata LPM.
 318          */
 319         reg_val = readl(mmio + IMX_P0PHYCR);
 320         writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
 321         imx_sata_disable(hpriv);
 322         imxpriv->no_device = true;
 323 }
 324
 325 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
 326                        unsigned long deadline)
 327 {
 328         struct ata_port *ap = link->ap;
 329         struct ata_host *host = dev_get_drvdata(ap->dev);
 330         struct ahci_host_priv *hpriv = host->private_data;
 331         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 332         int ret = -EIO;
 333
 334         if (imxpriv->type == AHCI_IMX53)
 335                 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
 336         else if (imxpriv->type == AHCI_IMX6Q)
 337                 ret = ahci_ops.softreset(link, class, deadline);
 338
 339         return ret;
 340 }
 341
 342 static struct ata_port_operations ahci_imx_ops = {
 343         .inherits       = &ahci_ops,
 344         .host_stop      = ahci_imx_host_stop,
 345         .error_handler  = ahci_imx_error_handler,
 346         .softreset      = ahci_imx_softreset,
 347 };
 348
 349 static const struct ata_port_info ahci_imx_port_info = {
 350         .flags          = AHCI_FLAG_COMMON,
 351         .pio_mask       = ATA_PIO4,
 352         .udma_mask      = ATA_UDMA6,
 353         .port_ops       = &ahci_imx_ops,
 354 };
 355
 356 static const struct of_device_id imx_ahci_of_match[] = {
 357         { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
 358         { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
 359         {},
 360 };
 361 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
 362
 363 struct reg_value {
 364         u32 of_value;
 365         u32 reg_value;
 366 };
 367
 368 struct reg_property {
 369         const char *name;
 370         const struct reg_value *values;
 371         size_t num_values;
 372         u32 def_value;
 373         u32 set_value;
 374 };
 375
 376 static const struct reg_value gpr13_tx_level[] = {
 377         {  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
 378         {  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
 379         {  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
 380         {  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
 381         {  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
 382         {  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
 383         {  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
 384         { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
 385         { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
 386         { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
 387         { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
 388         { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
 389         { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
 390         { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
 391         { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
 392         { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
 393         { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
 394         { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
 395         { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
 396         { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
 397         { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
 398         { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
 399         { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
 400         { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
 401         { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
 402         { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
 403         { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
 404         { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
 405         { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
 406         { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
 407         { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
 408         { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
 409 };
 410
 411 static const struct reg_value gpr13_tx_boost[] = {
 412         {    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
 413         {  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
 414         {  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
 415         { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
 416         { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
 417         { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
 418         { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
 419         { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
 420         { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
 421         { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
 422         { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
 423         { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
 424         { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
 425         { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
 426         { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
 427         { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
 428 };
 429
 430 static const struct reg_value gpr13_tx_atten[] = {
 431         {  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
 432         {  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
 433         { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
 434         { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
 435         { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
 436         { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
 437 };
 438
 439 static const struct reg_value gpr13_rx_eq[] = {
 440         {  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
 441         { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
 442         { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
 443         { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
 444         { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
 445         { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
 446         { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
 447         { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
 448 };
 449
 450 static const struct reg_property gpr13_props[] = {
 451         {
 452                 .name = "fsl,transmit-level-mV",
 453                 .values = gpr13_tx_level,
 454                 .num_values = ARRAY_SIZE(gpr13_tx_level),
 455                 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
 456         }, {
 457                 .name = "fsl,transmit-boost-mdB",
 458                 .values = gpr13_tx_boost,
 459                 .num_values = ARRAY_SIZE(gpr13_tx_boost),
 460                 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
 461         }, {
 462                 .name = "fsl,transmit-atten-16ths",
 463                 .values = gpr13_tx_atten,
 464                 .num_values = ARRAY_SIZE(gpr13_tx_atten),
 465                 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
 466         }, {
 467                 .name = "fsl,receive-eq-mdB",
 468                 .values = gpr13_rx_eq,
 469                 .num_values = ARRAY_SIZE(gpr13_rx_eq),
 470                 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
 471         }, {
 472                 .name = "fsl,no-spread-spectrum",
 473                 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
 474                 .set_value = 0,
 475         },
 476 };
 477
 478 static u32 imx_ahci_parse_props(struct device *dev,
 479                                 const struct reg_property *prop, size_t num)
 480 {
 481         struct device_node *np = dev->of_node;
 482         u32 reg_value = 0;
 483         int i, j;
 484
 485         for (i = 0; i < num; i++, prop++) {
 486                 u32 of_val;
 487
 488                 if (prop->num_values == 0) {
 489                         if (of_property_read_bool(np, prop->name))
 490                                 reg_value |= prop->set_value;
 491                         else
 492                                 reg_value |= prop->def_value;
 493                         continue;
 494                 }
 495
 496                 if (of_property_read_u32(np, prop->name, &of_val)) {
 497                         dev_info(dev, "%s not specified, using %08x\n",
 498                                 prop->name, prop->def_value);
 499                         reg_value |= prop->def_value;
 500                         continue;
 501                 }
 502
 503                 for (j = 0; j < prop->num_values; j++) {
 504                         if (prop->values[j].of_value == of_val) {
 505                                 dev_info(dev, "%s value %u, using %08x\n",
 506                                         prop->name, of_val, prop->values[j].reg_value);
 507                                 reg_value |= prop->values[j].reg_value;
 508                                 break;
 509                         }
 510                 }
 511
 512                 if (j == prop->num_values) {
 513                         dev_err(dev, "DT property %s is not a valid value\n",
 514                                 prop->name);
 515                         reg_value |= prop->def_value;
 516                 }
 517         }
 518
 519         return reg_value;
 520 }
 521
 522 static int imx_ahci_probe(struct platform_device *pdev)
 523 {
 524         struct device *dev = &pdev->dev;
 525         const struct of_device_id *of_id;
 526         struct ahci_host_priv *hpriv;
 527         struct imx_ahci_priv *imxpriv;
 528         unsigned int reg_val;
 529         int ret;
 530
 531         of_id = of_match_device(imx_ahci_of_match, dev);
 532         if (!of_id)
 533                 return -EINVAL;
 534
 535         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
 536         if (!imxpriv)
 537                 return -ENOMEM;
 538
 539         imxpriv->ahci_pdev = pdev;
 540         imxpriv->no_device = false;
 541         imxpriv->first_time = true;
 542         imxpriv->type = (enum ahci_imx_type)of_id->data;
 543         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
 544         if (IS_ERR(imxpriv->ahb_clk)) {
 545                 dev_err(dev, "can't get ahb clock.\n");
 546                 return PTR_ERR(imxpriv->ahb_clk);
 547         }
 548
 549         if (imxpriv->type == AHCI_IMX6Q) {
 550                 u32 reg_value;
 551
 552                 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
 553                                                         "fsl,imx6q-iomuxc-gpr");
 554                 if (IS_ERR(imxpriv->gpr)) {
 555                         dev_err(dev,
 556                                 "failed to find fsl,imx6q-iomux-gpr regmap\n");
 557                         return PTR_ERR(imxpriv->gpr);
 558                 }
 559
 560                 reg_value = imx_ahci_parse_props(dev, gpr13_props,
 561                                                  ARRAY_SIZE(gpr13_props));
 562
 563                 imxpriv->phy_params =
 564                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
 565                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
 566                                    IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
 567                                    reg_value;
 568         }
 569
 570         hpriv = ahci_platform_get_resources(pdev);
 571         if (IS_ERR(hpriv))
 572                 return PTR_ERR(hpriv);
 573
 574         hpriv->plat_data = imxpriv;
 575
 576         ret = imx_sata_enable(hpriv);
 577         if (ret)
 578                 return ret;
 579
 580         /*
 581          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
 582          * and IP vendor specific register IMX_TIMER1MS.
 583          * Configure CAP_SSS (support stagered spin up).
 584          * Implement the port0.
 585          * Get the ahb clock rate, and configure the TIMER1MS register.
 586          */
 587         reg_val = readl(hpriv->mmio + HOST_CAP);
 588         if (!(reg_val & HOST_CAP_SSS)) {
 589                 reg_val |= HOST_CAP_SSS;
 590                 writel(reg_val, hpriv->mmio + HOST_CAP);
 591         }
 592         reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
 593         if (!(reg_val & 0x1)) {
 594                 reg_val |= 0x1;
 595                 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
 596         }
 597
 598         reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
 599         writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
 600
 601         ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
 602                                       0, 0, 0);
 603         if (ret)
 604                 imx_sata_disable(hpriv);
 605
 606         return ret;
 607 }
 608
 609 static void ahci_imx_host_stop(struct ata_host *host)
 610 {
 611         struct ahci_host_priv *hpriv = host->private_data;
 612
 613         imx_sata_disable(hpriv);
 614 }
 615
 616 #ifdef CONFIG_PM_SLEEP
 617 static int imx_ahci_suspend(struct device *dev)
 618 {
 619         struct ata_host *host = dev_get_drvdata(dev);
 620         struct ahci_host_priv *hpriv = host->private_data;
 621         int ret;
 622
 623         ret = ahci_platform_suspend_host(dev);
 624         if (ret)
 625                 return ret;
 626
 627         imx_sata_disable(hpriv);
 628
 629         return 0;
 630 }
 631
 632 static int imx_ahci_resume(struct device *dev)
 633 {
 634         struct ata_host *host = dev_get_drvdata(dev);
 635         struct ahci_host_priv *hpriv = host->private_data;
 636         int ret;
 637
 638         ret = imx_sata_enable(hpriv);
 639         if (ret)
 640                 return ret;
 641
 642         return ahci_platform_resume_host(dev);
 643 }
 644 #endif
 645
 646 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
 647
 648 static struct platform_driver imx_ahci_driver = {
 649         .probe = imx_ahci_probe,
 650         .remove = ata_platform_remove_one,
 651         .driver = {
 652                 .name = "ahci-imx",
 653                 .owner = THIS_MODULE,
 654                 .of_match_table = imx_ahci_of_match,
 655                 .pm = &ahci_imx_pm_ops,
 656         },
 657 };
 658 module_platform_driver(imx_ahci_driver);
 659
 660 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
 661 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
 662 MODULE_LICENSE("GPL");
 663 MODULE_ALIAS("ahci:imx");