2 * AppliedMicro X-Gene SoC SATA Host Controller Driver
4 * Copyright (c) 2014, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 * Tuan Phan <tphan@apm.com>
7 * Suman Tripathi <stripathi@apm.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 * NOTE: PM support is not currently available.
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/ahci_platform.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/phy/phy.h>
33 /* Max # of disk per a controller */
34 #define MAX_AHCI_CHN_PERCTR 2
37 #define SATA_ENET_CONFIG_REG 0x00000000
38 #define CFG_SATA_ENET_SELECT_MASK 0x00000001
40 /* SATA core host controller CSR */
41 #define SLVRDERRATTRIBUTES 0x00000000
42 #define SLVWRERRATTRIBUTES 0x00000004
43 #define MSTRDERRATTRIBUTES 0x00000008
44 #define MSTWRERRATTRIBUTES 0x0000000c
45 #define BUSCTLREG 0x00000014
46 #define IOFMSTRWAUX 0x00000018
47 #define INTSTATUSMASK 0x0000002c
48 #define ERRINTSTATUS 0x00000030
49 #define ERRINTSTATUSMASK 0x00000034
51 /* SATA host AHCI CSR */
52 #define PORTCFG 0x000000a4
53 #define PORTADDR_SET(dst, src) \
54 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
55 #define PORTPHY1CFG 0x000000a8
56 #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
57 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
58 #define PORTPHY2CFG 0x000000ac
59 #define PORTPHY3CFG 0x000000b0
60 #define PORTPHY4CFG 0x000000b4
61 #define PORTPHY5CFG 0x000000b8
62 #define SCTL0 0x0000012C
63 #define PORTPHY5CFG_RTCHG_SET(dst, src) \
64 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
65 #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
66 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
67 #define PORTAXICFG 0x000000bc
68 #define PORTAXICFG_OUTTRANS_SET(dst, src) \
69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
70 #define PORTRANSCFG 0x000000c8
71 #define PORTRANSCFG_RXWM_SET(dst, src) \
72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
74 /* SATA host controller AXI CSR */
75 #define INT_SLV_TMOMASK 0x00000010
77 /* SATA diagnostic CSR */
78 #define CFG_MEM_RAM_SHUTDOWN 0x00000070
79 #define BLOCK_MEM_RDY 0x00000074
81 /* Max retry for link down */
82 #define MAX_LINK_DOWN_RETRY 3
84 struct xgene_ahci_context {
85 struct ahci_host_priv *hpriv;
87 u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
88 void __iomem *csr_core; /* Core CSR address of IP */
89 void __iomem *csr_diag; /* Diag CSR address of IP */
90 void __iomem *csr_axi; /* AXI CSR address of IP */
91 void __iomem *csr_mux; /* MUX CSR address of IP */
94 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
96 dev_dbg(ctx->dev, "Release memory from shutdown\n");
97 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
98 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
99 msleep(1); /* reset may take up to 1ms */
100 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
101 dev_err(ctx->dev, "failed to release memory from shutdown\n");
108 * xgene_ahci_restart_engine - Restart the dma engine.
109 * @ap : ATA port of interest
111 * Restarts the dma engine inside the controller.
113 static int xgene_ahci_restart_engine(struct ata_port *ap)
115 struct ahci_host_priv *hpriv = ap->host->private_data;
117 ahci_stop_engine(ap);
118 ahci_start_fis_rx(ap);
119 hpriv->start_engine(ap);
125 * xgene_ahci_qc_issue - Issue commands to the device
126 * @qc: Command to issue
128 * Due to Hardware errata for IDENTIFY DEVICE command and PACKET
129 * command of ATAPI protocol set, the controller cannot clear the BSY bit
130 * after receiving the PIO setup FIS. This results in the DMA state machine
131 * going into the CMFatalErrorUpdate state and locks up. By restarting the
132 * DMA engine, it removes the controller out of lock up state.
134 static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
136 struct ata_port *ap = qc->ap;
137 struct ahci_host_priv *hpriv = ap->host->private_data;
138 struct xgene_ahci_context *ctx = hpriv->plat_data;
141 if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
142 (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET)))
143 xgene_ahci_restart_engine(ap);
145 rc = ahci_qc_issue(qc);
147 /* Save the last command issued */
148 ctx->last_cmd[ap->port_no] = qc->tf.command;
153 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
155 void __iomem *diagcsr = ctx->csr_diag;
157 return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
158 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
162 * xgene_ahci_read_id - Read ID data from the specified device
164 * @tf: proposed taskfile
167 * This custom read ID function is required due to the fact that the HW
168 * does not support DEVSLP.
170 static unsigned int xgene_ahci_read_id(struct ata_device *dev,
171 struct ata_taskfile *tf, u16 *id)
175 err_mask = ata_do_dev_read_id(dev, tf, id);
180 * Mask reserved area. Word78 spec of Link Power Management
182 * bit7: NCQ autosence
183 * bit6: Software settings preservation supported
185 * bit4: In-order sata delivery supported
186 * bit3: DIPM requests supported
187 * bit2: DMA Setup FIS Auto-Activate optimization supported
188 * bit1: DMA Setup FIX non-Zero buffer offsets supported
191 * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
193 id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
198 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
200 void __iomem *mmio = ctx->hpriv->mmio;
203 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
205 val = readl(mmio + PORTCFG);
206 val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
207 writel(val, mmio + PORTCFG);
208 readl(mmio + PORTCFG); /* Force a barrier */
209 /* Disable fix rate */
210 writel(0x0001fffe, mmio + PORTPHY1CFG);
211 readl(mmio + PORTPHY1CFG); /* Force a barrier */
212 writel(0x28183219, mmio + PORTPHY2CFG);
213 readl(mmio + PORTPHY2CFG); /* Force a barrier */
214 writel(0x13081008, mmio + PORTPHY3CFG);
215 readl(mmio + PORTPHY3CFG); /* Force a barrier */
216 writel(0x00480815, mmio + PORTPHY4CFG);
217 readl(mmio + PORTPHY4CFG); /* Force a barrier */
218 /* Set window negotiation */
219 val = readl(mmio + PORTPHY5CFG);
220 val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
221 writel(val, mmio + PORTPHY5CFG);
222 readl(mmio + PORTPHY5CFG); /* Force a barrier */
223 val = readl(mmio + PORTAXICFG);
224 val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
225 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
226 writel(val, mmio + PORTAXICFG);
227 readl(mmio + PORTAXICFG); /* Force a barrier */
228 /* Set the watermark threshold of the receive FIFO */
229 val = readl(mmio + PORTRANSCFG);
230 val = PORTRANSCFG_RXWM_SET(val, 0x30);
231 writel(val, mmio + PORTRANSCFG);
235 * xgene_ahci_do_hardreset - Issue the actual COMRESET
236 * @link: link to reset
237 * @deadline: deadline jiffies for the operation
238 * @online: Return value to indicate if device online
240 * Due to the limitation of the hardware PHY, a difference set of setting is
241 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
242 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
243 * report disparity error and etc. In addition, during COMRESET, there can
244 * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
245 * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
246 * reboot cycle regression, sometimes the PHY reports link down even if the
247 * device is present because of speed negotiation failure. so need to retry
248 * the COMRESET to get the link up. The following algorithm is followed to
249 * proper configure the hardware PHY during COMRESET:
252 * 1. Start the PHY at Gen3 speed (default setting)
253 * 2. Issue the COMRESET
254 * 3. If no link, go to Alg Part 3
255 * 4. If link up, determine if the negotiated speed matches the PHY
257 * 5. If they matched, go to Alg Part 2
258 * 6. If they do not matched and first time, configure the PHY for the linked
259 * up disk speed and repeat step 2
260 * 7. Go to Alg Part 2
263 * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
264 * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
265 * 2. Go to Alg Part 4
268 * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
269 * communication establishment failed and maximum link down attempts are
270 * less than Max attempts 3 then goto Alg Part 1.
271 * 2. Go to Alg Part 4.
274 * 1. Clear any pending from register PORT_SCR_ERR.
276 * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
277 * and until the underlying PHY supports an method to reset the receiver
278 * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
279 * an warning message will be printed.
281 static int xgene_ahci_do_hardreset(struct ata_link *link,
282 unsigned long deadline, bool *online)
284 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
285 struct ata_port *ap = link->ap;
286 struct ahci_host_priv *hpriv = ap->host->private_data;
287 struct xgene_ahci_context *ctx = hpriv->plat_data;
288 struct ahci_port_priv *pp = ap->private_data;
289 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
290 void __iomem *port_mmio = ahci_port_base(ap);
291 struct ata_taskfile tf;
292 int link_down_retry = 0;
297 /* clear D2H reception area to properly wait for D2H FIS */
298 ata_tf_init(link->device, &tf);
299 tf.command = ATA_BUSY;
300 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
301 rc = sata_link_hardreset(link, timing, deadline, online,
304 val = readl(port_mmio + PORT_SCR_ERR);
305 if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
306 dev_warn(ctx->dev, "link has error\n");
310 sata_scr_read(link, SCR_STATUS, &sstatus);
311 } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
312 (sstatus & 0xff) == 0x1);
314 /* clear all errors if any pending */
315 val = readl(port_mmio + PORT_SCR_ERR);
316 writel(val, port_mmio + PORT_SCR_ERR);
321 static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
322 unsigned long deadline)
324 struct ata_port *ap = link->ap;
325 struct ahci_host_priv *hpriv = ap->host->private_data;
326 void __iomem *port_mmio = ahci_port_base(ap);
333 u32 portrxfishi_saved;
335 /* As hardreset resets these CSR, save it to restore later */
336 portcmd_saved = readl(port_mmio + PORT_CMD);
337 portclb_saved = readl(port_mmio + PORT_LST_ADDR);
338 portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
339 portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
340 portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
342 ahci_stop_engine(ap);
344 rc = xgene_ahci_do_hardreset(link, deadline, &online);
346 /* As controller hardreset clears them, restore them */
347 writel(portcmd_saved, port_mmio + PORT_CMD);
348 writel(portclb_saved, port_mmio + PORT_LST_ADDR);
349 writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
350 writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
351 writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
353 hpriv->start_engine(ap);
356 *class = ahci_dev_classify(ap);
361 static void xgene_ahci_host_stop(struct ata_host *host)
363 struct ahci_host_priv *hpriv = host->private_data;
365 ahci_platform_disable_resources(hpriv);
368 static struct ata_port_operations xgene_ahci_ops = {
369 .inherits = &ahci_ops,
370 .host_stop = xgene_ahci_host_stop,
371 .hardreset = xgene_ahci_hardreset,
372 .read_id = xgene_ahci_read_id,
373 .qc_issue = xgene_ahci_qc_issue,
376 static const struct ata_port_info xgene_ahci_port_info = {
377 .flags = AHCI_FLAG_COMMON,
378 .pio_mask = ATA_PIO4,
379 .udma_mask = ATA_UDMA6,
380 .port_ops = &xgene_ahci_ops,
383 static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
385 struct xgene_ahci_context *ctx = hpriv->plat_data;
390 /* Remove IP RAM out of shutdown */
391 rc = xgene_ahci_init_memram(ctx);
395 for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
396 xgene_ahci_set_phy_cfg(ctx, i);
398 /* AXI disable Mask */
399 writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
400 readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
401 writel(0, ctx->csr_core + INTSTATUSMASK);
402 val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
403 dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
406 writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
407 readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
408 writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
409 readl(ctx->csr_axi + INT_SLV_TMOMASK);
411 /* Enable AXI Interrupt */
412 writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
413 writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
414 writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
415 writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
417 /* Enable coherency */
418 val = readl(ctx->csr_core + BUSCTLREG);
419 val &= ~0x00000002; /* Enable write coherency */
420 val &= ~0x00000001; /* Enable read coherency */
421 writel(val, ctx->csr_core + BUSCTLREG);
423 val = readl(ctx->csr_core + IOFMSTRWAUX);
424 val |= (1 << 3); /* Enable read coherency */
425 val |= (1 << 9); /* Enable write coherency */
426 writel(val, ctx->csr_core + IOFMSTRWAUX);
427 val = readl(ctx->csr_core + IOFMSTRWAUX);
428 dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
434 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
438 /* Check for optional MUX resource */
442 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
443 val &= ~CFG_SATA_ENET_SELECT_MASK;
444 writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
445 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
446 return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
449 static int xgene_ahci_probe(struct platform_device *pdev)
451 struct device *dev = &pdev->dev;
452 struct ahci_host_priv *hpriv;
453 struct xgene_ahci_context *ctx;
454 struct resource *res;
457 hpriv = ahci_platform_get_resources(pdev);
459 return PTR_ERR(hpriv);
461 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
465 hpriv->plat_data = ctx;
469 /* Retrieve the IP core resource */
470 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
471 ctx->csr_core = devm_ioremap_resource(dev, res);
472 if (IS_ERR(ctx->csr_core))
473 return PTR_ERR(ctx->csr_core);
475 /* Retrieve the IP diagnostic resource */
476 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
477 ctx->csr_diag = devm_ioremap_resource(dev, res);
478 if (IS_ERR(ctx->csr_diag))
479 return PTR_ERR(ctx->csr_diag);
481 /* Retrieve the IP AXI resource */
482 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
483 ctx->csr_axi = devm_ioremap_resource(dev, res);
484 if (IS_ERR(ctx->csr_axi))
485 return PTR_ERR(ctx->csr_axi);
487 /* Retrieve the optional IP mux resource */
488 res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
490 void __iomem *csr = devm_ioremap_resource(dev, res);
497 dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
501 if ((rc = xgene_ahci_mux_select(ctx))) {
502 dev_err(dev, "SATA mux selection failed error %d\n", rc);
506 if (xgene_ahci_is_memram_inited(ctx)) {
507 dev_info(dev, "skip clock and PHY initialization\n");
511 /* Due to errata, HW requires full toggle transition */
512 rc = ahci_platform_enable_clks(hpriv);
514 goto disable_resources;
515 ahci_platform_disable_clks(hpriv);
517 rc = ahci_platform_enable_resources(hpriv);
519 goto disable_resources;
521 /* Configure the host controller */
522 xgene_ahci_hw_init(hpriv);
524 hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
526 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
528 goto disable_resources;
530 dev_dbg(dev, "X-Gene SATA host controller initialized\n");
534 ahci_platform_disable_resources(hpriv);
538 static const struct of_device_id xgene_ahci_of_match[] = {
539 {.compatible = "apm,xgene-ahci"},
542 MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
544 static struct platform_driver xgene_ahci_driver = {
545 .probe = xgene_ahci_probe,
546 .remove = ata_platform_remove_one,
548 .name = "xgene-ahci",
549 .of_match_table = xgene_ahci_of_match,
553 module_platform_driver(xgene_ahci_driver);
555 MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
556 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
557 MODULE_LICENSE("GPL");
558 MODULE_VERSION("0.4");