2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
49 static int ahci_skip_host_reset;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72 static int ahci_port_start(struct ata_port *ap);
73 static void ahci_port_stop(struct ata_port *ap);
74 static void ahci_qc_prep(struct ata_queued_cmd *qc);
75 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76 static void ahci_freeze(struct ata_port *ap);
77 static void ahci_thaw(struct ata_port *ap);
78 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static void ahci_dev_config(struct ata_device *dev);
93 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96 static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98 static void ahci_init_sw_activity(struct ata_link *link);
100 static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
113 static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
122 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
133 &dev_attr_em_message_supported,
136 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
138 struct device_attribute *ahci_sdev_attrs[] = {
139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
143 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
145 struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
153 .freeze = ahci_freeze,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
168 .set_lpm = ahci_set_lpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 .transmit_led_message = ahci_transmit_led_message,
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
181 EXPORT_SYMBOL_GPL(ahci_ops);
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
189 static bool ahci_em_messages __read_mostly = true;
190 EXPORT_SYMBOL_GPL(ahci_em_messages);
191 module_param(ahci_em_messages, bool, 0444);
192 /* add other LED protocol types when they become supported */
193 MODULE_PARM_DESC(ahci_em_messages,
194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
196 /* device sleep idle timeout in ms */
197 static int devslp_idle_timeout __read_mostly = 1000;
198 module_param(devslp_idle_timeout, int, 0644);
199 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
201 static void ahci_enable_ahci(void __iomem *mmio)
206 /* turn on AHCI_EN */
207 tmp = readl(mmio + HOST_CTL);
208 if (tmp & HOST_AHCI_EN)
211 /* Some controllers need AHCI_EN to be written multiple times.
212 * Try a few times before giving up.
214 for (i = 0; i < 5; i++) {
216 writel(tmp, mmio + HOST_CTL);
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
218 if (tmp & HOST_AHCI_EN)
226 static ssize_t ahci_show_host_caps(struct device *dev,
227 struct device_attribute *attr, char *buf)
229 struct Scsi_Host *shost = class_to_shost(dev);
230 struct ata_port *ap = ata_shost_to_port(shost);
231 struct ahci_host_priv *hpriv = ap->host->private_data;
233 return sprintf(buf, "%x\n", hpriv->cap);
236 static ssize_t ahci_show_host_cap2(struct device *dev,
237 struct device_attribute *attr, char *buf)
239 struct Scsi_Host *shost = class_to_shost(dev);
240 struct ata_port *ap = ata_shost_to_port(shost);
241 struct ahci_host_priv *hpriv = ap->host->private_data;
243 return sprintf(buf, "%x\n", hpriv->cap2);
246 static ssize_t ahci_show_host_version(struct device *dev,
247 struct device_attribute *attr, char *buf)
249 struct Scsi_Host *shost = class_to_shost(dev);
250 struct ata_port *ap = ata_shost_to_port(shost);
251 struct ahci_host_priv *hpriv = ap->host->private_data;
252 void __iomem *mmio = hpriv->mmio;
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
257 static ssize_t ahci_show_port_cmd(struct device *dev,
258 struct device_attribute *attr, char *buf)
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 void __iomem *port_mmio = ahci_port_base(ap);
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
267 static ssize_t ahci_read_em_buffer(struct device *dev,
268 struct device_attribute *attr, char *buf)
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273 void __iomem *mmio = hpriv->mmio;
274 void __iomem *em_mmio = mmio + hpriv->em_loc;
280 spin_lock_irqsave(ap->lock, flags);
282 em_ctl = readl(mmio + HOST_EM_CTL);
283 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
284 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
285 spin_unlock_irqrestore(ap->lock, flags);
289 if (!(em_ctl & EM_CTL_MR)) {
290 spin_unlock_irqrestore(ap->lock, flags);
294 if (!(em_ctl & EM_CTL_SMB))
295 em_mmio += hpriv->em_buf_sz;
297 count = hpriv->em_buf_sz;
299 /* the count should not be larger than PAGE_SIZE */
300 if (count > PAGE_SIZE) {
301 if (printk_ratelimit())
303 "EM read buffer size too large: "
304 "buffer size %u, page size %lu\n",
305 hpriv->em_buf_sz, PAGE_SIZE);
309 for (i = 0; i < count; i += 4) {
310 msg = readl(em_mmio + i);
312 buf[i + 1] = (msg >> 8) & 0xff;
313 buf[i + 2] = (msg >> 16) & 0xff;
314 buf[i + 3] = (msg >> 24) & 0xff;
317 spin_unlock_irqrestore(ap->lock, flags);
322 static ssize_t ahci_store_em_buffer(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf, size_t size)
326 struct Scsi_Host *shost = class_to_shost(dev);
327 struct ata_port *ap = ata_shost_to_port(shost);
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 void __iomem *mmio = hpriv->mmio;
330 void __iomem *em_mmio = mmio + hpriv->em_loc;
331 const unsigned char *msg_buf = buf;
336 /* check size validity */
337 if (!(ap->flags & ATA_FLAG_EM) ||
338 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
339 size % 4 || size > hpriv->em_buf_sz)
342 spin_lock_irqsave(ap->lock, flags);
344 em_ctl = readl(mmio + HOST_EM_CTL);
345 if (em_ctl & EM_CTL_TM) {
346 spin_unlock_irqrestore(ap->lock, flags);
350 for (i = 0; i < size; i += 4) {
351 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
352 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
353 writel(msg, em_mmio + i);
356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
358 spin_unlock_irqrestore(ap->lock, flags);
363 static ssize_t ahci_show_em_supported(struct device *dev,
364 struct device_attribute *attr, char *buf)
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
372 em_ctl = readl(mmio + HOST_EM_CTL);
374 return sprintf(buf, "%s%s%s%s\n",
375 em_ctl & EM_CTL_LED ? "led " : "",
376 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
377 em_ctl & EM_CTL_SES ? "ses-2 " : "",
378 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values
385 * @force_port_map: force port map to a specified value
386 * @mask_port_map: mask out particular bits from port map
388 * Some registers containing configuration info might be setup by
389 * BIOS and might be cleared on reset. This function saves the
390 * initial values of those registers into @hpriv such that they
391 * can be restored after controller reset.
393 * If inconsistent, config values are fixed up by this function.
395 * If it is not set already this function sets hpriv->start_engine to
401 void ahci_save_initial_config(struct device *dev,
402 struct ahci_host_priv *hpriv,
403 unsigned int force_port_map,
404 unsigned int mask_port_map)
406 void __iomem *mmio = hpriv->mmio;
407 u32 cap, cap2, vers, port_map;
410 /* make sure AHCI mode is enabled before accessing CAP */
411 ahci_enable_ahci(mmio);
413 /* Values prefixed with saved_ are written back to host after
414 * reset. Values without are used for driver operation.
416 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
417 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
419 /* CAP2 register is only defined for AHCI 1.2 and later */
420 vers = readl(mmio + HOST_VERSION);
421 if ((vers >> 16) > 1 ||
422 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
423 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
425 hpriv->saved_cap2 = cap2 = 0;
427 /* some chips have errata preventing 64bit use */
428 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
429 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
433 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
434 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
435 cap &= ~HOST_CAP_NCQ;
438 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
439 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
443 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
444 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
445 cap &= ~HOST_CAP_PMP;
448 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
450 "controller can't do SNTF, turning off CAP_SNTF\n");
451 cap &= ~HOST_CAP_SNTF;
454 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
456 "controller can't do DEVSLP, turning off\n");
457 cap2 &= ~HOST_CAP2_SDS;
458 cap2 &= ~HOST_CAP2_SADM;
461 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
462 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
466 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
467 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
468 cap &= ~HOST_CAP_FBS;
471 if (force_port_map && port_map != force_port_map) {
472 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
473 port_map, force_port_map);
474 port_map = force_port_map;
478 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
480 port_map & mask_port_map);
481 port_map &= mask_port_map;
484 /* cross check port_map and cap.n_ports */
488 for (i = 0; i < AHCI_MAX_PORTS; i++)
489 if (port_map & (1 << i))
492 /* If PI has more ports than n_ports, whine, clear
493 * port_map and let it be generated from n_ports.
495 if (map_ports > ahci_nr_ports(cap)) {
497 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
498 port_map, ahci_nr_ports(cap));
503 /* fabricate port_map from cap.nr_ports */
505 port_map = (1 << ahci_nr_ports(cap)) - 1;
506 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
508 /* write the fixed up value to the PI register */
509 hpriv->saved_port_map = port_map;
512 /* record values to use during operation */
515 hpriv->port_map = port_map;
517 if (!hpriv->start_engine)
518 hpriv->start_engine = ahci_start_engine;
520 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
523 * ahci_restore_initial_config - Restore initial config
524 * @host: target ATA host
526 * Restore initial config stored by ahci_save_initial_config().
531 static void ahci_restore_initial_config(struct ata_host *host)
533 struct ahci_host_priv *hpriv = host->private_data;
534 void __iomem *mmio = hpriv->mmio;
536 writel(hpriv->saved_cap, mmio + HOST_CAP);
537 if (hpriv->saved_cap2)
538 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
539 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
540 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
543 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
545 static const int offset[] = {
546 [SCR_STATUS] = PORT_SCR_STAT,
547 [SCR_CONTROL] = PORT_SCR_CTL,
548 [SCR_ERROR] = PORT_SCR_ERR,
549 [SCR_ACTIVE] = PORT_SCR_ACT,
550 [SCR_NOTIFICATION] = PORT_SCR_NTF,
552 struct ahci_host_priv *hpriv = ap->host->private_data;
554 if (sc_reg < ARRAY_SIZE(offset) &&
555 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
556 return offset[sc_reg];
560 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
562 void __iomem *port_mmio = ahci_port_base(link->ap);
563 int offset = ahci_scr_offset(link->ap, sc_reg);
566 *val = readl(port_mmio + offset);
572 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
574 void __iomem *port_mmio = ahci_port_base(link->ap);
575 int offset = ahci_scr_offset(link->ap, sc_reg);
578 writel(val, port_mmio + offset);
584 void ahci_start_engine(struct ata_port *ap)
586 void __iomem *port_mmio = ahci_port_base(ap);
590 tmp = readl(port_mmio + PORT_CMD);
591 tmp |= PORT_CMD_START;
592 writel(tmp, port_mmio + PORT_CMD);
593 readl(port_mmio + PORT_CMD); /* flush */
595 EXPORT_SYMBOL_GPL(ahci_start_engine);
597 int ahci_stop_engine(struct ata_port *ap)
599 void __iomem *port_mmio = ahci_port_base(ap);
602 tmp = readl(port_mmio + PORT_CMD);
604 /* check if the HBA is idle */
605 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
608 /* setting HBA to idle */
609 tmp &= ~PORT_CMD_START;
610 writel(tmp, port_mmio + PORT_CMD);
612 /* wait for engine to stop. This could be as long as 500 msec */
613 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
614 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
615 if (tmp & PORT_CMD_LIST_ON)
620 EXPORT_SYMBOL_GPL(ahci_stop_engine);
622 void ahci_start_fis_rx(struct ata_port *ap)
624 void __iomem *port_mmio = ahci_port_base(ap);
625 struct ahci_host_priv *hpriv = ap->host->private_data;
626 struct ahci_port_priv *pp = ap->private_data;
629 /* set FIS registers */
630 if (hpriv->cap & HOST_CAP_64)
631 writel((pp->cmd_slot_dma >> 16) >> 16,
632 port_mmio + PORT_LST_ADDR_HI);
633 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
635 if (hpriv->cap & HOST_CAP_64)
636 writel((pp->rx_fis_dma >> 16) >> 16,
637 port_mmio + PORT_FIS_ADDR_HI);
638 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
640 /* enable FIS reception */
641 tmp = readl(port_mmio + PORT_CMD);
642 tmp |= PORT_CMD_FIS_RX;
643 writel(tmp, port_mmio + PORT_CMD);
646 readl(port_mmio + PORT_CMD);
648 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
650 static int ahci_stop_fis_rx(struct ata_port *ap)
652 void __iomem *port_mmio = ahci_port_base(ap);
655 /* disable FIS reception */
656 tmp = readl(port_mmio + PORT_CMD);
657 tmp &= ~PORT_CMD_FIS_RX;
658 writel(tmp, port_mmio + PORT_CMD);
660 /* wait for completion, spec says 500ms, give it 1000 */
661 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
662 PORT_CMD_FIS_ON, 10, 1000);
663 if (tmp & PORT_CMD_FIS_ON)
669 static void ahci_power_up(struct ata_port *ap)
671 struct ahci_host_priv *hpriv = ap->host->private_data;
672 void __iomem *port_mmio = ahci_port_base(ap);
675 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
678 if (hpriv->cap & HOST_CAP_SSS) {
679 cmd |= PORT_CMD_SPIN_UP;
680 writel(cmd, port_mmio + PORT_CMD);
684 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
687 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
690 struct ata_port *ap = link->ap;
691 struct ahci_host_priv *hpriv = ap->host->private_data;
692 struct ahci_port_priv *pp = ap->private_data;
693 void __iomem *port_mmio = ahci_port_base(ap);
695 if (policy != ATA_LPM_MAX_POWER) {
697 * Disable interrupts on Phy Ready. This keeps us from
698 * getting woken up due to spurious phy ready
701 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
702 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
704 sata_link_scr_lpm(link, policy, false);
707 if (hpriv->cap & HOST_CAP_ALPM) {
708 u32 cmd = readl(port_mmio + PORT_CMD);
710 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
711 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
712 cmd |= PORT_CMD_ICC_ACTIVE;
714 writel(cmd, port_mmio + PORT_CMD);
715 readl(port_mmio + PORT_CMD);
717 /* wait 10ms to be sure we've come out of LPM state */
720 cmd |= PORT_CMD_ALPE;
721 if (policy == ATA_LPM_MIN_POWER)
724 /* write out new cmd value */
725 writel(cmd, port_mmio + PORT_CMD);
729 /* set aggressive device sleep */
730 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
731 (hpriv->cap2 & HOST_CAP2_SADM) &&
732 (link->device->flags & ATA_DFLAG_DEVSLP)) {
733 if (policy == ATA_LPM_MIN_POWER)
734 ahci_set_aggressive_devslp(ap, true);
736 ahci_set_aggressive_devslp(ap, false);
739 if (policy == ATA_LPM_MAX_POWER) {
740 sata_link_scr_lpm(link, policy, false);
742 /* turn PHYRDY IRQ back on */
743 pp->intr_mask |= PORT_IRQ_PHYRDY;
744 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
751 static void ahci_power_down(struct ata_port *ap)
753 struct ahci_host_priv *hpriv = ap->host->private_data;
754 void __iomem *port_mmio = ahci_port_base(ap);
757 if (!(hpriv->cap & HOST_CAP_SSS))
760 /* put device into listen mode, first set PxSCTL.DET to 0 */
761 scontrol = readl(port_mmio + PORT_SCR_CTL);
763 writel(scontrol, port_mmio + PORT_SCR_CTL);
765 /* then set PxCMD.SUD to 0 */
766 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
767 cmd &= ~PORT_CMD_SPIN_UP;
768 writel(cmd, port_mmio + PORT_CMD);
772 static void ahci_start_port(struct ata_port *ap)
774 struct ahci_host_priv *hpriv = ap->host->private_data;
775 struct ahci_port_priv *pp = ap->private_data;
776 struct ata_link *link;
777 struct ahci_em_priv *emp;
781 /* enable FIS reception */
782 ahci_start_fis_rx(ap);
785 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
786 hpriv->start_engine(ap);
789 if (ap->flags & ATA_FLAG_EM) {
790 ata_for_each_link(link, ap, EDGE) {
791 emp = &pp->em_priv[link->pmp];
793 /* EM Transmit bit maybe busy during init */
794 for (i = 0; i < EM_MAX_RETRY; i++) {
795 rc = ap->ops->transmit_led_message(ap,
799 * If busy, give a breather but do not
800 * release EH ownership by using msleep()
801 * instead of ata_msleep(). EM Transmit
802 * bit is busy for the whole host and
803 * releasing ownership will cause other
804 * ports to fail the same way.
814 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
815 ata_for_each_link(link, ap, EDGE)
816 ahci_init_sw_activity(link);
820 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
825 rc = ahci_stop_engine(ap);
827 *emsg = "failed to stop engine";
831 /* disable FIS reception */
832 rc = ahci_stop_fis_rx(ap);
834 *emsg = "failed stop FIS RX";
841 int ahci_reset_controller(struct ata_host *host)
843 struct ahci_host_priv *hpriv = host->private_data;
844 void __iomem *mmio = hpriv->mmio;
847 /* we must be in AHCI mode, before using anything
848 * AHCI-specific, such as HOST_RESET.
850 ahci_enable_ahci(mmio);
852 /* global controller reset */
853 if (!ahci_skip_host_reset) {
854 tmp = readl(mmio + HOST_CTL);
855 if ((tmp & HOST_RESET) == 0) {
856 writel(tmp | HOST_RESET, mmio + HOST_CTL);
857 readl(mmio + HOST_CTL); /* flush */
861 * to perform host reset, OS should set HOST_RESET
862 * and poll until this bit is read to be "0".
863 * reset must complete within 1 second, or
864 * the hardware should be considered fried.
866 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
867 HOST_RESET, 10, 1000);
869 if (tmp & HOST_RESET) {
870 dev_err(host->dev, "controller reset failed (0x%x)\n",
875 /* turn on AHCI mode */
876 ahci_enable_ahci(mmio);
878 /* Some registers might be cleared on reset. Restore
881 ahci_restore_initial_config(host);
883 dev_info(host->dev, "skipping global host reset\n");
887 EXPORT_SYMBOL_GPL(ahci_reset_controller);
889 static void ahci_sw_activity(struct ata_link *link)
891 struct ata_port *ap = link->ap;
892 struct ahci_port_priv *pp = ap->private_data;
893 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
895 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
899 if (!timer_pending(&emp->timer))
900 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
903 static void ahci_sw_activity_blink(unsigned long arg)
905 struct ata_link *link = (struct ata_link *)arg;
906 struct ata_port *ap = link->ap;
907 struct ahci_port_priv *pp = ap->private_data;
908 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
909 unsigned long led_message = emp->led_state;
910 u32 activity_led_state;
913 led_message &= EM_MSG_LED_VALUE;
914 led_message |= ap->port_no | (link->pmp << 8);
916 /* check to see if we've had activity. If so,
917 * toggle state of LED and reset timer. If not,
918 * turn LED to desired idle state.
920 spin_lock_irqsave(ap->lock, flags);
921 if (emp->saved_activity != emp->activity) {
922 emp->saved_activity = emp->activity;
923 /* get the current LED state */
924 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
926 if (activity_led_state)
927 activity_led_state = 0;
929 activity_led_state = 1;
931 /* clear old state */
932 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
935 led_message |= (activity_led_state << 16);
936 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
939 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
940 if (emp->blink_policy == BLINK_OFF)
941 led_message |= (1 << 16);
943 spin_unlock_irqrestore(ap->lock, flags);
944 ap->ops->transmit_led_message(ap, led_message, 4);
947 static void ahci_init_sw_activity(struct ata_link *link)
949 struct ata_port *ap = link->ap;
950 struct ahci_port_priv *pp = ap->private_data;
951 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
953 /* init activity stats, setup timer */
954 emp->saved_activity = emp->activity = 0;
955 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
957 /* check our blink policy and set flag for link if it's enabled */
958 if (emp->blink_policy)
959 link->flags |= ATA_LFLAG_SW_ACTIVITY;
962 int ahci_reset_em(struct ata_host *host)
964 struct ahci_host_priv *hpriv = host->private_data;
965 void __iomem *mmio = hpriv->mmio;
968 em_ctl = readl(mmio + HOST_EM_CTL);
969 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
972 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
975 EXPORT_SYMBOL_GPL(ahci_reset_em);
977 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
980 struct ahci_host_priv *hpriv = ap->host->private_data;
981 struct ahci_port_priv *pp = ap->private_data;
982 void __iomem *mmio = hpriv->mmio;
984 u32 message[] = {0, 0};
987 struct ahci_em_priv *emp;
989 /* get the slot number from the message */
990 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
991 if (pmp < EM_MAX_SLOTS)
992 emp = &pp->em_priv[pmp];
996 spin_lock_irqsave(ap->lock, flags);
999 * if we are still busy transmitting a previous message,
1002 em_ctl = readl(mmio + HOST_EM_CTL);
1003 if (em_ctl & EM_CTL_TM) {
1004 spin_unlock_irqrestore(ap->lock, flags);
1008 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1010 * create message header - this is all zero except for
1011 * the message size, which is 4 bytes.
1013 message[0] |= (4 << 8);
1015 /* ignore 0:4 of byte zero, fill in port info yourself */
1016 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1018 /* write message to EM_LOC */
1019 writel(message[0], mmio + hpriv->em_loc);
1020 writel(message[1], mmio + hpriv->em_loc+4);
1023 * tell hardware to transmit the message
1025 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1028 /* save off new led state for port/slot */
1029 emp->led_state = state;
1031 spin_unlock_irqrestore(ap->lock, flags);
1035 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1037 struct ahci_port_priv *pp = ap->private_data;
1038 struct ata_link *link;
1039 struct ahci_em_priv *emp;
1042 ata_for_each_link(link, ap, EDGE) {
1043 emp = &pp->em_priv[link->pmp];
1044 rc += sprintf(buf, "%lx\n", emp->led_state);
1049 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1054 struct ahci_port_priv *pp = ap->private_data;
1055 struct ahci_em_priv *emp;
1057 if (kstrtouint(buf, 0, &state) < 0)
1060 /* get the slot number from the message */
1061 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1062 if (pmp < EM_MAX_SLOTS)
1063 emp = &pp->em_priv[pmp];
1067 /* mask off the activity bits if we are in sw_activity
1068 * mode, user should turn off sw_activity before setting
1069 * activity led through em_message
1071 if (emp->blink_policy)
1072 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1074 return ap->ops->transmit_led_message(ap, state, size);
1077 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1079 struct ata_link *link = dev->link;
1080 struct ata_port *ap = link->ap;
1081 struct ahci_port_priv *pp = ap->private_data;
1082 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1083 u32 port_led_state = emp->led_state;
1085 /* save the desired Activity LED behavior */
1088 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1090 /* set the LED to OFF */
1091 port_led_state &= EM_MSG_LED_VALUE_OFF;
1092 port_led_state |= (ap->port_no | (link->pmp << 8));
1093 ap->ops->transmit_led_message(ap, port_led_state, 4);
1095 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1096 if (val == BLINK_OFF) {
1097 /* set LED to ON for idle */
1098 port_led_state &= EM_MSG_LED_VALUE_OFF;
1099 port_led_state |= (ap->port_no | (link->pmp << 8));
1100 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1101 ap->ops->transmit_led_message(ap, port_led_state, 4);
1104 emp->blink_policy = val;
1108 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1110 struct ata_link *link = dev->link;
1111 struct ata_port *ap = link->ap;
1112 struct ahci_port_priv *pp = ap->private_data;
1113 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1115 /* display the saved value of activity behavior for this
1118 return sprintf(buf, "%d\n", emp->blink_policy);
1121 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1122 int port_no, void __iomem *mmio,
1123 void __iomem *port_mmio)
1125 const char *emsg = NULL;
1129 /* make sure port is not active */
1130 rc = ahci_deinit_port(ap, &emsg);
1132 dev_warn(dev, "%s (%d)\n", emsg, rc);
1135 tmp = readl(port_mmio + PORT_SCR_ERR);
1136 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1137 writel(tmp, port_mmio + PORT_SCR_ERR);
1139 /* clear port IRQ */
1140 tmp = readl(port_mmio + PORT_IRQ_STAT);
1141 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1143 writel(tmp, port_mmio + PORT_IRQ_STAT);
1145 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1148 void ahci_init_controller(struct ata_host *host)
1150 struct ahci_host_priv *hpriv = host->private_data;
1151 void __iomem *mmio = hpriv->mmio;
1153 void __iomem *port_mmio;
1156 for (i = 0; i < host->n_ports; i++) {
1157 struct ata_port *ap = host->ports[i];
1159 port_mmio = ahci_port_base(ap);
1160 if (ata_port_is_dummy(ap))
1163 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1166 tmp = readl(mmio + HOST_CTL);
1167 VPRINTK("HOST_CTL 0x%x\n", tmp);
1168 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1169 tmp = readl(mmio + HOST_CTL);
1170 VPRINTK("HOST_CTL 0x%x\n", tmp);
1172 EXPORT_SYMBOL_GPL(ahci_init_controller);
1174 static void ahci_dev_config(struct ata_device *dev)
1176 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1178 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1179 dev->max_sectors = 255;
1181 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1185 unsigned int ahci_dev_classify(struct ata_port *ap)
1187 void __iomem *port_mmio = ahci_port_base(ap);
1188 struct ata_taskfile tf;
1191 tmp = readl(port_mmio + PORT_SIG);
1192 tf.lbah = (tmp >> 24) & 0xff;
1193 tf.lbam = (tmp >> 16) & 0xff;
1194 tf.lbal = (tmp >> 8) & 0xff;
1195 tf.nsect = (tmp) & 0xff;
1197 return ata_dev_classify(&tf);
1199 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1201 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1204 dma_addr_t cmd_tbl_dma;
1206 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1208 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1209 pp->cmd_slot[tag].status = 0;
1210 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1211 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1213 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1215 int ahci_kick_engine(struct ata_port *ap)
1217 void __iomem *port_mmio = ahci_port_base(ap);
1218 struct ahci_host_priv *hpriv = ap->host->private_data;
1219 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1224 rc = ahci_stop_engine(ap);
1229 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1231 busy = status & (ATA_BUSY | ATA_DRQ);
1232 if (!busy && !sata_pmp_attached(ap)) {
1237 if (!(hpriv->cap & HOST_CAP_CLO)) {
1243 tmp = readl(port_mmio + PORT_CMD);
1244 tmp |= PORT_CMD_CLO;
1245 writel(tmp, port_mmio + PORT_CMD);
1248 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1249 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1250 if (tmp & PORT_CMD_CLO)
1253 /* restart engine */
1255 hpriv->start_engine(ap);
1258 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1260 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1261 struct ata_taskfile *tf, int is_cmd, u16 flags,
1262 unsigned long timeout_msec)
1264 const u32 cmd_fis_len = 5; /* five dwords */
1265 struct ahci_port_priv *pp = ap->private_data;
1266 void __iomem *port_mmio = ahci_port_base(ap);
1267 u8 *fis = pp->cmd_tbl;
1270 /* prep the command */
1271 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1272 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1275 writel(1, port_mmio + PORT_CMD_ISSUE);
1278 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1279 0x1, 0x1, 1, timeout_msec);
1281 ahci_kick_engine(ap);
1285 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1290 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1291 int pmp, unsigned long deadline,
1292 int (*check_ready)(struct ata_link *link))
1294 struct ata_port *ap = link->ap;
1295 struct ahci_host_priv *hpriv = ap->host->private_data;
1296 struct ahci_port_priv *pp = ap->private_data;
1297 const char *reason = NULL;
1298 unsigned long now, msecs;
1299 struct ata_taskfile tf;
1300 bool fbs_disabled = false;
1305 /* prepare for SRST (AHCI-1.1 10.4.1) */
1306 rc = ahci_kick_engine(ap);
1307 if (rc && rc != -EOPNOTSUPP)
1308 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1311 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1312 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1313 * that is attached to port multiplier.
1315 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1316 ahci_disable_fbs(ap);
1317 fbs_disabled = true;
1320 ata_tf_init(link->device, &tf);
1322 /* issue the first D2H Register FIS */
1325 if (time_after(deadline, now))
1326 msecs = jiffies_to_msecs(deadline - now);
1329 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1330 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1332 reason = "1st FIS failed";
1336 /* spec says at least 5us, but be generous and sleep for 1ms */
1339 /* issue the second D2H Register FIS */
1340 tf.ctl &= ~ATA_SRST;
1341 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1343 /* wait for link to become ready */
1344 rc = ata_wait_after_reset(link, deadline, check_ready);
1345 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1347 * Workaround for cases where link online status can't
1348 * be trusted. Treat device readiness timeout as link
1351 ata_link_info(link, "device not ready, treating as offline\n");
1352 *class = ATA_DEV_NONE;
1354 /* link occupied, -ENODEV too is an error */
1355 reason = "device not ready";
1358 *class = ahci_dev_classify(ap);
1360 /* re-enable FBS if disabled before */
1362 ahci_enable_fbs(ap);
1364 DPRINTK("EXIT, class=%u\n", *class);
1368 ata_link_err(link, "softreset failed (%s)\n", reason);
1372 int ahci_check_ready(struct ata_link *link)
1374 void __iomem *port_mmio = ahci_port_base(link->ap);
1375 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1377 return ata_check_ready(status);
1379 EXPORT_SYMBOL_GPL(ahci_check_ready);
1381 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1382 unsigned long deadline)
1384 int pmp = sata_srst_pmp(link);
1388 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1390 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1392 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1394 void __iomem *port_mmio = ahci_port_base(link->ap);
1395 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1396 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1399 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1400 * which can save timeout delay.
1402 if (irq_status & PORT_IRQ_BAD_PMP)
1405 return ata_check_ready(status);
1408 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1409 unsigned long deadline)
1411 struct ata_port *ap = link->ap;
1412 void __iomem *port_mmio = ahci_port_base(ap);
1413 int pmp = sata_srst_pmp(link);
1419 rc = ahci_do_softreset(link, class, pmp, deadline,
1420 ahci_bad_pmp_check_ready);
1423 * Soft reset fails with IPMS set when PMP is enabled but
1424 * SATA HDD/ODD is connected to SATA port, do soft reset
1428 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1429 if (irq_sts & PORT_IRQ_BAD_PMP) {
1431 "applying PMP SRST workaround "
1433 rc = ahci_do_softreset(link, class, 0, deadline,
1441 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1442 unsigned long deadline)
1444 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1445 struct ata_port *ap = link->ap;
1446 struct ahci_port_priv *pp = ap->private_data;
1447 struct ahci_host_priv *hpriv = ap->host->private_data;
1448 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1449 struct ata_taskfile tf;
1455 ahci_stop_engine(ap);
1457 /* clear D2H reception area to properly wait for D2H FIS */
1458 ata_tf_init(link->device, &tf);
1459 tf.command = ATA_BUSY;
1460 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1462 rc = sata_link_hardreset(link, timing, deadline, &online,
1465 hpriv->start_engine(ap);
1468 *class = ahci_dev_classify(ap);
1470 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1474 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1476 struct ata_port *ap = link->ap;
1477 void __iomem *port_mmio = ahci_port_base(ap);
1480 ata_std_postreset(link, class);
1482 /* Make sure port's ATAPI bit is set appropriately */
1483 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1484 if (*class == ATA_DEV_ATAPI)
1485 new_tmp |= PORT_CMD_ATAPI;
1487 new_tmp &= ~PORT_CMD_ATAPI;
1488 if (new_tmp != tmp) {
1489 writel(new_tmp, port_mmio + PORT_CMD);
1490 readl(port_mmio + PORT_CMD); /* flush */
1494 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1496 struct scatterlist *sg;
1497 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1503 * Next, the S/G list.
1505 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1506 dma_addr_t addr = sg_dma_address(sg);
1507 u32 sg_len = sg_dma_len(sg);
1509 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1510 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1511 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1517 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1519 struct ata_port *ap = qc->ap;
1520 struct ahci_port_priv *pp = ap->private_data;
1522 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1523 return ata_std_qc_defer(qc);
1525 return sata_pmp_qc_defer_cmd_switch(qc);
1528 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1530 struct ata_port *ap = qc->ap;
1531 struct ahci_port_priv *pp = ap->private_data;
1532 int is_atapi = ata_is_atapi(qc->tf.protocol);
1535 const u32 cmd_fis_len = 5; /* five dwords */
1536 unsigned int n_elem;
1539 * Fill in command table information. First, the header,
1540 * a SATA Register - Host to Device command FIS.
1542 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1544 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1546 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1547 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1551 if (qc->flags & ATA_QCFLAG_DMAMAP)
1552 n_elem = ahci_fill_sg(qc, cmd_tbl);
1555 * Fill in command slot information.
1557 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1558 if (qc->tf.flags & ATA_TFLAG_WRITE)
1559 opts |= AHCI_CMD_WRITE;
1561 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1563 ahci_fill_cmd_slot(pp, qc->tag, opts);
1566 static void ahci_fbs_dec_intr(struct ata_port *ap)
1568 struct ahci_port_priv *pp = ap->private_data;
1569 void __iomem *port_mmio = ahci_port_base(ap);
1570 u32 fbs = readl(port_mmio + PORT_FBS);
1574 BUG_ON(!pp->fbs_enabled);
1576 /* time to wait for DEC is not specified by AHCI spec,
1577 * add a retry loop for safety.
1579 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1580 fbs = readl(port_mmio + PORT_FBS);
1581 while ((fbs & PORT_FBS_DEC) && retries--) {
1583 fbs = readl(port_mmio + PORT_FBS);
1586 if (fbs & PORT_FBS_DEC)
1587 dev_err(ap->host->dev, "failed to clear device error\n");
1590 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1592 struct ahci_host_priv *hpriv = ap->host->private_data;
1593 struct ahci_port_priv *pp = ap->private_data;
1594 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1595 struct ata_link *link = NULL;
1596 struct ata_queued_cmd *active_qc;
1597 struct ata_eh_info *active_ehi;
1598 bool fbs_need_dec = false;
1601 /* determine active link with error */
1602 if (pp->fbs_enabled) {
1603 void __iomem *port_mmio = ahci_port_base(ap);
1604 u32 fbs = readl(port_mmio + PORT_FBS);
1605 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1607 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1608 link = &ap->pmp_link[pmp];
1609 fbs_need_dec = true;
1613 ata_for_each_link(link, ap, EDGE)
1614 if (ata_link_active(link))
1620 active_qc = ata_qc_from_tag(ap, link->active_tag);
1621 active_ehi = &link->eh_info;
1623 /* record irq stat */
1624 ata_ehi_clear_desc(host_ehi);
1625 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1627 /* AHCI needs SError cleared; otherwise, it might lock up */
1628 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1629 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1630 host_ehi->serror |= serror;
1632 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1633 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1634 irq_stat &= ~PORT_IRQ_IF_ERR;
1636 if (irq_stat & PORT_IRQ_TF_ERR) {
1637 /* If qc is active, charge it; otherwise, the active
1638 * link. There's no active qc on NCQ errors. It will
1639 * be determined by EH by reading log page 10h.
1642 active_qc->err_mask |= AC_ERR_DEV;
1644 active_ehi->err_mask |= AC_ERR_DEV;
1646 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1647 host_ehi->serror &= ~SERR_INTERNAL;
1650 if (irq_stat & PORT_IRQ_UNK_FIS) {
1651 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1653 active_ehi->err_mask |= AC_ERR_HSM;
1654 active_ehi->action |= ATA_EH_RESET;
1655 ata_ehi_push_desc(active_ehi,
1656 "unknown FIS %08x %08x %08x %08x" ,
1657 unk[0], unk[1], unk[2], unk[3]);
1660 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1661 active_ehi->err_mask |= AC_ERR_HSM;
1662 active_ehi->action |= ATA_EH_RESET;
1663 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1666 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1667 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1668 host_ehi->action |= ATA_EH_RESET;
1669 ata_ehi_push_desc(host_ehi, "host bus error");
1672 if (irq_stat & PORT_IRQ_IF_ERR) {
1674 active_ehi->err_mask |= AC_ERR_DEV;
1676 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1677 host_ehi->action |= ATA_EH_RESET;
1680 ata_ehi_push_desc(host_ehi, "interface fatal error");
1683 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1684 ata_ehi_hotplugged(host_ehi);
1685 ata_ehi_push_desc(host_ehi, "%s",
1686 irq_stat & PORT_IRQ_CONNECT ?
1687 "connection status changed" : "PHY RDY changed");
1690 /* okay, let's hand over to EH */
1692 if (irq_stat & PORT_IRQ_FREEZE)
1693 ata_port_freeze(ap);
1694 else if (fbs_need_dec) {
1695 ata_link_abort(link);
1696 ahci_fbs_dec_intr(ap);
1701 static void ahci_handle_port_interrupt(struct ata_port *ap,
1702 void __iomem *port_mmio, u32 status)
1704 struct ata_eh_info *ehi = &ap->link.eh_info;
1705 struct ahci_port_priv *pp = ap->private_data;
1706 struct ahci_host_priv *hpriv = ap->host->private_data;
1707 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1711 /* ignore BAD_PMP while resetting */
1712 if (unlikely(resetting))
1713 status &= ~PORT_IRQ_BAD_PMP;
1715 /* if LPM is enabled, PHYRDY doesn't mean anything */
1716 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
1717 status &= ~PORT_IRQ_PHYRDY;
1718 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1721 if (unlikely(status & PORT_IRQ_ERROR)) {
1722 ahci_error_intr(ap, status);
1726 if (status & PORT_IRQ_SDB_FIS) {
1727 /* If SNotification is available, leave notification
1728 * handling to sata_async_notification(). If not,
1729 * emulate it by snooping SDB FIS RX area.
1731 * Snooping FIS RX area is probably cheaper than
1732 * poking SNotification but some constrollers which
1733 * implement SNotification, ICH9 for example, don't
1734 * store AN SDB FIS into receive area.
1736 if (hpriv->cap & HOST_CAP_SNTF)
1737 sata_async_notification(ap);
1739 /* If the 'N' bit in word 0 of the FIS is set,
1740 * we just received asynchronous notification.
1741 * Tell libata about it.
1743 * Lack of SNotification should not appear in
1744 * ahci 1.2, so the workaround is unnecessary
1745 * when FBS is enabled.
1747 if (pp->fbs_enabled)
1750 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1751 u32 f0 = le32_to_cpu(f[0]);
1753 sata_async_notification(ap);
1758 /* pp->active_link is not reliable once FBS is enabled, both
1759 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1760 * NCQ and non-NCQ commands may be in flight at the same time.
1762 if (pp->fbs_enabled) {
1763 if (ap->qc_active) {
1764 qc_active = readl(port_mmio + PORT_SCR_ACT);
1765 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1768 /* pp->active_link is valid iff any command is in flight */
1769 if (ap->qc_active && pp->active_link->sactive)
1770 qc_active = readl(port_mmio + PORT_SCR_ACT);
1772 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1776 rc = ata_qc_complete_multiple(ap, qc_active);
1778 /* while resetting, invalid completions are expected */
1779 if (unlikely(rc < 0 && !resetting)) {
1780 ehi->err_mask |= AC_ERR_HSM;
1781 ehi->action |= ATA_EH_RESET;
1782 ata_port_freeze(ap);
1786 static void ahci_port_intr(struct ata_port *ap)
1788 void __iomem *port_mmio = ahci_port_base(ap);
1791 status = readl(port_mmio + PORT_IRQ_STAT);
1792 writel(status, port_mmio + PORT_IRQ_STAT);
1794 ahci_handle_port_interrupt(ap, port_mmio, status);
1797 irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1799 struct ata_port *ap = dev_instance;
1800 struct ahci_port_priv *pp = ap->private_data;
1801 void __iomem *port_mmio = ahci_port_base(ap);
1802 unsigned long flags;
1805 spin_lock_irqsave(&ap->host->lock, flags);
1806 status = pp->intr_status;
1808 pp->intr_status = 0;
1809 spin_unlock_irqrestore(&ap->host->lock, flags);
1811 spin_lock_bh(ap->lock);
1812 ahci_handle_port_interrupt(ap, port_mmio, status);
1813 spin_unlock_bh(ap->lock);
1817 EXPORT_SYMBOL_GPL(ahci_thread_fn);
1819 static void ahci_hw_port_interrupt(struct ata_port *ap)
1821 void __iomem *port_mmio = ahci_port_base(ap);
1822 struct ahci_port_priv *pp = ap->private_data;
1825 status = readl(port_mmio + PORT_IRQ_STAT);
1826 writel(status, port_mmio + PORT_IRQ_STAT);
1828 pp->intr_status |= status;
1831 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1833 struct ata_port *ap_this = dev_instance;
1834 struct ahci_port_priv *pp = ap_this->private_data;
1835 struct ata_host *host = ap_this->host;
1836 struct ahci_host_priv *hpriv = host->private_data;
1837 void __iomem *mmio = hpriv->mmio;
1839 u32 irq_stat, irq_masked;
1843 spin_lock(&host->lock);
1845 irq_stat = readl(mmio + HOST_IRQ_STAT);
1848 u32 status = pp->intr_status;
1850 spin_unlock(&host->lock);
1854 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1857 irq_masked = irq_stat & hpriv->port_map;
1859 for (i = 0; i < host->n_ports; i++) {
1860 struct ata_port *ap;
1862 if (!(irq_masked & (1 << i)))
1865 ap = host->ports[i];
1867 ahci_hw_port_interrupt(ap);
1868 VPRINTK("port %u\n", i);
1870 VPRINTK("port %u (no irq)\n", i);
1871 if (ata_ratelimit())
1873 "interrupt on disabled port %u\n", i);
1877 writel(irq_stat, mmio + HOST_IRQ_STAT);
1879 spin_unlock(&host->lock);
1883 return IRQ_WAKE_THREAD;
1885 EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1887 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1889 struct ata_host *host = dev_instance;
1890 struct ahci_host_priv *hpriv;
1891 unsigned int i, handled = 0;
1893 u32 irq_stat, irq_masked;
1897 hpriv = host->private_data;
1900 /* sigh. 0xffffffff is a valid return from h/w */
1901 irq_stat = readl(mmio + HOST_IRQ_STAT);
1905 irq_masked = irq_stat & hpriv->port_map;
1907 spin_lock(&host->lock);
1909 for (i = 0; i < host->n_ports; i++) {
1910 struct ata_port *ap;
1912 if (!(irq_masked & (1 << i)))
1915 ap = host->ports[i];
1918 VPRINTK("port %u\n", i);
1920 VPRINTK("port %u (no irq)\n", i);
1921 if (ata_ratelimit())
1923 "interrupt on disabled port %u\n", i);
1929 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1930 * it should be cleared after all the port events are cleared;
1931 * otherwise, it will raise a spurious interrupt after each
1932 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1935 * Also, use the unmasked value to clear interrupt as spurious
1936 * pending event on a dummy port might cause screaming IRQ.
1938 writel(irq_stat, mmio + HOST_IRQ_STAT);
1940 spin_unlock(&host->lock);
1944 return IRQ_RETVAL(handled);
1946 EXPORT_SYMBOL_GPL(ahci_interrupt);
1948 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1950 struct ata_port *ap = qc->ap;
1951 void __iomem *port_mmio = ahci_port_base(ap);
1952 struct ahci_port_priv *pp = ap->private_data;
1954 /* Keep track of the currently active link. It will be used
1955 * in completion path to determine whether NCQ phase is in
1958 pp->active_link = qc->dev->link;
1960 if (qc->tf.protocol == ATA_PROT_NCQ)
1961 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1963 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1964 u32 fbs = readl(port_mmio + PORT_FBS);
1965 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1966 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1967 writel(fbs, port_mmio + PORT_FBS);
1968 pp->fbs_last_dev = qc->dev->link->pmp;
1971 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1973 ahci_sw_activity(qc->dev->link);
1977 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1979 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1981 struct ahci_port_priv *pp = qc->ap->private_data;
1982 u8 *rx_fis = pp->rx_fis;
1984 if (pp->fbs_enabled)
1985 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1988 * After a successful execution of an ATA PIO data-in command,
1989 * the device doesn't send D2H Reg FIS to update the TF and
1990 * the host should take TF and E_Status from the preceding PIO
1993 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1994 !(qc->flags & ATA_QCFLAG_FAILED)) {
1995 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1996 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1998 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2003 static void ahci_freeze(struct ata_port *ap)
2005 void __iomem *port_mmio = ahci_port_base(ap);
2008 writel(0, port_mmio + PORT_IRQ_MASK);
2011 static void ahci_thaw(struct ata_port *ap)
2013 struct ahci_host_priv *hpriv = ap->host->private_data;
2014 void __iomem *mmio = hpriv->mmio;
2015 void __iomem *port_mmio = ahci_port_base(ap);
2017 struct ahci_port_priv *pp = ap->private_data;
2020 tmp = readl(port_mmio + PORT_IRQ_STAT);
2021 writel(tmp, port_mmio + PORT_IRQ_STAT);
2022 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2024 /* turn IRQ back on */
2025 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2028 void ahci_error_handler(struct ata_port *ap)
2030 struct ahci_host_priv *hpriv = ap->host->private_data;
2032 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2033 /* restart engine */
2034 ahci_stop_engine(ap);
2035 hpriv->start_engine(ap);
2038 sata_pmp_error_handler(ap);
2040 if (!ata_dev_enabled(ap->link.device))
2041 ahci_stop_engine(ap);
2043 EXPORT_SYMBOL_GPL(ahci_error_handler);
2045 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2047 struct ata_port *ap = qc->ap;
2049 /* make DMA engine forget about the failed command */
2050 if (qc->flags & ATA_QCFLAG_FAILED)
2051 ahci_kick_engine(ap);
2054 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2056 struct ahci_host_priv *hpriv = ap->host->private_data;
2057 void __iomem *port_mmio = ahci_port_base(ap);
2058 struct ata_device *dev = ap->link.device;
2059 u32 devslp, dm, dito, mdat, deto;
2061 unsigned int err_mask;
2063 devslp = readl(port_mmio + PORT_DEVSLP);
2064 if (!(devslp & PORT_DEVSLP_DSP)) {
2065 dev_err(ap->host->dev, "port does not support device sleep\n");
2069 /* disable device sleep */
2071 if (devslp & PORT_DEVSLP_ADSE) {
2072 writel(devslp & ~PORT_DEVSLP_ADSE,
2073 port_mmio + PORT_DEVSLP);
2074 err_mask = ata_dev_set_feature(dev,
2075 SETFEATURES_SATA_DISABLE,
2077 if (err_mask && err_mask != AC_ERR_DEV)
2078 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2083 /* device sleep was already enabled */
2084 if (devslp & PORT_DEVSLP_ADSE)
2087 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2088 rc = ahci_stop_engine(ap);
2092 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2093 dito = devslp_idle_timeout / (dm + 1);
2097 /* Use the nominal value 10 ms if the read MDAT is zero,
2098 * the nominal value of DETO is 20 ms.
2100 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2101 ATA_LOG_DEVSLP_VALID_MASK) {
2102 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2103 ATA_LOG_DEVSLP_MDAT_MASK;
2106 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2114 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2115 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2116 (deto << PORT_DEVSLP_DETO_OFFSET) |
2118 writel(devslp, port_mmio + PORT_DEVSLP);
2120 hpriv->start_engine(ap);
2122 /* enable device sleep feature for the drive */
2123 err_mask = ata_dev_set_feature(dev,
2124 SETFEATURES_SATA_ENABLE,
2126 if (err_mask && err_mask != AC_ERR_DEV)
2127 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2130 static void ahci_enable_fbs(struct ata_port *ap)
2132 struct ahci_host_priv *hpriv = ap->host->private_data;
2133 struct ahci_port_priv *pp = ap->private_data;
2134 void __iomem *port_mmio = ahci_port_base(ap);
2138 if (!pp->fbs_supported)
2141 fbs = readl(port_mmio + PORT_FBS);
2142 if (fbs & PORT_FBS_EN) {
2143 pp->fbs_enabled = true;
2144 pp->fbs_last_dev = -1; /* initialization */
2148 rc = ahci_stop_engine(ap);
2152 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2153 fbs = readl(port_mmio + PORT_FBS);
2154 if (fbs & PORT_FBS_EN) {
2155 dev_info(ap->host->dev, "FBS is enabled\n");
2156 pp->fbs_enabled = true;
2157 pp->fbs_last_dev = -1; /* initialization */
2159 dev_err(ap->host->dev, "Failed to enable FBS\n");
2161 hpriv->start_engine(ap);
2164 static void ahci_disable_fbs(struct ata_port *ap)
2166 struct ahci_host_priv *hpriv = ap->host->private_data;
2167 struct ahci_port_priv *pp = ap->private_data;
2168 void __iomem *port_mmio = ahci_port_base(ap);
2172 if (!pp->fbs_supported)
2175 fbs = readl(port_mmio + PORT_FBS);
2176 if ((fbs & PORT_FBS_EN) == 0) {
2177 pp->fbs_enabled = false;
2181 rc = ahci_stop_engine(ap);
2185 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2186 fbs = readl(port_mmio + PORT_FBS);
2187 if (fbs & PORT_FBS_EN)
2188 dev_err(ap->host->dev, "Failed to disable FBS\n");
2190 dev_info(ap->host->dev, "FBS is disabled\n");
2191 pp->fbs_enabled = false;
2194 hpriv->start_engine(ap);
2197 static void ahci_pmp_attach(struct ata_port *ap)
2199 void __iomem *port_mmio = ahci_port_base(ap);
2200 struct ahci_port_priv *pp = ap->private_data;
2203 cmd = readl(port_mmio + PORT_CMD);
2204 cmd |= PORT_CMD_PMP;
2205 writel(cmd, port_mmio + PORT_CMD);
2207 ahci_enable_fbs(ap);
2209 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2212 * We must not change the port interrupt mask register if the
2213 * port is marked frozen, the value in pp->intr_mask will be
2214 * restored later when the port is thawed.
2216 * Note that during initialization, the port is marked as
2217 * frozen since the irq handler is not yet registered.
2219 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2220 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2223 static void ahci_pmp_detach(struct ata_port *ap)
2225 void __iomem *port_mmio = ahci_port_base(ap);
2226 struct ahci_port_priv *pp = ap->private_data;
2229 ahci_disable_fbs(ap);
2231 cmd = readl(port_mmio + PORT_CMD);
2232 cmd &= ~PORT_CMD_PMP;
2233 writel(cmd, port_mmio + PORT_CMD);
2235 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2237 /* see comment above in ahci_pmp_attach() */
2238 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2239 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2242 int ahci_port_resume(struct ata_port *ap)
2245 ahci_start_port(ap);
2247 if (sata_pmp_attached(ap))
2248 ahci_pmp_attach(ap);
2250 ahci_pmp_detach(ap);
2254 EXPORT_SYMBOL_GPL(ahci_port_resume);
2257 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2259 const char *emsg = NULL;
2262 rc = ahci_deinit_port(ap, &emsg);
2264 ahci_power_down(ap);
2266 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2267 ata_port_freeze(ap);
2274 static int ahci_port_start(struct ata_port *ap)
2276 struct ahci_host_priv *hpriv = ap->host->private_data;
2277 struct device *dev = ap->host->dev;
2278 struct ahci_port_priv *pp;
2281 size_t dma_sz, rx_fis_sz;
2283 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2287 if (ap->host->n_ports > 1) {
2288 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2289 if (!pp->irq_desc) {
2290 devm_kfree(dev, pp);
2293 snprintf(pp->irq_desc, 8,
2294 "%s%d", dev_driver_string(dev), ap->port_no);
2297 /* check FBS capability */
2298 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2299 void __iomem *port_mmio = ahci_port_base(ap);
2300 u32 cmd = readl(port_mmio + PORT_CMD);
2301 if (cmd & PORT_CMD_FBSCP)
2302 pp->fbs_supported = true;
2303 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2304 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2306 pp->fbs_supported = true;
2308 dev_warn(dev, "port %d is not capable of FBS\n",
2312 if (pp->fbs_supported) {
2313 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2314 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2316 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2317 rx_fis_sz = AHCI_RX_FIS_SZ;
2320 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2323 memset(mem, 0, dma_sz);
2326 * First item in chunk of DMA memory: 32-slot command table,
2327 * 32 bytes each in size
2330 pp->cmd_slot_dma = mem_dma;
2332 mem += AHCI_CMD_SLOT_SZ;
2333 mem_dma += AHCI_CMD_SLOT_SZ;
2336 * Second item: Received-FIS area
2339 pp->rx_fis_dma = mem_dma;
2342 mem_dma += rx_fis_sz;
2345 * Third item: data area for storing a single command
2346 * and its scatter-gather table
2349 pp->cmd_tbl_dma = mem_dma;
2352 * Save off initial list of interrupts to be enabled.
2353 * This could be changed later
2355 pp->intr_mask = DEF_PORT_IRQ;
2358 * Switch to per-port locking in case each port has its own MSI vector.
2360 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2361 spin_lock_init(&pp->lock);
2362 ap->lock = &pp->lock;
2365 ap->private_data = pp;
2367 /* engage engines, captain */
2368 return ahci_port_resume(ap);
2371 static void ahci_port_stop(struct ata_port *ap)
2373 const char *emsg = NULL;
2376 /* de-initialize port */
2377 rc = ahci_deinit_port(ap, &emsg);
2379 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2382 void ahci_print_info(struct ata_host *host, const char *scc_s)
2384 struct ahci_host_priv *hpriv = host->private_data;
2385 void __iomem *mmio = hpriv->mmio;
2386 u32 vers, cap, cap2, impl, speed;
2387 const char *speed_s;
2389 vers = readl(mmio + HOST_VERSION);
2392 impl = hpriv->port_map;
2394 speed = (cap >> 20) & 0xf;
2397 else if (speed == 2)
2399 else if (speed == 3)
2405 "AHCI %02x%02x.%02x%02x "
2406 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2409 (vers >> 24) & 0xff,
2410 (vers >> 16) & 0xff,
2414 ((cap >> 8) & 0x1f) + 1,
2428 cap & HOST_CAP_64 ? "64bit " : "",
2429 cap & HOST_CAP_NCQ ? "ncq " : "",
2430 cap & HOST_CAP_SNTF ? "sntf " : "",
2431 cap & HOST_CAP_MPS ? "ilck " : "",
2432 cap & HOST_CAP_SSS ? "stag " : "",
2433 cap & HOST_CAP_ALPM ? "pm " : "",
2434 cap & HOST_CAP_LED ? "led " : "",
2435 cap & HOST_CAP_CLO ? "clo " : "",
2436 cap & HOST_CAP_ONLY ? "only " : "",
2437 cap & HOST_CAP_PMP ? "pmp " : "",
2438 cap & HOST_CAP_FBS ? "fbs " : "",
2439 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2440 cap & HOST_CAP_SSC ? "slum " : "",
2441 cap & HOST_CAP_PART ? "part " : "",
2442 cap & HOST_CAP_CCC ? "ccc " : "",
2443 cap & HOST_CAP_EMS ? "ems " : "",
2444 cap & HOST_CAP_SXS ? "sxs " : "",
2445 cap2 & HOST_CAP2_DESO ? "deso " : "",
2446 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2447 cap2 & HOST_CAP2_SDS ? "sds " : "",
2448 cap2 & HOST_CAP2_APST ? "apst " : "",
2449 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2450 cap2 & HOST_CAP2_BOH ? "boh " : ""
2453 EXPORT_SYMBOL_GPL(ahci_print_info);
2455 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2456 struct ata_port_info *pi)
2459 void __iomem *mmio = hpriv->mmio;
2460 u32 em_loc = readl(mmio + HOST_EM_LOC);
2461 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2463 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2466 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2470 hpriv->em_loc = ((em_loc >> 16) * 4);
2471 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2472 hpriv->em_msg_type = messages;
2473 pi->flags |= ATA_FLAG_EM;
2474 if (!(em_ctl & EM_CTL_ALHD))
2475 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2478 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2480 MODULE_AUTHOR("Jeff Garzik");
2481 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2482 MODULE_LICENSE("GPL");