2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
14 * Look into engine reset on timeout errors. Should not be required.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.12"
37 struct hpt_clock const *clocks[4];
40 /* key for bus clock timings
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
63 static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
83 static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
103 static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
124 static const struct hpt_chip hpt370 = {
135 static const struct hpt_chip hpt370a = {
146 static const struct hpt_chip hpt372 = {
157 static const struct hpt_chip hpt302 = {
168 static const struct hpt_chip hpt371 = {
179 static const struct hpt_chip hpt372a = {
190 static const struct hpt_chip hpt374 = {
202 * hpt37x_find_mode - reset the hpt37x bus
204 * @speed: transfer mode
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
210 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
212 struct hpt_clock *clocks = ap->host->private_data;
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
220 return 0xffffffffU; /* silence compiler warning */
223 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
241 static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
252 static const char *bad_ata100_5[] = {
272 * hpt370_filter - mode selection filter
275 * Block UDMA on devices that cause trouble with this controller.
278 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
286 return ata_bmdma_mode_filter(adev, mask);
290 * hpt370a_filter - mode selection filter
293 * Block UDMA on devices that cause trouble with this controller.
296 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
298 if (adev->class == ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
302 return ata_bmdma_mode_filter(adev, mask);
306 * hpt37x_cable_detect - Detect the cable type
307 * @ap: ATA port to detect on
309 * Return the cable type attached to this port
312 static int hpt37x_cable_detect(struct ata_port *ap)
314 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
317 pci_read_config_byte(pdev, 0x5B, &scr2);
318 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
320 udelay(10); /* debounce */
322 /* Cable register now active */
323 pci_read_config_byte(pdev, 0x5A, &ata66);
325 pci_write_config_byte(pdev, 0x5B, scr2);
327 if (ata66 & (2 >> ap->port_no))
328 return ATA_CBL_PATA40;
330 return ATA_CBL_PATA80;
334 * hpt374_fn1_cable_detect - Detect the cable type
335 * @ap: ATA port to detect on
337 * Return the cable type attached to this port
340 static int hpt374_fn1_cable_detect(struct ata_port *ap)
342 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
343 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
347 /* Do the extra channel work */
348 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
349 /* Set bit 15 of 0x52 to enable TCBLID as input */
350 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
351 pci_read_config_byte(pdev, 0x5A, &ata66);
352 /* Reset TCBLID/FCBLID to output */
353 pci_write_config_word(pdev, mcrbase + 2, mcr3);
355 if (ata66 & (2 >> ap->port_no))
356 return ATA_CBL_PATA40;
358 return ATA_CBL_PATA80;
362 * hpt37x_pre_reset - reset the hpt37x bus
363 * @link: ATA link to reset
364 * @deadline: deadline jiffies for the operation
366 * Perform the initial reset handling for the HPT37x.
369 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
371 struct ata_port *ap = link->ap;
372 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
373 static const struct pci_bits hpt37x_enable_bits[] = {
374 { 0x50, 1, 0x04, 0x04 },
375 { 0x54, 1, 0x04, 0x04 }
377 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
380 /* Reset the state machine */
381 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
384 return ata_sff_prereset(link, deadline);
388 * hpt370_set_piomode - PIO setup
390 * @adev: device on the interface
392 * Perform PIO mode setup.
395 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
397 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
403 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
404 addr2 = 0x51 + 4 * ap->port_no;
406 /* Fast interrupt prediction disable, hold off interrupt disable */
407 pci_read_config_byte(pdev, addr2, &fast);
410 pci_write_config_byte(pdev, addr2, fast);
412 pci_read_config_dword(pdev, addr1, ®);
413 mode = hpt37x_find_mode(ap, adev->pio_mode);
414 mode &= ~0x8000000; /* No FIFO in PIO */
415 mode &= ~0x30070000; /* Leave config bits alone */
416 reg &= 0x30070000; /* Strip timing bits */
417 pci_write_config_dword(pdev, addr1, reg | mode);
421 * hpt370_set_dmamode - DMA timing setup
423 * @adev: Device being configured
425 * Set up the channel for MWDMA or UDMA modes. Much the same as with
426 * PIO, load the mode number and then set MWDMA or UDMA flag.
429 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
431 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
437 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
438 addr2 = 0x51 + 4 * ap->port_no;
440 /* Fast interrupt prediction disable, hold off interrupt disable */
441 pci_read_config_byte(pdev, addr2, &fast);
444 pci_write_config_byte(pdev, addr2, fast);
446 pci_read_config_dword(pdev, addr1, ®);
447 mode = hpt37x_find_mode(ap, adev->dma_mode);
448 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
449 mode &= ~0xC0000000; /* Leave config bits alone */
450 reg &= 0xC0000000; /* Strip timing bits */
451 pci_write_config_dword(pdev, addr1, reg | mode);
455 * hpt370_bmdma_end - DMA engine stop
458 * Work around the HPT370 DMA engine.
461 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
463 struct ata_port *ap = qc->ap;
464 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
465 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
467 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
469 if (dma_stat & 0x01) {
471 dma_stat = ioread8(bmdma + 2);
473 if (dma_stat & 0x01) {
474 /* Clear the engine */
475 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
478 dma_cmd = ioread8(bmdma );
479 iowrite8(dma_cmd & 0xFE, bmdma);
481 dma_stat = ioread8(bmdma + 2);
482 iowrite8(dma_stat | 0x06 , bmdma + 2);
483 /* Clear the engine */
484 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
491 * hpt372_set_piomode - PIO setup
493 * @adev: device on the interface
495 * Perform PIO mode setup.
498 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
500 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
506 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
507 addr2 = 0x51 + 4 * ap->port_no;
509 /* Fast interrupt prediction disable, hold off interrupt disable */
510 pci_read_config_byte(pdev, addr2, &fast);
512 pci_write_config_byte(pdev, addr2, fast);
514 pci_read_config_dword(pdev, addr1, ®);
515 mode = hpt37x_find_mode(ap, adev->pio_mode);
517 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
518 mode &= ~0x80000000; /* No FIFO in PIO */
519 mode &= ~0x30070000; /* Leave config bits alone */
520 reg &= 0x30070000; /* Strip timing bits */
521 pci_write_config_dword(pdev, addr1, reg | mode);
525 * hpt372_set_dmamode - DMA timing setup
527 * @adev: Device being configured
529 * Set up the channel for MWDMA or UDMA modes. Much the same as with
530 * PIO, load the mode number and then set MWDMA or UDMA flag.
533 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
535 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
541 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
542 addr2 = 0x51 + 4 * ap->port_no;
544 /* Fast interrupt prediction disable, hold off interrupt disable */
545 pci_read_config_byte(pdev, addr2, &fast);
547 pci_write_config_byte(pdev, addr2, fast);
549 pci_read_config_dword(pdev, addr1, ®);
550 mode = hpt37x_find_mode(ap, adev->dma_mode);
551 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
552 mode &= ~0xC0000000; /* Leave config bits alone */
553 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
554 reg &= 0xC0000000; /* Strip timing bits */
555 pci_write_config_dword(pdev, addr1, reg | mode);
559 * hpt37x_bmdma_end - DMA engine stop
562 * Clean up after the HPT372 and later DMA engine
565 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
567 struct ata_port *ap = qc->ap;
568 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
569 int mscreg = 0x50 + 4 * ap->port_no;
570 u8 bwsr_stat, msc_stat;
572 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
573 pci_read_config_byte(pdev, mscreg, &msc_stat);
574 if (bwsr_stat & (1 << ap->port_no))
575 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
580 static struct scsi_host_template hpt37x_sht = {
581 ATA_BMDMA_SHT(DRV_NAME),
585 * Configuration for HPT370
588 static struct ata_port_operations hpt370_port_ops = {
589 .inherits = &ata_bmdma_port_ops,
591 .bmdma_stop = hpt370_bmdma_stop,
593 .mode_filter = hpt370_filter,
594 .cable_detect = hpt37x_cable_detect,
595 .set_piomode = hpt370_set_piomode,
596 .set_dmamode = hpt370_set_dmamode,
597 .prereset = hpt37x_pre_reset,
601 * Configuration for HPT370A. Close to 370 but less filters
604 static struct ata_port_operations hpt370a_port_ops = {
605 .inherits = &hpt370_port_ops,
606 .mode_filter = hpt370a_filter,
610 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
611 * and DMA mode setting functionality.
614 static struct ata_port_operations hpt372_port_ops = {
615 .inherits = &ata_bmdma_port_ops,
617 .bmdma_stop = hpt37x_bmdma_stop,
619 .cable_detect = hpt37x_cable_detect,
620 .set_piomode = hpt372_set_piomode,
621 .set_dmamode = hpt372_set_dmamode,
622 .prereset = hpt37x_pre_reset,
626 * Configuration for HPT374. Mode setting works like 372 and friends
627 * but we have a different cable detection procedure for function 1.
630 static struct ata_port_operations hpt374_fn1_port_ops = {
631 .inherits = &hpt372_port_ops,
632 .cable_detect = hpt374_fn1_cable_detect,
633 .prereset = hpt37x_pre_reset,
637 * hpt37x_clock_slot - Turn timing to PC clock entry
638 * @freq: Reported frequency timing
641 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
645 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
647 unsigned int f = (base * freq) / 192; /* Mhz */
649 return 0; /* 33Mhz slot */
651 return 1; /* 40Mhz slot */
653 return 2; /* 50Mhz slot */
654 return 3; /* 60Mhz slot */
658 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
661 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
665 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
671 for(tries = 0; tries < 0x5000; tries++) {
673 pci_read_config_byte(dev, 0x5b, ®5b);
675 /* See if it stays set */
676 for(tries = 0; tries < 0x1000; tries ++) {
677 pci_read_config_byte(dev, 0x5b, ®5b);
679 if ((reg5b & 0x80) == 0)
682 /* Turn off tuning, we have the DPLL set */
683 pci_read_config_dword(dev, 0x5c, ®5c);
684 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
688 /* Never went stable */
692 static u32 hpt374_read_freq(struct pci_dev *pdev)
695 unsigned long io_base = pci_resource_start(pdev, 4);
696 if (PCI_FUNC(pdev->devfn) & 1) {
697 struct pci_dev *pdev_0;
699 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
700 /* Someone hot plugged the controller on us ? */
703 io_base = pci_resource_start(pdev_0, 4);
704 freq = inl(io_base + 0x90);
707 freq = inl(io_base + 0x90);
712 * hpt37x_init_one - Initialise an HPT37X/302
714 * @id: Entry in match table
716 * Initialise an HPT37x device. There are some interesting complications
717 * here. Firstly the chip may report 366 and be one of several variants.
718 * Secondly all the timings depend on the clock for the chip which we must
721 * This is the known chip mappings. It may be missing a couple of later
724 * Chip version PCI Rev Notes
725 * HPT366 4 (HPT366) 0 Other driver
726 * HPT366 4 (HPT366) 1 Other driver
727 * HPT368 4 (HPT366) 2 Other driver
728 * HPT370 4 (HPT366) 3 UDMA100
729 * HPT370A 4 (HPT366) 4 UDMA100
730 * HPT372 4 (HPT366) 5 UDMA133 (1)
731 * HPT372N 4 (HPT366) 6 Other driver
732 * HPT372A 5 (HPT372) 1 UDMA133 (1)
733 * HPT372N 5 (HPT372) 2 Other driver
734 * HPT302 6 (HPT302) 1 UDMA133
735 * HPT302N 6 (HPT302) 2 Other driver
736 * HPT371 7 (HPT371) * UDMA133
737 * HPT374 8 (HPT374) * UDMA133 4 channel
738 * HPT372N 9 (HPT372N) * Other driver
740 * (1) UDMA133 support depends on the bus clock
743 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
745 /* HPT370 - UDMA100 */
746 static const struct ata_port_info info_hpt370 = {
747 .flags = ATA_FLAG_SLAVE_POSS,
748 .pio_mask = ATA_PIO4,
749 .mwdma_mask = ATA_MWDMA2,
750 .udma_mask = ATA_UDMA5,
751 .port_ops = &hpt370_port_ops
753 /* HPT370A - UDMA100 */
754 static const struct ata_port_info info_hpt370a = {
755 .flags = ATA_FLAG_SLAVE_POSS,
756 .pio_mask = ATA_PIO4,
757 .mwdma_mask = ATA_MWDMA2,
758 .udma_mask = ATA_UDMA5,
759 .port_ops = &hpt370a_port_ops
761 /* HPT370 - UDMA100 */
762 static const struct ata_port_info info_hpt370_33 = {
763 .flags = ATA_FLAG_SLAVE_POSS,
764 .pio_mask = ATA_PIO4,
765 .mwdma_mask = ATA_MWDMA2,
766 .udma_mask = ATA_UDMA5,
767 .port_ops = &hpt370_port_ops
769 /* HPT370A - UDMA100 */
770 static const struct ata_port_info info_hpt370a_33 = {
771 .flags = ATA_FLAG_SLAVE_POSS,
772 .pio_mask = ATA_PIO4,
773 .mwdma_mask = ATA_MWDMA2,
774 .udma_mask = ATA_UDMA5,
775 .port_ops = &hpt370a_port_ops
777 /* HPT371, 372 and friends - UDMA133 */
778 static const struct ata_port_info info_hpt372 = {
779 .flags = ATA_FLAG_SLAVE_POSS,
780 .pio_mask = ATA_PIO4,
781 .mwdma_mask = ATA_MWDMA2,
782 .udma_mask = ATA_UDMA6,
783 .port_ops = &hpt372_port_ops
785 /* HPT374 - UDMA100, function 1 uses different prereset method */
786 static const struct ata_port_info info_hpt374_fn0 = {
787 .flags = ATA_FLAG_SLAVE_POSS,
788 .pio_mask = ATA_PIO4,
789 .mwdma_mask = ATA_MWDMA2,
790 .udma_mask = ATA_UDMA5,
791 .port_ops = &hpt372_port_ops
793 static const struct ata_port_info info_hpt374_fn1 = {
794 .flags = ATA_FLAG_SLAVE_POSS,
795 .pio_mask = ATA_PIO4,
796 .mwdma_mask = ATA_MWDMA2,
797 .udma_mask = ATA_UDMA5,
798 .port_ops = &hpt374_fn1_port_ops
801 static const int MHz[4] = { 33, 40, 50, 66 };
802 void *private_data = NULL;
803 const struct ata_port_info *ppi[] = { NULL, NULL };
811 unsigned long iobase = pci_resource_start(dev, 4);
813 const struct hpt_chip *chip_table;
817 rc = pcim_enable_device(dev);
821 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
824 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
825 /* May be a later chip in disguise. Check */
826 /* Older chips are in the HPT366 driver. Ignore them */
829 /* N series chips have their own driver. Ignore */
835 ppi[0] = &info_hpt370;
836 chip_table = &hpt370;
840 ppi[0] = &info_hpt370a;
841 chip_table = &hpt370a;
845 ppi[0] = &info_hpt372;
846 chip_table = &hpt372;
849 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
853 switch(dev->device) {
854 case PCI_DEVICE_ID_TTI_HPT372:
855 /* 372N if rev >= 2*/
858 ppi[0] = &info_hpt372;
859 chip_table = &hpt372a;
861 case PCI_DEVICE_ID_TTI_HPT302:
862 /* 302N if rev > 1 */
865 ppi[0] = &info_hpt372;
867 chip_table = &hpt302;
869 case PCI_DEVICE_ID_TTI_HPT371:
872 ppi[0] = &info_hpt372;
873 chip_table = &hpt371;
874 /* Single channel device, master is not present
875 but the BIOS (or us for non x86) must mark it
877 pci_read_config_byte(dev, 0x50, &mcr1);
879 pci_write_config_byte(dev, 0x50, mcr1);
881 case PCI_DEVICE_ID_TTI_HPT374:
882 chip_table = &hpt374;
883 if (!(PCI_FUNC(dev->devfn) & 1))
884 *ppi = &info_hpt374_fn0;
886 *ppi = &info_hpt374_fn1;
889 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
893 /* Ok so this is a chip we support */
895 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
896 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
897 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
898 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
900 pci_read_config_byte(dev, 0x5A, &irqmask);
902 pci_write_config_byte(dev, 0x5a, irqmask);
905 * default to pci clock. make sure MA15/16 are set to output
906 * to prevent drives having problems with 40-pin cables. Needed
907 * for some drives such as IBM-DTLA which will not enter ready
908 * state on reset when PDIAG is a input.
911 pci_write_config_byte(dev, 0x5b, 0x23);
914 * HighPoint does this for HPT372A.
915 * NOTE: This register is only writeable via I/O space.
917 if (chip_table == &hpt372a)
918 outb(0x0e, iobase + 0x9c);
920 /* Some devices do not let this value be accessed via PCI space
921 according to the old driver. In addition we must use the value
922 from FN 0 on the HPT374 */
924 if (chip_table == &hpt374) {
925 freq = hpt374_read_freq(dev);
929 freq = inl(iobase + 0x90);
931 if ((freq >> 12) != 0xABCDE) {
936 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
938 /* This is the process the HPT371 BIOS is reported to use */
939 for(i = 0; i < 128; i++) {
940 pci_read_config_byte(dev, 0x78, &sr);
949 * Turn the frequency check into a band and then find a timing
953 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
954 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
956 * We need to try PLL mode instead
958 * For non UDMA133 capable devices we should
959 * use a 50MHz DPLL by choice
961 unsigned int f_low, f_high;
965 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
967 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
972 /* Select the DPLL clock. */
973 pci_write_config_byte(dev, 0x5b, 0x21);
974 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
976 for(adjust = 0; adjust < 8; adjust++) {
977 if (hpt37x_calibrate_dpll(dev))
979 /* See if it'll settle at a fractionally different clock */
981 f_low -= adjust >> 1;
983 f_high += adjust >> 1;
984 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
987 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
991 private_data = (void *)hpt37x_timings_66;
993 private_data = (void *)hpt37x_timings_50;
995 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
996 MHz[clock_slot], MHz[dpll]);
998 private_data = (void *)chip_table->clocks[clock_slot];
1000 * Perform a final fixup. Note that we will have used the
1001 * DPLL on the HPT372 which means we don't have to worry
1002 * about lack of UDMA133 support on lower clocks
1005 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1006 ppi[0] = &info_hpt370_33;
1007 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1008 ppi[0] = &info_hpt370a_33;
1009 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1010 chip_table->name, MHz[clock_slot]);
1013 /* Now kick off ATA set up */
1014 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
1017 static const struct pci_device_id hpt37x[] = {
1018 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1019 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1020 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1021 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1022 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1027 static struct pci_driver hpt37x_pci_driver = {
1030 .probe = hpt37x_init_one,
1031 .remove = ata_pci_remove_one
1034 static int __init hpt37x_init(void)
1036 return pci_register_driver(&hpt37x_pci_driver);
1039 static void __exit hpt37x_exit(void)
1041 pci_unregister_driver(&hpt37x_pci_driver);
1044 MODULE_AUTHOR("Alan Cox");
1045 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1046 MODULE_LICENSE("GPL");
1047 MODULE_DEVICE_TABLE(pci, hpt37x);
1048 MODULE_VERSION(DRV_VERSION);
1050 module_init(hpt37x_init);
1051 module_exit(hpt37x_exit);