2 * drivers/ata/pata_mpc52xx.c
4 * libata driver for the Freescale MPC52xx on-chip IDE interface
6 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
7 * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/libata.h>
20 #include <asm/types.h>
22 #include <asm/of_platform.h>
23 #include <asm/mpc52xx.h>
26 #define DRV_NAME "mpc52xx_ata"
27 #define DRV_VERSION "0.1.2"
30 /* Private structures used by the driver */
31 struct mpc52xx_ata_timings {
36 struct mpc52xx_ata_priv {
37 unsigned int ipb_period;
38 struct mpc52xx_ata __iomem * ata_regs;
40 struct mpc52xx_ata_timings timings[2];
45 /* ATAPI-4 PIO specs (in ns) */
46 static const int ataspec_t0[5] = {600, 383, 240, 180, 120};
47 static const int ataspec_t1[5] = { 70, 50, 30, 30, 25};
48 static const int ataspec_t2_8[5] = {290, 290, 290, 80, 70};
49 static const int ataspec_t2_16[5] = {165, 125, 100, 80, 70};
50 static const int ataspec_t2i[5] = { 0, 0, 0, 70, 25};
51 static const int ataspec_t4[5] = { 30, 20, 15, 10, 10};
52 static const int ataspec_ta[5] = { 35, 35, 35, 35, 35};
54 #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
57 /* Bit definitions inside the registers */
58 #define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
59 #define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
60 #define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
61 #define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
63 #define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
64 #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
65 #define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
66 #define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
68 #define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
70 #define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
71 #define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
72 #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
73 #define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
74 #define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
75 #define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
76 #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
79 /* Structure of the hardware registers */
82 /* Host interface registers */
83 u32 config; /* ATA + 0x00 Host configuration */
84 u32 host_status; /* ATA + 0x04 Host controller status */
85 u32 pio1; /* ATA + 0x08 PIO Timing 1 */
86 u32 pio2; /* ATA + 0x0c PIO Timing 2 */
87 u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
88 u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
89 u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
90 u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
91 u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
92 u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
93 u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
94 u32 share_cnt; /* ATA + 0x2c ATA share counter */
98 u32 fifo_data; /* ATA + 0x3c */
99 u8 fifo_status_frame; /* ATA + 0x40 */
100 u8 fifo_status; /* ATA + 0x41 */
102 u8 fifo_control; /* ATA + 0x44 */
104 u16 fifo_alarm; /* ATA + 0x4a */
106 u16 fifo_rdp; /* ATA + 0x4e */
108 u16 fifo_wrp; /* ATA + 0x52 */
110 u16 fifo_lfrdp; /* ATA + 0x56 */
112 u16 fifo_lfwrp; /* ATA + 0x5a */
114 /* Drive TaskFile registers */
115 u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
117 u16 tf_data; /* ATA + 0x60 TASKFILE Data */
119 u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
121 u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
123 u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
125 u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
127 u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
129 u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
131 u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
132 u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
137 /* ======================================================================== */
139 /* ======================================================================== */
142 /* MPC52xx low level hw control */
145 mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
147 struct mpc52xx_ata_timings *timing = &priv->timings[dev];
148 unsigned int ipb_period = priv->ipb_period;
149 unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;
151 if ((pio<0) || (pio>4))
154 t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
155 t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
156 t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
157 t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
158 t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
159 t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
160 ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
162 timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
163 timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
169 mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
171 struct mpc52xx_ata __iomem *regs = priv->ata_regs;
172 struct mpc52xx_ata_timings *timing = &priv->timings[device];
174 out_be32(®s->pio1, timing->pio1);
175 out_be32(®s->pio2, timing->pio2);
176 out_be32(®s->mdma1, 0);
177 out_be32(®s->mdma2, 0);
178 out_be32(®s->udma1, 0);
179 out_be32(®s->udma2, 0);
180 out_be32(®s->udma3, 0);
181 out_be32(®s->udma4, 0);
182 out_be32(®s->udma5, 0);
188 mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
190 struct mpc52xx_ata __iomem *regs = priv->ata_regs;
193 /* Clear share_cnt (all sample code do this ...) */
194 out_be32(®s->share_cnt, 0);
196 /* Configure and reset host */
197 out_be32(®s->config,
198 MPC52xx_ATA_HOSTCONF_IE |
199 MPC52xx_ATA_HOSTCONF_IORDY |
200 MPC52xx_ATA_HOSTCONF_SMR |
201 MPC52xx_ATA_HOSTCONF_FR);
205 out_be32(®s->config,
206 MPC52xx_ATA_HOSTCONF_IE |
207 MPC52xx_ATA_HOSTCONF_IORDY);
209 /* Set the time slot to 1us */
210 tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
211 out_be32(®s->share_cnt, tslot << 16 );
213 /* Init timings to PIO0 */
214 memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
216 mpc52xx_ata_compute_pio_timings(priv, 0, 0);
217 mpc52xx_ata_compute_pio_timings(priv, 1, 0);
219 mpc52xx_ata_apply_timings(priv, 0);
225 /* ======================================================================== */
227 /* ======================================================================== */
230 mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
232 struct mpc52xx_ata_priv *priv = ap->host->private_data;
235 pio = adev->pio_mode - XFER_PIO_0;
237 rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
240 printk(KERN_ERR DRV_NAME
241 ": Trying to select invalid PIO mode %d\n", pio);
245 mpc52xx_ata_apply_timings(priv, adev->devno);
248 mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
250 struct mpc52xx_ata_priv *priv = ap->host->private_data;
252 if (device != priv->csel)
253 mpc52xx_ata_apply_timings(priv, device);
255 ata_std_dev_select(ap,device);
259 mpc52xx_ata_error_handler(struct ata_port *ap)
261 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
267 static struct scsi_host_template mpc52xx_ata_sht = {
268 .module = THIS_MODULE,
270 .ioctl = ata_scsi_ioctl,
271 .queuecommand = ata_scsi_queuecmd,
272 .can_queue = ATA_DEF_QUEUE,
273 .this_id = ATA_SHT_THIS_ID,
274 .sg_tablesize = LIBATA_MAX_PRD,
275 .max_sectors = ATA_MAX_SECTORS,
276 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
277 .emulated = ATA_SHT_EMULATED,
278 .use_clustering = ATA_SHT_USE_CLUSTERING,
279 .proc_name = DRV_NAME,
280 .dma_boundary = ATA_DMA_BOUNDARY,
281 .slave_configure = ata_scsi_slave_config,
282 .bios_param = ata_std_bios_param,
285 static struct ata_port_operations mpc52xx_ata_port_ops = {
286 .set_piomode = mpc52xx_ata_set_piomode,
287 .dev_select = mpc52xx_ata_dev_select,
288 .tf_load = ata_tf_load,
289 .tf_read = ata_tf_read,
290 .check_status = ata_check_status,
291 .exec_command = ata_exec_command,
292 .freeze = ata_bmdma_freeze,
293 .thaw = ata_bmdma_thaw,
294 .error_handler = mpc52xx_ata_error_handler,
295 .cable_detect = ata_cable_40wire,
296 .qc_prep = ata_qc_prep,
297 .qc_issue = ata_qc_issue_prot,
298 .data_xfer = ata_data_xfer,
299 .irq_clear = ata_noop_irq_clear,
300 .irq_on = ata_irq_on,
301 .port_start = ata_port_start,
305 mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv,
306 unsigned long raw_ata_regs)
308 struct ata_host *host;
310 struct ata_ioports *aio;
312 host = ata_host_alloc(dev, 1);
317 ap->flags |= ATA_FLAG_SLAVE_POSS;
318 ap->pio_mask = 0x1f; /* Up to PIO4 */
319 ap->mwdma_mask = 0x00; /* No MWDMA */
320 ap->udma_mask = 0x00; /* No UDMA */
321 ap->ops = &mpc52xx_ata_port_ops;
322 host->private_data = priv;
325 aio->cmd_addr = NULL; /* Don't have a classic reg block */
326 aio->altstatus_addr = &priv->ata_regs->tf_control;
327 aio->ctl_addr = &priv->ata_regs->tf_control;
328 aio->data_addr = &priv->ata_regs->tf_data;
329 aio->error_addr = &priv->ata_regs->tf_features;
330 aio->feature_addr = &priv->ata_regs->tf_features;
331 aio->nsect_addr = &priv->ata_regs->tf_sec_count;
332 aio->lbal_addr = &priv->ata_regs->tf_sec_num;
333 aio->lbam_addr = &priv->ata_regs->tf_cyl_low;
334 aio->lbah_addr = &priv->ata_regs->tf_cyl_high;
335 aio->device_addr = &priv->ata_regs->tf_dev_head;
336 aio->status_addr = &priv->ata_regs->tf_command;
337 aio->command_addr = &priv->ata_regs->tf_command;
339 ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
342 return ata_host_activate(host, priv->ata_irq, ata_interrupt, 0,
346 static struct mpc52xx_ata_priv *
347 mpc52xx_ata_remove_one(struct device *dev)
349 struct ata_host *host = dev_get_drvdata(dev);
350 struct mpc52xx_ata_priv *priv = host->private_data;
352 ata_host_detach(host);
358 /* ======================================================================== */
359 /* OF Platform driver */
360 /* ======================================================================== */
363 mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
365 unsigned int ipb_freq;
366 struct resource res_mem;
368 struct mpc52xx_ata __iomem *ata_regs;
369 struct mpc52xx_ata_priv *priv;
372 /* Get ipb frequency */
373 ipb_freq = mpc52xx_find_ipb_freq(op->node);
375 printk(KERN_ERR DRV_NAME ": "
376 "Unable to find IPB Bus frequency\n" );
380 /* Get IRQ and register */
381 rv = of_address_to_resource(op->node, 0, &res_mem);
383 printk(KERN_ERR DRV_NAME ": "
384 "Error while parsing device node resource\n" );
388 ata_irq = irq_of_parse_and_map(op->node, 0);
389 if (ata_irq == NO_IRQ) {
390 printk(KERN_ERR DRV_NAME ": "
391 "Error while mapping the irq\n");
395 /* Request mem region */
396 if (!devm_request_mem_region(&op->dev, res_mem.start,
397 sizeof(struct mpc52xx_ata), DRV_NAME)) {
398 printk(KERN_ERR DRV_NAME ": "
399 "Error while requesting mem region\n");
404 /* Remap registers */
405 ata_regs = devm_ioremap(&op->dev, res_mem.start,
406 sizeof(struct mpc52xx_ata));
408 printk(KERN_ERR DRV_NAME ": "
409 "Error while mapping register set\n");
414 /* Prepare our private structure */
415 priv = devm_kzalloc(&op->dev, sizeof(struct mpc52xx_ata_priv),
418 printk(KERN_ERR DRV_NAME ": "
419 "Error while allocating private structure\n");
424 priv->ipb_period = 1000000000 / (ipb_freq / 1000);
425 priv->ata_regs = ata_regs;
426 priv->ata_irq = ata_irq;
430 rv = mpc52xx_ata_hw_init(priv);
432 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
436 /* Register ourselves to libata */
437 rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start);
439 printk(KERN_ERR DRV_NAME ": "
440 "Error while registering to ATA layer\n");
449 irq_dispose_mapping(ata_irq);
454 mpc52xx_ata_remove(struct of_device *op)
456 struct mpc52xx_ata_priv *priv;
458 priv = mpc52xx_ata_remove_one(&op->dev);
459 irq_dispose_mapping(priv->ata_irq);
468 mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
470 struct ata_host *host = dev_get_drvdata(&op->dev);
472 return ata_host_suspend(host, state);
476 mpc52xx_ata_resume(struct of_device *op)
478 struct ata_host *host = dev_get_drvdata(&op->dev);
479 struct mpc52xx_ata_priv *priv = host->private_data;
482 rv = mpc52xx_ata_hw_init(priv);
484 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
488 ata_host_resume(host);
496 static struct of_device_id mpc52xx_ata_of_match[] = {
497 { .compatible = "fsl,mpc5200-ata", },
498 { .compatible = "mpc5200-ata", },
503 static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
504 .owner = THIS_MODULE,
506 .match_table = mpc52xx_ata_of_match,
507 .probe = mpc52xx_ata_probe,
508 .remove = mpc52xx_ata_remove,
510 .suspend = mpc52xx_ata_suspend,
511 .resume = mpc52xx_ata_resume,
515 .owner = THIS_MODULE,
520 /* ======================================================================== */
522 /* ======================================================================== */
525 mpc52xx_ata_init(void)
527 printk(KERN_INFO "ata: MPC52xx IDE/ATA libata driver\n");
528 return of_register_platform_driver(&mpc52xx_ata_of_platform_driver);
532 mpc52xx_ata_exit(void)
534 of_unregister_platform_driver(&mpc52xx_ata_of_platform_driver);
537 module_init(mpc52xx_ata_init);
538 module_exit(mpc52xx_ata_exit);
540 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
541 MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
542 MODULE_LICENSE("GPL");
543 MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
544 MODULE_VERSION(DRV_VERSION);