2 * pata_sis.c - SiS ATA driver
4 * (C) 2005 Red Hat <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
7 * Based upon linux/drivers/ide/pci/sis5513.c
8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
11 * SiS Taiwan : for direct support and hardware.
12 * Daniela Engert : for initial ATA100 advices and numerous others.
13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
14 * for checking code correctness, providing patches.
15 * Original tests and design on the SiS620 chipset.
16 * ATA100 tests and design on the SiS735 chipset.
17 * ATA16/33 support from specs
18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
35 #include <linux/ata.h>
38 #define DRV_NAME "pata_sis"
39 #define DRV_VERSION "0.5.2"
42 u16 device; /* PCI host ID */
43 const struct ata_port_info *info; /* Info block */
44 /* Probably add family, cable detect type etc here to clean
54 static const struct sis_laptop sis_laptop[] = {
55 /* devid, subvendor, subdev */
56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
63 static int sis_short_ata40(struct pci_dev *dev)
65 const struct sis_laptop *lap = &sis_laptop[0];
68 if (lap->device == dev->device &&
69 lap->subvendor == dev->subsystem_vendor &&
70 lap->subdevice == dev->subsystem_device)
79 * sis_old_port_base - return PCI configuration base for dev
82 * Returns the base of the PCI configuration registers for this port
86 static int sis_old_port_base(struct ata_device *adev)
88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
92 * sis_133_cable_detect - check for 40/80 pin
94 * @deadline: deadline jiffies for the operation
96 * Perform cable detection for the later UDMA133 capable
100 static int sis_133_cable_detect(struct ata_port *ap)
102 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
105 /* The top bit of this register is the cable detect bit */
106 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
107 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
108 return ATA_CBL_PATA40;
109 return ATA_CBL_PATA80;
113 * sis_66_cable_detect - check for 40/80 pin
115 * @deadline: deadline jiffies for the operation
117 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
118 * SiS IDE controllers.
121 static int sis_66_cable_detect(struct ata_port *ap)
123 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
126 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
127 pci_read_config_byte(pdev, 0x48, &tmp);
129 if ((tmp & 0x10) && !sis_short_ata40(pdev))
130 return ATA_CBL_PATA40;
131 return ATA_CBL_PATA80;
136 * sis_pre_reset - probe begin
138 * @deadline: deadline jiffies for the operation
140 * Set up cable type and use generic probe init
143 static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
145 static const struct pci_bits sis_enable_bits[] = {
146 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
147 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
150 struct ata_port *ap = link->ap;
151 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
153 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
156 /* Clear the FIFO settings. We can't enable the FIFO until
157 we know we are poking at a disk */
158 pci_write_config_byte(pdev, 0x4B, 0);
159 return ata_std_prereset(link, deadline);
164 * sis_error_handler - Probe specified port on PATA host controller
168 * None (inherited from caller).
171 static void sis_error_handler(struct ata_port *ap)
173 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
177 * sis_set_fifo - Set RWP fifo bits for this device
181 * SIS chipsets implement prefetch/postwrite bits for each device
182 * on both channels. This functionality is not ATAPI compatible and
183 * must be configured according to the class of device present
186 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
188 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
192 mask <<= (2 * ap->port_no);
193 mask <<= adev->devno;
195 /* This holds various bits including the FIFO control */
196 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
199 /* Enable for ATA (disk) only */
200 if (adev->class == ATA_DEV_ATA)
202 pci_write_config_byte(pdev, 0x4B, fifoctrl);
206 * sis_old_set_piomode - Initialize host controller PATA PIO timings
207 * @ap: Port whose timings we are configuring
208 * @adev: Device we are configuring for.
210 * Set PIO mode for device, in host controller PCI config space. This
211 * function handles PIO set up for all chips that are pre ATA100 and
212 * also early ATA100 devices.
215 * None (inherited from caller).
218 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
220 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
221 int port = sis_old_port_base(adev);
223 int speed = adev->pio_mode - XFER_PIO_0;
225 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
226 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
228 sis_set_fifo(ap, adev);
230 pci_read_config_byte(pdev, port, &t1);
231 pci_read_config_byte(pdev, port + 1, &t2);
233 t1 &= ~0x0F; /* Clear active/recovery timings */
237 t2 |= recovery[speed];
239 pci_write_config_byte(pdev, port, t1);
240 pci_write_config_byte(pdev, port + 1, t2);
244 * sis_100_set_piomode - Initialize host controller PATA PIO timings
245 * @ap: Port whose timings we are configuring
246 * @adev: Device we are configuring for.
248 * Set PIO mode for device, in host controller PCI config space. This
249 * function handles PIO set up for ATA100 devices and early ATA133.
252 * None (inherited from caller).
255 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
257 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
258 int port = sis_old_port_base(adev);
259 int speed = adev->pio_mode - XFER_PIO_0;
261 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
263 sis_set_fifo(ap, adev);
265 pci_write_config_byte(pdev, port, actrec[speed]);
269 * sis_133_set_piomode - Initialize host controller PATA PIO timings
270 * @ap: Port whose timings we are configuring
271 * @adev: Device we are configuring for.
273 * Set PIO mode for device, in host controller PCI config space. This
274 * function handles PIO set up for the later ATA133 devices.
277 * None (inherited from caller).
280 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
282 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
286 int speed = adev->pio_mode - XFER_PIO_0;
288 const u32 timing133[] = {
289 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
295 const u32 timing100[] = {
296 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
303 sis_set_fifo(ap, adev);
305 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
306 pci_read_config_dword(pdev, 0x54, ®54);
307 if (reg54 & 0x40000000)
309 port += 8 * ap->port_no + 4 * adev->devno;
311 pci_read_config_dword(pdev, port, &t1);
312 t1 &= 0xC0C00FFF; /* Mask out timing */
314 if (t1 & 0x08) /* 100 or 133 ? */
315 t1 |= timing133[speed];
317 t1 |= timing100[speed];
318 pci_write_config_byte(pdev, port, t1);
322 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
323 * @ap: Port whose timings we are configuring
324 * @adev: Device to program
326 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
327 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
328 * the old ide/pci driver.
331 * None (inherited from caller).
334 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
336 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
337 int speed = adev->dma_mode - XFER_MW_DMA_0;
338 int drive_pci = sis_old_port_base(adev);
341 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
342 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
344 pci_read_config_word(pdev, drive_pci, &timing);
346 if (adev->dma_mode < XFER_UDMA_0) {
347 /* bits 3-0 hold recovery timing bits 8-10 active timing and
348 the higher bits are dependant on the device */
350 timing |= mwdma_bits[speed];
352 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
353 speed = adev->dma_mode - XFER_UDMA_0;
355 timing |= udma_bits[speed];
357 pci_write_config_word(pdev, drive_pci, timing);
361 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
362 * @ap: Port whose timings we are configuring
363 * @adev: Device to program
365 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
366 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
367 * the old ide/pci driver.
370 * None (inherited from caller).
373 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
375 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
376 int speed = adev->dma_mode - XFER_MW_DMA_0;
377 int drive_pci = sis_old_port_base(adev);
380 /* MWDMA 0-2 and UDMA 0-5 */
381 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
382 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
384 pci_read_config_word(pdev, drive_pci, &timing);
386 if (adev->dma_mode < XFER_UDMA_0) {
387 /* bits 3-0 hold recovery timing bits 8-10 active timing and
388 the higher bits are dependant on the device, bit 15 udma */
390 timing |= mwdma_bits[speed];
392 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
393 speed = adev->dma_mode - XFER_UDMA_0;
395 timing |= udma_bits[speed];
397 pci_write_config_word(pdev, drive_pci, timing);
401 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
402 * @ap: Port whose timings we are configuring
403 * @adev: Device to program
405 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
406 * Handles UDMA66 and early UDMA100 devices.
409 * None (inherited from caller).
412 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
414 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
415 int speed = adev->dma_mode - XFER_MW_DMA_0;
416 int drive_pci = sis_old_port_base(adev);
419 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
421 pci_read_config_byte(pdev, drive_pci + 1, &timing);
423 if (adev->dma_mode < XFER_UDMA_0) {
424 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
426 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
427 speed = adev->dma_mode - XFER_UDMA_0;
429 timing |= udma_bits[speed];
431 pci_write_config_byte(pdev, drive_pci + 1, timing);
435 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
436 * @ap: Port whose timings we are configuring
437 * @adev: Device to program
439 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
440 * Handles early SiS 961 bridges.
443 * None (inherited from caller).
446 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
448 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
449 int speed = adev->dma_mode - XFER_MW_DMA_0;
450 int drive_pci = sis_old_port_base(adev);
452 /* Low 4 bits are timing */
453 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
455 pci_read_config_byte(pdev, drive_pci + 1, &timing);
457 if (adev->dma_mode < XFER_UDMA_0) {
458 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
460 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
461 speed = adev->dma_mode - XFER_UDMA_0;
463 timing |= udma_bits[speed];
465 pci_write_config_byte(pdev, drive_pci + 1, timing);
469 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
470 * @ap: Port whose timings we are configuring
471 * @adev: Device to program
473 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
476 * None (inherited from caller).
479 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
481 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
482 int speed = adev->dma_mode - XFER_MW_DMA_0;
487 /* bits 4- cycle time 8 - cvs time */
488 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
489 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
491 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
492 pci_read_config_dword(pdev, 0x54, ®54);
493 if (reg54 & 0x40000000)
495 port += (8 * ap->port_no) + (4 * adev->devno);
497 pci_read_config_dword(pdev, port, &t1);
499 if (adev->dma_mode < XFER_UDMA_0) {
501 /* FIXME: need data sheet to add MWDMA here. Also lacking on
504 speed = adev->dma_mode - XFER_UDMA_0;
505 /* if & 8 no UDMA133 - need info for ... */
509 t1 |= timing_u133[speed];
511 t1 |= timing_u100[speed];
513 pci_write_config_dword(pdev, port, t1);
516 static struct scsi_host_template sis_sht = {
517 ATA_BMDMA_SHT(DRV_NAME),
520 static const struct ata_port_operations sis_133_ops = {
521 .set_piomode = sis_133_set_piomode,
522 .set_dmamode = sis_133_set_dmamode,
523 .mode_filter = ata_pci_default_filter,
525 .tf_load = ata_tf_load,
526 .tf_read = ata_tf_read,
527 .check_status = ata_check_status,
528 .exec_command = ata_exec_command,
529 .dev_select = ata_std_dev_select,
531 .freeze = ata_bmdma_freeze,
532 .thaw = ata_bmdma_thaw,
533 .error_handler = sis_error_handler,
534 .post_internal_cmd = ata_bmdma_post_internal_cmd,
535 .cable_detect = sis_133_cable_detect,
537 .bmdma_setup = ata_bmdma_setup,
538 .bmdma_start = ata_bmdma_start,
539 .bmdma_stop = ata_bmdma_stop,
540 .bmdma_status = ata_bmdma_status,
541 .qc_prep = ata_qc_prep,
542 .qc_issue = ata_qc_issue_prot,
543 .data_xfer = ata_data_xfer,
545 .irq_handler = ata_interrupt,
546 .irq_clear = ata_bmdma_irq_clear,
547 .irq_on = ata_irq_on,
549 .port_start = ata_sff_port_start,
552 static const struct ata_port_operations sis_133_for_sata_ops = {
553 .set_piomode = sis_133_set_piomode,
554 .set_dmamode = sis_133_set_dmamode,
555 .mode_filter = ata_pci_default_filter,
557 .tf_load = ata_tf_load,
558 .tf_read = ata_tf_read,
559 .check_status = ata_check_status,
560 .exec_command = ata_exec_command,
561 .dev_select = ata_std_dev_select,
563 .freeze = ata_bmdma_freeze,
564 .thaw = ata_bmdma_thaw,
565 .error_handler = ata_bmdma_error_handler,
566 .post_internal_cmd = ata_bmdma_post_internal_cmd,
567 .cable_detect = sis_133_cable_detect,
569 .bmdma_setup = ata_bmdma_setup,
570 .bmdma_start = ata_bmdma_start,
571 .bmdma_stop = ata_bmdma_stop,
572 .bmdma_status = ata_bmdma_status,
573 .qc_prep = ata_qc_prep,
574 .qc_issue = ata_qc_issue_prot,
575 .data_xfer = ata_data_xfer,
577 .irq_handler = ata_interrupt,
578 .irq_clear = ata_bmdma_irq_clear,
579 .irq_on = ata_irq_on,
581 .port_start = ata_sff_port_start,
584 static const struct ata_port_operations sis_133_early_ops = {
585 .set_piomode = sis_100_set_piomode,
586 .set_dmamode = sis_133_early_set_dmamode,
587 .mode_filter = ata_pci_default_filter,
589 .tf_load = ata_tf_load,
590 .tf_read = ata_tf_read,
591 .check_status = ata_check_status,
592 .exec_command = ata_exec_command,
593 .dev_select = ata_std_dev_select,
595 .freeze = ata_bmdma_freeze,
596 .thaw = ata_bmdma_thaw,
597 .error_handler = sis_error_handler,
598 .post_internal_cmd = ata_bmdma_post_internal_cmd,
599 .cable_detect = sis_66_cable_detect,
601 .bmdma_setup = ata_bmdma_setup,
602 .bmdma_start = ata_bmdma_start,
603 .bmdma_stop = ata_bmdma_stop,
604 .bmdma_status = ata_bmdma_status,
605 .qc_prep = ata_qc_prep,
606 .qc_issue = ata_qc_issue_prot,
607 .data_xfer = ata_data_xfer,
609 .irq_handler = ata_interrupt,
610 .irq_clear = ata_bmdma_irq_clear,
611 .irq_on = ata_irq_on,
613 .port_start = ata_sff_port_start,
616 static const struct ata_port_operations sis_100_ops = {
617 .set_piomode = sis_100_set_piomode,
618 .set_dmamode = sis_100_set_dmamode,
619 .mode_filter = ata_pci_default_filter,
621 .tf_load = ata_tf_load,
622 .tf_read = ata_tf_read,
623 .check_status = ata_check_status,
624 .exec_command = ata_exec_command,
625 .dev_select = ata_std_dev_select,
627 .freeze = ata_bmdma_freeze,
628 .thaw = ata_bmdma_thaw,
629 .error_handler = sis_error_handler,
630 .post_internal_cmd = ata_bmdma_post_internal_cmd,
631 .cable_detect = sis_66_cable_detect,
633 .bmdma_setup = ata_bmdma_setup,
634 .bmdma_start = ata_bmdma_start,
635 .bmdma_stop = ata_bmdma_stop,
636 .bmdma_status = ata_bmdma_status,
637 .qc_prep = ata_qc_prep,
638 .qc_issue = ata_qc_issue_prot,
639 .data_xfer = ata_data_xfer,
641 .irq_handler = ata_interrupt,
642 .irq_clear = ata_bmdma_irq_clear,
643 .irq_on = ata_irq_on,
645 .port_start = ata_sff_port_start,
648 static const struct ata_port_operations sis_66_ops = {
649 .set_piomode = sis_old_set_piomode,
650 .set_dmamode = sis_66_set_dmamode,
651 .mode_filter = ata_pci_default_filter,
653 .tf_load = ata_tf_load,
654 .tf_read = ata_tf_read,
655 .check_status = ata_check_status,
656 .exec_command = ata_exec_command,
657 .dev_select = ata_std_dev_select,
658 .cable_detect = sis_66_cable_detect,
660 .freeze = ata_bmdma_freeze,
661 .thaw = ata_bmdma_thaw,
662 .error_handler = sis_error_handler,
663 .post_internal_cmd = ata_bmdma_post_internal_cmd,
665 .bmdma_setup = ata_bmdma_setup,
666 .bmdma_start = ata_bmdma_start,
667 .bmdma_stop = ata_bmdma_stop,
668 .bmdma_status = ata_bmdma_status,
669 .qc_prep = ata_qc_prep,
670 .qc_issue = ata_qc_issue_prot,
671 .data_xfer = ata_data_xfer,
673 .irq_handler = ata_interrupt,
674 .irq_clear = ata_bmdma_irq_clear,
675 .irq_on = ata_irq_on,
677 .port_start = ata_sff_port_start,
680 static const struct ata_port_operations sis_old_ops = {
681 .set_piomode = sis_old_set_piomode,
682 .set_dmamode = sis_old_set_dmamode,
683 .mode_filter = ata_pci_default_filter,
685 .tf_load = ata_tf_load,
686 .tf_read = ata_tf_read,
687 .check_status = ata_check_status,
688 .exec_command = ata_exec_command,
689 .dev_select = ata_std_dev_select,
691 .freeze = ata_bmdma_freeze,
692 .thaw = ata_bmdma_thaw,
693 .error_handler = sis_error_handler,
694 .post_internal_cmd = ata_bmdma_post_internal_cmd,
695 .cable_detect = ata_cable_40wire,
697 .bmdma_setup = ata_bmdma_setup,
698 .bmdma_start = ata_bmdma_start,
699 .bmdma_stop = ata_bmdma_stop,
700 .bmdma_status = ata_bmdma_status,
701 .qc_prep = ata_qc_prep,
702 .qc_issue = ata_qc_issue_prot,
703 .data_xfer = ata_data_xfer,
705 .irq_handler = ata_interrupt,
706 .irq_clear = ata_bmdma_irq_clear,
707 .irq_on = ata_irq_on,
709 .port_start = ata_sff_port_start,
712 static const struct ata_port_info sis_info = {
714 .flags = ATA_FLAG_SLAVE_POSS,
715 .pio_mask = 0x1f, /* pio0-4 */
718 .port_ops = &sis_old_ops,
720 static const struct ata_port_info sis_info33 = {
722 .flags = ATA_FLAG_SLAVE_POSS,
723 .pio_mask = 0x1f, /* pio0-4 */
725 .udma_mask = ATA_UDMA2, /* UDMA 33 */
726 .port_ops = &sis_old_ops,
728 static const struct ata_port_info sis_info66 = {
730 .flags = ATA_FLAG_SLAVE_POSS,
731 .pio_mask = 0x1f, /* pio0-4 */
732 .udma_mask = ATA_UDMA4, /* UDMA 66 */
733 .port_ops = &sis_66_ops,
735 static const struct ata_port_info sis_info100 = {
737 .flags = ATA_FLAG_SLAVE_POSS,
738 .pio_mask = 0x1f, /* pio0-4 */
739 .udma_mask = ATA_UDMA5,
740 .port_ops = &sis_100_ops,
742 static const struct ata_port_info sis_info100_early = {
744 .flags = ATA_FLAG_SLAVE_POSS,
745 .udma_mask = ATA_UDMA5,
746 .pio_mask = 0x1f, /* pio0-4 */
747 .port_ops = &sis_66_ops,
749 static const struct ata_port_info sis_info133 = {
751 .flags = ATA_FLAG_SLAVE_POSS,
752 .pio_mask = 0x1f, /* pio0-4 */
753 .udma_mask = ATA_UDMA6,
754 .port_ops = &sis_133_ops,
756 const struct ata_port_info sis_info133_for_sata = {
758 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
759 .pio_mask = 0x1f, /* pio0-4 */
760 .udma_mask = ATA_UDMA6,
761 .port_ops = &sis_133_for_sata_ops,
763 static const struct ata_port_info sis_info133_early = {
765 .flags = ATA_FLAG_SLAVE_POSS,
766 .pio_mask = 0x1f, /* pio0-4 */
767 .udma_mask = ATA_UDMA6,
768 .port_ops = &sis_133_early_ops,
771 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
772 EXPORT_SYMBOL_GPL(sis_info133_for_sata);
774 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
779 if (sis->info == &sis_info133) {
780 pci_read_config_word(pdev, 0x50, ®w);
782 pci_write_config_word(pdev, 0x50, regw & ~0x08);
783 pci_read_config_word(pdev, 0x52, ®w);
785 pci_write_config_word(pdev, 0x52, regw & ~0x08);
789 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
791 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
792 /* Set compatibility bit */
793 pci_read_config_byte(pdev, 0x49, ®);
795 pci_write_config_byte(pdev, 0x49, reg | 0x01);
799 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
801 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
802 /* Set compatibility bit */
803 pci_read_config_byte(pdev, 0x52, ®);
805 pci_write_config_byte(pdev, 0x52, reg | 0x04);
809 if (sis->info == &sis_info33) {
810 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®);
811 if (( reg & 0x0F ) != 0x00)
812 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
813 /* Fall through to ATA16 fixup below */
816 if (sis->info == &sis_info || sis->info == &sis_info33) {
817 /* force per drive recovery and active timings
818 needed on ATA_33 and below chips */
819 pci_read_config_byte(pdev, 0x52, ®);
821 pci_write_config_byte(pdev, 0x52, reg|0x08);
829 * sis_init_one - Register SiS ATA PCI device with kernel services
830 * @pdev: PCI device to register
831 * @ent: Entry in sis_pci_tbl matching with @pdev
833 * Called from kernel PCI layer. We probe for combined mode (sigh),
834 * and then hand over control to libata, for it to do the rest.
837 * Inherited from PCI layer (may sleep).
840 * Zero on success, or -ERRNO value.
843 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
845 static int printed_version;
846 struct ata_port_info port;
847 const struct ata_port_info *ppi[] = { &port, NULL };
848 struct pci_dev *host = NULL;
849 struct sis_chipset *chipset = NULL;
850 struct sis_chipset *sets;
853 static struct sis_chipset sis_chipsets[] = {
855 { 0x0968, &sis_info133 },
856 { 0x0966, &sis_info133 },
857 { 0x0965, &sis_info133 },
858 { 0x0745, &sis_info100 },
859 { 0x0735, &sis_info100 },
860 { 0x0733, &sis_info100 },
861 { 0x0635, &sis_info100 },
862 { 0x0633, &sis_info100 },
864 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
865 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
867 { 0x0640, &sis_info66 },
868 { 0x0630, &sis_info66 },
869 { 0x0620, &sis_info66 },
870 { 0x0540, &sis_info66 },
871 { 0x0530, &sis_info66 },
873 { 0x5600, &sis_info33 },
874 { 0x5598, &sis_info33 },
875 { 0x5597, &sis_info33 },
876 { 0x5591, &sis_info33 },
877 { 0x5582, &sis_info33 },
878 { 0x5581, &sis_info33 },
880 { 0x5596, &sis_info },
881 { 0x5571, &sis_info },
882 { 0x5517, &sis_info },
883 { 0x5511, &sis_info },
887 static struct sis_chipset sis133_early = {
888 0x0, &sis_info133_early
890 static struct sis_chipset sis133 = {
893 static struct sis_chipset sis100_early = {
894 0x0, &sis_info100_early
896 static struct sis_chipset sis100 = {
900 if (!printed_version++)
901 dev_printk(KERN_DEBUG, &pdev->dev,
902 "version " DRV_VERSION "\n");
904 rc = pcim_enable_device(pdev);
908 /* We have to find the bridge first */
909 for (sets = &sis_chipsets[0]; sets->device; sets++) {
910 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
912 chipset = sets; /* Match found */
913 if (sets->device == 0x630) { /* SIS630 */
914 if (host->revision >= 0x30) /* 630 ET */
915 chipset = &sis100_early;
921 /* Look for concealed bridges */
922 if (chipset == NULL) {
927 /* Disable ID masking and register remapping then
928 see what the real ID is */
930 pci_read_config_dword(pdev, 0x54, &idemisc);
931 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
932 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
933 pci_write_config_dword(pdev, 0x54, idemisc);
936 case 0x5518: /* SIS 962/963 */
938 if ((idemisc & 0x40000000) == 0) {
939 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
940 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
943 case 0x0180: /* SIS 965/965L */
946 case 0x1180: /* SIS 966/966L */
953 if (chipset == NULL) {
954 struct pci_dev *lpc_bridge;
959 /* Try the second unmasking technique */
960 pci_read_config_byte(pdev, 0x4a, &idecfg);
961 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
962 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
963 pci_write_config_byte(pdev, 0x4a, idecfg);
967 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
968 if (lpc_bridge == NULL)
970 pci_read_config_byte(pdev, 0x49, &prefctl);
971 pci_dev_put(lpc_bridge);
973 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
974 chipset = &sis133_early;
983 /* No chipset info, no support */
987 port = *chipset->info;
988 port.private_data = chipset;
990 sis_fixup(pdev, chipset);
992 return ata_pci_init_one(pdev, ppi);
995 static const struct pci_device_id sis_pci_tbl[] = {
996 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
997 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
998 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
1003 static struct pci_driver sis_pci_driver = {
1005 .id_table = sis_pci_tbl,
1006 .probe = sis_init_one,
1007 .remove = ata_pci_remove_one,
1009 .suspend = ata_pci_device_suspend,
1010 .resume = ata_pci_device_resume,
1014 static int __init sis_init(void)
1016 return pci_register_driver(&sis_pci_driver);
1019 static void __exit sis_exit(void)
1021 pci_unregister_driver(&sis_pci_driver);
1024 module_init(sis_init);
1025 module_exit(sis_exit);
1027 MODULE_AUTHOR("Alan Cox");
1028 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1029 MODULE_LICENSE("GPL");
1030 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1031 MODULE_VERSION(DRV_VERSION);