2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
7 * This file is released under GPL v2.
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
19 * - Both STR and STD work.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.3"
39 IDMA_CPB_TBL_SIZE = 4 * 32,
41 INIC_DMA_BOUNDARY = 0xffffff,
51 /* registers for ATA TF operation */
53 PORT_TF_FEATURE = 0x01,
58 PORT_TF_DEVICE = 0x06,
59 PORT_TF_COMMAND = 0x07,
60 PORT_TF_ALT_STAT = 0x08,
65 PORT_PRD_XFERLEN = 0x10,
66 PORT_CPB_CPBLAR = 0x18,
67 PORT_CPB_PTQFIFO = 0x1c,
71 PORT_IDMA_STAT = 0x16,
79 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
80 HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
81 HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
82 HCTL_PWRDWN = (1 << 12), /* power down PHYs */
83 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
84 HCTL_RPGSEL = (1 << 15), /* register page select */
86 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
89 /* HOST_IRQ_(STAT|MASK) bits */
90 HIRQ_PORT0 = (1 << 0),
91 HIRQ_PORT1 = (1 << 1),
92 HIRQ_SOFT = (1 << 14),
93 HIRQ_GLOBAL = (1 << 15), /* STAT only */
95 /* PORT_IRQ_(STAT|MASK) bits */
96 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
97 PIRQ_ONLINE = (1 << 1), /* device plugged */
98 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
99 PIRQ_FATAL = (1 << 3), /* fatal error */
100 PIRQ_ATA = (1 << 4), /* ATA interrupt */
101 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
102 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
104 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
105 PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
106 PIRQ_MASK_FREEZE = 0xff,
108 /* PORT_PRD_CTL bits */
109 PRD_CTL_START = (1 << 0),
110 PRD_CTL_WR = (1 << 3),
111 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
113 /* PORT_IDMA_CTL bits */
114 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
115 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
116 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
117 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
119 /* PORT_IDMA_STAT bits */
120 IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
121 IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
122 IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
123 IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
124 IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
125 IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
126 IDMA_STAT_DONE = (1 << 7), /* ADMA done */
128 IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
130 /* CPB Control Flags*/
131 CPB_CTL_VALID = (1 << 0), /* CPB valid */
132 CPB_CTL_QUEUED = (1 << 1), /* queued command */
133 CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
134 CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
135 CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
137 /* CPB Response Flags */
138 CPB_RESP_DONE = (1 << 0), /* ATA command complete */
139 CPB_RESP_REL = (1 << 1), /* ATA release */
140 CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
141 CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
142 CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
143 CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
144 CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
145 CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
147 /* PRD Control Flags */
148 PRD_DRAIN = (1 << 1), /* ignore data excess */
149 PRD_CDB = (1 << 2), /* atapi packet command pointer */
150 PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
151 PRD_DMA = (1 << 4), /* data transfer method */
152 PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
153 PRD_IOM = (1 << 6), /* io/memory transfer */
154 PRD_END = (1 << 7), /* APRD chain end */
157 /* Comman Parameter Block */
159 u8 resp_flags; /* Response Flags */
160 u8 error; /* ATA Error */
161 u8 status; /* ATA Status */
162 u8 ctl_flags; /* Control Flags */
163 __le32 len; /* Total Transfer Length */
164 __le32 prd; /* First PRD pointer */
167 u8 feature; /* ATA Feature */
168 u8 hob_feature; /* ATA Ex. Feature */
169 u8 device; /* ATA Device/Head */
170 u8 mirctl; /* Mirror Control */
171 u8 nsect; /* ATA Sector Count */
172 u8 hob_nsect; /* ATA Ex. Sector Count */
173 u8 lbal; /* ATA Sector Number */
174 u8 hob_lbal; /* ATA Ex. Sector Number */
175 u8 lbam; /* ATA Cylinder Low */
176 u8 hob_lbam; /* ATA Ex. Cylinder Low */
177 u8 lbah; /* ATA Cylinder High */
178 u8 hob_lbah; /* ATA Ex. Cylinder High */
179 u8 command; /* ATA Command */
180 u8 ctl; /* ATA Control */
181 u8 slave_error; /* Slave ATA Error */
182 u8 slave_status; /* Slave ATA Status */
186 /* Physical Region Descriptor */
188 __le32 mad; /* Physical Memory Address */
189 __le16 len; /* Transfer Length */
191 u8 flags; /* Control Flags */
196 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
197 u8 cdb[ATAPI_CDB_LEN];
200 struct inic_host_priv {
201 void __iomem *mmio_base;
205 struct inic_port_priv {
206 struct inic_pkt *pkt;
209 dma_addr_t cpb_tbl_dma;
212 static struct scsi_host_template inic_sht = {
213 ATA_BASE_SHT(DRV_NAME),
214 .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
215 .dma_boundary = INIC_DMA_BOUNDARY,
218 static const int scr_map[] = {
224 static void __iomem *inic_port_base(struct ata_port *ap)
226 struct inic_host_priv *hpriv = ap->host->private_data;
228 return hpriv->mmio_base + ap->port_no * PORT_SIZE;
231 static void inic_reset_port(void __iomem *port_base)
233 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
235 /* stop IDMA engine */
236 readw(idma_ctl); /* flush */
239 /* mask IRQ and assert reset */
240 writew(IDMA_CTL_RST_IDMA, idma_ctl);
241 readw(idma_ctl); /* flush */
248 writeb(0xff, port_base + PORT_IRQ_STAT);
251 static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
253 void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
256 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
259 addr = scr_addr + scr_map[sc_reg] * 4;
260 *val = readl(scr_addr + scr_map[sc_reg] * 4);
262 /* this controller has stuck DIAG.N, ignore it */
263 if (sc_reg == SCR_ERROR)
264 *val &= ~SERR_PHYRDY_CHG;
268 static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
270 void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
272 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
275 writel(val, scr_addr + scr_map[sc_reg] * 4);
279 static void inic_stop_idma(struct ata_port *ap)
281 void __iomem *port_base = inic_port_base(ap);
283 readb(port_base + PORT_RPQ_FIFO);
284 readb(port_base + PORT_RPQ_CNT);
285 writew(0, port_base + PORT_IDMA_CTL);
288 static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
290 struct ata_eh_info *ehi = &ap->link.eh_info;
291 struct inic_port_priv *pp = ap->private_data;
292 struct inic_cpb *cpb = &pp->pkt->cpb;
295 ata_ehi_clear_desc(ehi);
296 ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
297 irq_stat, idma_stat);
301 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
302 ata_ehi_push_desc(ehi, "hotplug");
303 ata_ehi_hotplugged(ehi);
307 if (idma_stat & IDMA_STAT_PERR) {
308 ata_ehi_push_desc(ehi, "PCI error");
312 if (idma_stat & IDMA_STAT_CPBERR) {
313 ata_ehi_push_desc(ehi, "CPB error");
315 if (cpb->resp_flags & CPB_RESP_IGNORED) {
316 __ata_ehi_push_desc(ehi, " ignored");
317 ehi->err_mask |= AC_ERR_INVALID;
321 if (cpb->resp_flags & CPB_RESP_ATA_ERR)
322 ehi->err_mask |= AC_ERR_DEV;
324 if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
325 __ata_ehi_push_desc(ehi, " spurious-intr");
326 ehi->err_mask |= AC_ERR_HSM;
330 if (cpb->resp_flags &
331 (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
332 __ata_ehi_push_desc(ehi, " data-over/underflow");
333 ehi->err_mask |= AC_ERR_HSM;
344 static void inic_host_intr(struct ata_port *ap)
346 void __iomem *port_base = inic_port_base(ap);
347 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
351 /* read and clear IRQ status */
352 irq_stat = readb(port_base + PORT_IRQ_STAT);
353 writeb(irq_stat, port_base + PORT_IRQ_STAT);
354 idma_stat = readw(port_base + PORT_IDMA_STAT);
356 if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
357 inic_host_err_intr(ap, irq_stat, idma_stat);
362 if (likely(idma_stat & IDMA_STAT_DONE)) {
365 /* Depending on circumstances, device error
366 * isn't reported by IDMA, check it explicitly.
368 if (unlikely(readb(port_base + PORT_TF_COMMAND) &
370 qc->err_mask |= AC_ERR_DEV;
377 ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: "
378 "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
379 qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
382 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
384 struct ata_host *host = dev_instance;
385 struct inic_host_priv *hpriv = host->private_data;
389 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
391 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
394 spin_lock(&host->lock);
396 for (i = 0; i < NR_PORTS; i++) {
397 struct ata_port *ap = host->ports[i];
399 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
402 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
407 dev_printk(KERN_ERR, host->dev, "interrupt "
408 "from disabled port %d (0x%x)\n",
413 spin_unlock(&host->lock);
416 return IRQ_RETVAL(handled);
419 static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
421 /* For some reason ATAPI_PROT_DMA doesn't work for some
422 * commands including writes and other misc ops. Use PIO
423 * protocol instead, which BTW is driven by the DMA engine
424 * anyway, so it shouldn't make much difference for native
427 if (atapi_cmd_type(qc->cdb[0]) == READ)
432 static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
434 struct scatterlist *sg;
438 if (qc->tf.flags & ATA_TFLAG_WRITE)
441 if (ata_is_dma(qc->tf.protocol))
444 for_each_sg(qc->sg, sg, qc->n_elem, si) {
445 prd->mad = cpu_to_le32(sg_dma_address(sg));
446 prd->len = cpu_to_le16(sg_dma_len(sg));
452 prd[-1].flags |= PRD_END;
455 static void inic_qc_prep(struct ata_queued_cmd *qc)
457 struct inic_port_priv *pp = qc->ap->private_data;
458 struct inic_pkt *pkt = pp->pkt;
459 struct inic_cpb *cpb = &pkt->cpb;
460 struct inic_prd *prd = pkt->prd;
461 bool is_atapi = ata_is_atapi(qc->tf.protocol);
462 bool is_data = ata_is_data(qc->tf.protocol);
463 unsigned int cdb_len = 0;
468 cdb_len = qc->dev->cdb_len;
470 /* prepare packet, based on initio driver */
471 memset(pkt, 0, sizeof(struct inic_pkt));
473 cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
474 if (is_atapi || is_data)
475 cpb->ctl_flags |= CPB_CTL_DATA;
477 cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
478 cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
480 cpb->device = qc->tf.device;
481 cpb->feature = qc->tf.feature;
482 cpb->nsect = qc->tf.nsect;
483 cpb->lbal = qc->tf.lbal;
484 cpb->lbam = qc->tf.lbam;
485 cpb->lbah = qc->tf.lbah;
487 if (qc->tf.flags & ATA_TFLAG_LBA48) {
488 cpb->hob_feature = qc->tf.hob_feature;
489 cpb->hob_nsect = qc->tf.hob_nsect;
490 cpb->hob_lbal = qc->tf.hob_lbal;
491 cpb->hob_lbam = qc->tf.hob_lbam;
492 cpb->hob_lbah = qc->tf.hob_lbah;
495 cpb->command = qc->tf.command;
496 /* don't load ctl - dunno why. it's like that in the initio driver */
498 /* setup PRD for CDB */
500 memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
501 prd->mad = cpu_to_le32(pp->pkt_dma +
502 offsetof(struct inic_pkt, cdb));
503 prd->len = cpu_to_le16(cdb_len);
504 prd->flags = PRD_CDB | PRD_WRITE;
506 prd->flags |= PRD_END;
512 inic_fill_sg(prd, qc);
514 pp->cpb_tbl[0] = pp->pkt_dma;
517 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
519 struct ata_port *ap = qc->ap;
520 void __iomem *port_base = inic_port_base(ap);
522 /* fire up the ADMA engine */
523 writew(HCTL_FTHD0, port_base + HOST_CTL);
524 writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
525 writeb(0, port_base + PORT_CPB_PTQFIFO);
530 static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
532 void __iomem *port_base = inic_port_base(ap);
534 tf->feature = readb(port_base + PORT_TF_FEATURE);
535 tf->nsect = readb(port_base + PORT_TF_NSECT);
536 tf->lbal = readb(port_base + PORT_TF_LBAL);
537 tf->lbam = readb(port_base + PORT_TF_LBAM);
538 tf->lbah = readb(port_base + PORT_TF_LBAH);
539 tf->device = readb(port_base + PORT_TF_DEVICE);
540 tf->command = readb(port_base + PORT_TF_COMMAND);
543 static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
545 struct ata_taskfile *rtf = &qc->result_tf;
546 struct ata_taskfile tf;
548 /* FIXME: Except for status and error, result TF access
549 * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
550 * None works regardless of which command interface is used.
551 * For now return true iff status indicates device error.
552 * This means that we're reporting bogus sector for RW
553 * failures. Eeekk....
555 inic_tf_read(qc->ap, &tf);
557 if (!(tf.command & ATA_ERR))
560 rtf->command = tf.command;
561 rtf->feature = tf.feature;
565 static void inic_freeze(struct ata_port *ap)
567 void __iomem *port_base = inic_port_base(ap);
569 writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
570 writeb(0xff, port_base + PORT_IRQ_STAT);
573 static void inic_thaw(struct ata_port *ap)
575 void __iomem *port_base = inic_port_base(ap);
577 writeb(0xff, port_base + PORT_IRQ_STAT);
578 writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
581 static int inic_check_ready(struct ata_link *link)
583 void __iomem *port_base = inic_port_base(link->ap);
585 return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
589 * SRST and SControl hardreset don't give valid signature on this
590 * controller. Only controller specific hardreset mechanism works.
592 static int inic_hardreset(struct ata_link *link, unsigned int *class,
593 unsigned long deadline)
595 struct ata_port *ap = link->ap;
596 void __iomem *port_base = inic_port_base(ap);
597 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
598 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
601 /* hammer it into sane state */
602 inic_reset_port(port_base);
604 writew(IDMA_CTL_RST_ATA, idma_ctl);
605 readw(idma_ctl); /* flush */
609 rc = sata_link_resume(link, timing, deadline);
611 ata_link_printk(link, KERN_WARNING, "failed to resume "
612 "link after reset (errno=%d)\n", rc);
616 *class = ATA_DEV_NONE;
617 if (ata_link_online(link)) {
618 struct ata_taskfile tf;
620 /* wait for link to become ready */
621 rc = ata_wait_after_reset(link, deadline, inic_check_ready);
622 /* link occupied, -ENODEV too is an error */
624 ata_link_printk(link, KERN_WARNING, "device not ready "
625 "after hardreset (errno=%d)\n", rc);
629 inic_tf_read(ap, &tf);
630 *class = ata_dev_classify(&tf);
636 static void inic_error_handler(struct ata_port *ap)
638 void __iomem *port_base = inic_port_base(ap);
640 inic_reset_port(port_base);
641 ata_std_error_handler(ap);
644 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
646 /* make DMA engine forget about the failed command */
647 if (qc->flags & ATA_QCFLAG_FAILED)
648 inic_reset_port(inic_port_base(qc->ap));
651 static void init_port(struct ata_port *ap)
653 void __iomem *port_base = inic_port_base(ap);
654 struct inic_port_priv *pp = ap->private_data;
656 /* clear packet and CPB table */
657 memset(pp->pkt, 0, sizeof(struct inic_pkt));
658 memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
660 /* setup PRD and CPB lookup table addresses */
661 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
662 writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
665 static int inic_port_resume(struct ata_port *ap)
671 static int inic_port_start(struct ata_port *ap)
673 struct device *dev = ap->host->dev;
674 struct inic_port_priv *pp;
677 /* alloc and initialize private data */
678 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
681 ap->private_data = pp;
683 /* Alloc resources */
684 rc = ata_port_start(ap);
688 pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
689 &pp->pkt_dma, GFP_KERNEL);
693 pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
694 &pp->cpb_tbl_dma, GFP_KERNEL);
703 static struct ata_port_operations inic_port_ops = {
704 .inherits = &sata_port_ops,
706 .check_atapi_dma = inic_check_atapi_dma,
707 .qc_prep = inic_qc_prep,
708 .qc_issue = inic_qc_issue,
709 .qc_fill_rtf = inic_qc_fill_rtf,
711 .freeze = inic_freeze,
713 .hardreset = inic_hardreset,
714 .error_handler = inic_error_handler,
715 .post_internal_cmd = inic_post_internal_cmd,
717 .scr_read = inic_scr_read,
718 .scr_write = inic_scr_write,
720 .port_resume = inic_port_resume,
721 .port_start = inic_port_start,
724 static struct ata_port_info inic_port_info = {
725 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
726 .pio_mask = 0x1f, /* pio0-4 */
727 .mwdma_mask = 0x07, /* mwdma0-2 */
728 .udma_mask = ATA_UDMA6,
729 .port_ops = &inic_port_ops
732 static int init_controller(void __iomem *mmio_base, u16 hctl)
737 hctl &= ~HCTL_KNOWN_BITS;
739 /* Soft reset whole controller. Spec says reset duration is 3
740 * PCI clocks, be generous and give it 10ms.
742 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
743 readw(mmio_base + HOST_CTL); /* flush */
745 for (i = 0; i < 10; i++) {
747 val = readw(mmio_base + HOST_CTL);
748 if (!(val & HCTL_SOFTRST))
752 if (val & HCTL_SOFTRST)
755 /* mask all interrupts and reset ports */
756 for (i = 0; i < NR_PORTS; i++) {
757 void __iomem *port_base = mmio_base + i * PORT_SIZE;
759 writeb(0xff, port_base + PORT_IRQ_MASK);
760 inic_reset_port(port_base);
763 /* port IRQ is masked now, unmask global IRQ */
764 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
765 val = readw(mmio_base + HOST_IRQ_MASK);
766 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
767 writew(val, mmio_base + HOST_IRQ_MASK);
773 static int inic_pci_device_resume(struct pci_dev *pdev)
775 struct ata_host *host = dev_get_drvdata(&pdev->dev);
776 struct inic_host_priv *hpriv = host->private_data;
779 rc = ata_pci_device_do_resume(pdev);
783 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
784 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
789 ata_host_resume(host);
795 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
797 static int printed_version;
798 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
799 struct ata_host *host;
800 struct inic_host_priv *hpriv;
801 void __iomem * const *iomap;
805 if (!printed_version++)
806 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
809 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
810 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
814 host->private_data = hpriv;
816 /* Acquire resources and fill host. Note that PCI and cardbus
817 * use different BARs.
819 rc = pcim_enable_device(pdev);
823 if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
824 mmio_bar = MMIO_BAR_PCI;
826 mmio_bar = MMIO_BAR_CARDBUS;
828 rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
831 host->iomap = iomap = pcim_iomap_table(pdev);
832 hpriv->mmio_base = iomap[mmio_bar];
833 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
835 for (i = 0; i < NR_PORTS; i++) {
836 struct ata_port *ap = host->ports[i];
838 ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
839 ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
842 /* Set dma_mask. This devices doesn't support 64bit addressing. */
843 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
845 dev_printk(KERN_ERR, &pdev->dev,
846 "32-bit DMA enable failed\n");
850 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
852 dev_printk(KERN_ERR, &pdev->dev,
853 "32-bit consistent DMA enable failed\n");
858 * This controller is braindamaged. dma_boundary is 0xffff
859 * like others but it will lock up the whole machine HARD if
860 * 65536 byte PRD entry is fed. Reduce maximum segment size.
862 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
864 dev_printk(KERN_ERR, &pdev->dev,
865 "failed to set the maximum segment size.\n");
869 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
871 dev_printk(KERN_ERR, &pdev->dev,
872 "failed to initialize controller\n");
876 pci_set_master(pdev);
877 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
881 static const struct pci_device_id inic_pci_tbl[] = {
882 { PCI_VDEVICE(INIT, 0x1622), },
886 static struct pci_driver inic_pci_driver = {
888 .id_table = inic_pci_tbl,
890 .suspend = ata_pci_device_suspend,
891 .resume = inic_pci_device_resume,
893 .probe = inic_init_one,
894 .remove = ata_pci_remove_one,
897 static int __init inic_init(void)
899 return pci_register_driver(&inic_pci_driver);
902 static void __exit inic_exit(void)
904 pci_unregister_driver(&inic_pci_driver);
907 MODULE_AUTHOR("Tejun Heo");
908 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
909 MODULE_LICENSE("GPL v2");
910 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
911 MODULE_VERSION(DRV_VERSION);
913 module_init(inic_init);
914 module_exit(inic_exit);