2 * Register cache access API
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/device.h>
16 #include <trace/events/regmap.h>
17 #include <linux/bsearch.h>
18 #include <linux/sort.h>
22 static const struct regcache_ops *cache_types[] = {
28 static int regcache_hw_init(struct regmap *map)
36 if (!map->num_reg_defaults_raw)
39 if (!map->reg_defaults_raw) {
40 u32 cache_bypass = map->cache_bypass;
41 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
43 /* Bypass the cache access till data read from HW*/
44 map->cache_bypass = 1;
45 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
48 ret = regmap_raw_read(map, 0, tmp_buf,
49 map->num_reg_defaults_raw);
50 map->cache_bypass = cache_bypass;
55 map->reg_defaults_raw = tmp_buf;
59 /* calculate the size of reg_defaults */
60 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) {
61 val = regcache_get_val(map, map->reg_defaults_raw, i);
62 if (regmap_volatile(map, i * map->reg_stride))
67 map->reg_defaults = kmalloc(count * sizeof(struct reg_default),
69 if (!map->reg_defaults) {
74 /* fill the reg_defaults */
75 map->num_reg_defaults = count;
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 val = regcache_get_val(map, map->reg_defaults_raw, i);
78 if (regmap_volatile(map, i * map->reg_stride))
80 map->reg_defaults[j].reg = i * map->reg_stride;
81 map->reg_defaults[j].def = val;
89 kfree(map->reg_defaults_raw);
94 int regcache_init(struct regmap *map, const struct regmap_config *config)
100 for (i = 0; i < config->num_reg_defaults; i++)
101 if (config->reg_defaults[i].reg % map->reg_stride)
104 if (map->cache_type == REGCACHE_NONE) {
105 map->cache_bypass = true;
109 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
110 if (cache_types[i]->type == map->cache_type)
113 if (i == ARRAY_SIZE(cache_types)) {
114 dev_err(map->dev, "Could not match compress type: %d\n",
119 map->num_reg_defaults = config->num_reg_defaults;
120 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
121 map->reg_defaults_raw = config->reg_defaults_raw;
122 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
123 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
124 map->cache_present = NULL;
125 map->cache_present_nbits = 0;
128 map->cache_ops = cache_types[i];
130 if (!map->cache_ops->read ||
131 !map->cache_ops->write ||
132 !map->cache_ops->name)
135 /* We still need to ensure that the reg_defaults
136 * won't vanish from under us. We'll need to make
139 if (config->reg_defaults) {
140 if (!map->num_reg_defaults)
142 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
143 sizeof(struct reg_default), GFP_KERNEL);
146 map->reg_defaults = tmp_buf;
147 } else if (map->num_reg_defaults_raw) {
148 /* Some devices such as PMICs don't have cache defaults,
149 * we cope with this by reading back the HW registers and
150 * crafting the cache defaults by hand.
152 ret = regcache_hw_init(map);
157 if (!map->max_register)
158 map->max_register = map->num_reg_defaults_raw;
160 if (map->cache_ops->init) {
161 dev_dbg(map->dev, "Initializing %s cache\n",
162 map->cache_ops->name);
163 ret = map->cache_ops->init(map);
170 kfree(map->reg_defaults);
172 kfree(map->reg_defaults_raw);
177 void regcache_exit(struct regmap *map)
179 if (map->cache_type == REGCACHE_NONE)
182 BUG_ON(!map->cache_ops);
184 kfree(map->cache_present);
185 kfree(map->reg_defaults);
187 kfree(map->reg_defaults_raw);
189 if (map->cache_ops->exit) {
190 dev_dbg(map->dev, "Destroying %s cache\n",
191 map->cache_ops->name);
192 map->cache_ops->exit(map);
197 * regcache_read: Fetch the value of a given register from the cache.
199 * @map: map to configure.
200 * @reg: The register index.
201 * @value: The value to be returned.
203 * Return a negative value on failure, 0 on success.
205 int regcache_read(struct regmap *map,
206 unsigned int reg, unsigned int *value)
210 if (map->cache_type == REGCACHE_NONE)
213 BUG_ON(!map->cache_ops);
215 if (!regmap_volatile(map, reg)) {
216 ret = map->cache_ops->read(map, reg, value);
219 trace_regmap_reg_read_cache(map->dev, reg, *value);
228 * regcache_write: Set the value of a given register in the cache.
230 * @map: map to configure.
231 * @reg: The register index.
232 * @value: The new register value.
234 * Return a negative value on failure, 0 on success.
236 int regcache_write(struct regmap *map,
237 unsigned int reg, unsigned int value)
239 if (map->cache_type == REGCACHE_NONE)
242 BUG_ON(!map->cache_ops);
244 if (!regmap_writeable(map, reg))
247 if (!regmap_volatile(map, reg))
248 return map->cache_ops->write(map, reg, value);
254 * regcache_sync: Sync the register cache with the hardware.
256 * @map: map to configure.
258 * Any registers that should not be synced should be marked as
259 * volatile. In general drivers can choose not to use the provided
260 * syncing functionality if they so require.
262 * Return a negative value on failure, 0 on success.
264 int regcache_sync(struct regmap *map)
271 BUG_ON(!map->cache_ops || !map->cache_ops->sync);
273 map->lock(map->lock_arg);
274 /* Remember the initial bypass state */
275 bypass = map->cache_bypass;
276 dev_dbg(map->dev, "Syncing %s cache\n",
277 map->cache_ops->name);
278 name = map->cache_ops->name;
279 trace_regcache_sync(map->dev, name, "start");
281 if (!map->cache_dirty)
284 /* Apply any patch first */
285 map->cache_bypass = 1;
286 for (i = 0; i < map->patch_regs; i++) {
287 if (map->patch[i].reg % map->reg_stride) {
291 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
293 dev_err(map->dev, "Failed to write %x = %x: %d\n",
294 map->patch[i].reg, map->patch[i].def, ret);
298 map->cache_bypass = 0;
300 ret = map->cache_ops->sync(map, 0, map->max_register);
303 map->cache_dirty = false;
306 trace_regcache_sync(map->dev, name, "stop");
307 /* Restore the bypass state */
308 map->cache_bypass = bypass;
309 map->unlock(map->lock_arg);
313 EXPORT_SYMBOL_GPL(regcache_sync);
316 * regcache_sync_region: Sync part of the register cache with the hardware.
319 * @min: first register to sync
320 * @max: last register to sync
322 * Write all non-default register values in the specified region to
325 * Return a negative value on failure, 0 on success.
327 int regcache_sync_region(struct regmap *map, unsigned int min,
334 BUG_ON(!map->cache_ops || !map->cache_ops->sync);
336 map->lock(map->lock_arg);
338 /* Remember the initial bypass state */
339 bypass = map->cache_bypass;
341 name = map->cache_ops->name;
342 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
344 trace_regcache_sync(map->dev, name, "start region");
346 if (!map->cache_dirty)
349 ret = map->cache_ops->sync(map, min, max);
352 trace_regcache_sync(map->dev, name, "stop region");
353 /* Restore the bypass state */
354 map->cache_bypass = bypass;
355 map->unlock(map->lock_arg);
359 EXPORT_SYMBOL_GPL(regcache_sync_region);
362 * regcache_cache_only: Put a register map into cache only mode
364 * @map: map to configure
365 * @cache_only: flag if changes should be written to the hardware
367 * When a register map is marked as cache only writes to the register
368 * map API will only update the register cache, they will not cause
369 * any hardware changes. This is useful for allowing portions of
370 * drivers to act as though the device were functioning as normal when
371 * it is disabled for power saving reasons.
373 void regcache_cache_only(struct regmap *map, bool enable)
375 map->lock(map->lock_arg);
376 WARN_ON(map->cache_bypass && enable);
377 map->cache_only = enable;
378 trace_regmap_cache_only(map->dev, enable);
379 map->unlock(map->lock_arg);
381 EXPORT_SYMBOL_GPL(regcache_cache_only);
384 * regcache_mark_dirty: Mark the register cache as dirty
388 * Mark the register cache as dirty, for example due to the device
389 * having been powered down for suspend. If the cache is not marked
390 * as dirty then the cache sync will be suppressed.
392 void regcache_mark_dirty(struct regmap *map)
394 map->lock(map->lock_arg);
395 map->cache_dirty = true;
396 map->unlock(map->lock_arg);
398 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
401 * regcache_cache_bypass: Put a register map into cache bypass mode
403 * @map: map to configure
404 * @cache_bypass: flag if changes should not be written to the hardware
406 * When a register map is marked with the cache bypass option, writes
407 * to the register map API will only update the hardware and not the
408 * the cache directly. This is useful when syncing the cache back to
411 void regcache_cache_bypass(struct regmap *map, bool enable)
413 map->lock(map->lock_arg);
414 WARN_ON(map->cache_only && enable);
415 map->cache_bypass = enable;
416 trace_regmap_cache_bypass(map->dev, enable);
417 map->unlock(map->lock_arg);
419 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
421 int regcache_set_reg_present(struct regmap *map, unsigned int reg)
423 unsigned long *cache_present;
424 unsigned int cache_present_size;
429 cache_present_size = BITS_TO_LONGS(nregs);
430 cache_present_size *= sizeof(long);
432 if (!map->cache_present) {
433 cache_present = kmalloc(cache_present_size, GFP_KERNEL);
436 bitmap_zero(cache_present, nregs);
437 map->cache_present = cache_present;
438 map->cache_present_nbits = nregs;
441 if (nregs > map->cache_present_nbits) {
442 cache_present = krealloc(map->cache_present,
443 cache_present_size, GFP_KERNEL);
446 for (i = 0; i < nregs; i++)
447 if (i >= map->cache_present_nbits)
448 clear_bit(i, cache_present);
449 map->cache_present = cache_present;
450 map->cache_present_nbits = nregs;
453 set_bit(reg, map->cache_present);
457 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
460 if (regcache_get_val(map, base, idx) == val)
463 /* Use device native format if possible */
464 if (map->format.format_val) {
465 map->format.format_val(base + (map->cache_word_size * idx),
470 switch (map->cache_word_size) {
492 unsigned int regcache_get_val(struct regmap *map, const void *base,
498 /* Use device native format if possible */
499 if (map->format.parse_val)
500 return map->format.parse_val(regcache_get_val_addr(map, base,
503 switch (map->cache_word_size) {
505 const u8 *cache = base;
509 const u16 *cache = base;
513 const u32 *cache = base;
523 static int regcache_default_cmp(const void *a, const void *b)
525 const struct reg_default *_a = a;
526 const struct reg_default *_b = b;
528 return _a->reg - _b->reg;
531 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
533 struct reg_default key;
534 struct reg_default *r;
539 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
540 sizeof(struct reg_default), regcache_default_cmp);
543 return r - map->reg_defaults;
548 static int regcache_sync_block_single(struct regmap *map, void *block,
549 unsigned int block_base,
550 unsigned int start, unsigned int end)
552 unsigned int i, regtmp, val;
555 for (i = start; i < end; i++) {
556 regtmp = block_base + (i * map->reg_stride);
558 if (!regcache_reg_present(map, regtmp))
561 val = regcache_get_val(map, block, i);
563 /* Is this the hardware default? If so skip. */
564 ret = regcache_lookup_reg(map, regtmp);
565 if (ret >= 0 && val == map->reg_defaults[ret].def)
568 map->cache_bypass = 1;
570 ret = _regmap_write(map, regtmp, val);
572 map->cache_bypass = 0;
575 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
582 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
583 unsigned int base, unsigned int cur)
585 size_t val_bytes = map->format.val_bytes;
593 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
594 count * val_bytes, count, base, cur - 1);
596 map->cache_bypass = 1;
598 ret = _regmap_raw_write(map, base, *data, count * val_bytes,
601 map->cache_bypass = 0;
608 static int regcache_sync_block_raw(struct regmap *map, void *block,
609 unsigned int block_base, unsigned int start,
613 unsigned int regtmp = 0;
614 unsigned int base = 0;
615 const void *data = NULL;
618 for (i = start; i < end; i++) {
619 regtmp = block_base + (i * map->reg_stride);
621 if (!regcache_reg_present(map, regtmp)) {
622 ret = regcache_sync_block_raw_flush(map, &data,
629 val = regcache_get_val(map, block, i);
631 /* Is this the hardware default? If so skip. */
632 ret = regcache_lookup_reg(map, regtmp);
633 if (ret >= 0 && val == map->reg_defaults[ret].def) {
634 ret = regcache_sync_block_raw_flush(map, &data,
642 data = regcache_get_val_addr(map, block, i);
647 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
651 int regcache_sync_block(struct regmap *map, void *block,
652 unsigned int block_base, unsigned int start,
655 if (regmap_can_raw_write(map))
656 return regcache_sync_block_raw(map, block, block_base,
659 return regcache_sync_block_single(map, block, block_base,