2 * Register cache access API
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/device.h>
16 #include <trace/events/regmap.h>
17 #include <linux/bsearch.h>
18 #include <linux/sort.h>
22 static const struct regcache_ops *cache_types[] = {
28 static int regcache_hw_init(struct regmap *map)
36 if (!map->num_reg_defaults_raw)
39 if (!map->reg_defaults_raw) {
40 u32 cache_bypass = map->cache_bypass;
41 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
43 /* Bypass the cache access till data read from HW*/
44 map->cache_bypass = 1;
45 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
48 ret = regmap_raw_read(map, 0, tmp_buf,
49 map->num_reg_defaults_raw);
50 map->cache_bypass = cache_bypass;
55 map->reg_defaults_raw = tmp_buf;
59 /* calculate the size of reg_defaults */
60 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
61 if (!regmap_volatile(map, i * map->reg_stride))
64 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
66 if (!map->reg_defaults) {
71 /* fill the reg_defaults */
72 map->num_reg_defaults = count;
73 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
74 if (regmap_volatile(map, i * map->reg_stride))
76 val = regcache_get_val(map, map->reg_defaults_raw, i);
77 map->reg_defaults[j].reg = i * map->reg_stride;
78 map->reg_defaults[j].def = val;
86 kfree(map->reg_defaults_raw);
91 int regcache_init(struct regmap *map, const struct regmap_config *config)
97 for (i = 0; i < config->num_reg_defaults; i++)
98 if (config->reg_defaults[i].reg % map->reg_stride)
101 if (map->cache_type == REGCACHE_NONE) {
102 map->cache_bypass = true;
106 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
107 if (cache_types[i]->type == map->cache_type)
110 if (i == ARRAY_SIZE(cache_types)) {
111 dev_err(map->dev, "Could not match compress type: %d\n",
116 map->num_reg_defaults = config->num_reg_defaults;
117 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
118 map->reg_defaults_raw = config->reg_defaults_raw;
119 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
120 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
123 map->cache_ops = cache_types[i];
125 if (!map->cache_ops->read ||
126 !map->cache_ops->write ||
127 !map->cache_ops->name)
130 /* We still need to ensure that the reg_defaults
131 * won't vanish from under us. We'll need to make
134 if (config->reg_defaults) {
135 if (!map->num_reg_defaults)
137 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
138 sizeof(struct reg_default), GFP_KERNEL);
141 map->reg_defaults = tmp_buf;
142 } else if (map->num_reg_defaults_raw) {
143 /* Some devices such as PMICs don't have cache defaults,
144 * we cope with this by reading back the HW registers and
145 * crafting the cache defaults by hand.
147 ret = regcache_hw_init(map);
152 if (!map->max_register)
153 map->max_register = map->num_reg_defaults_raw;
155 if (map->cache_ops->init) {
156 dev_dbg(map->dev, "Initializing %s cache\n",
157 map->cache_ops->name);
158 ret = map->cache_ops->init(map);
165 kfree(map->reg_defaults);
167 kfree(map->reg_defaults_raw);
172 void regcache_exit(struct regmap *map)
174 if (map->cache_type == REGCACHE_NONE)
177 BUG_ON(!map->cache_ops);
179 kfree(map->reg_defaults);
181 kfree(map->reg_defaults_raw);
183 if (map->cache_ops->exit) {
184 dev_dbg(map->dev, "Destroying %s cache\n",
185 map->cache_ops->name);
186 map->cache_ops->exit(map);
191 * regcache_read: Fetch the value of a given register from the cache.
193 * @map: map to configure.
194 * @reg: The register index.
195 * @value: The value to be returned.
197 * Return a negative value on failure, 0 on success.
199 int regcache_read(struct regmap *map,
200 unsigned int reg, unsigned int *value)
204 if (map->cache_type == REGCACHE_NONE)
207 BUG_ON(!map->cache_ops);
209 if (!regmap_volatile(map, reg)) {
210 ret = map->cache_ops->read(map, reg, value);
213 trace_regmap_reg_read_cache(map->dev, reg, *value);
222 * regcache_write: Set the value of a given register in the cache.
224 * @map: map to configure.
225 * @reg: The register index.
226 * @value: The new register value.
228 * Return a negative value on failure, 0 on success.
230 int regcache_write(struct regmap *map,
231 unsigned int reg, unsigned int value)
233 if (map->cache_type == REGCACHE_NONE)
236 BUG_ON(!map->cache_ops);
238 if (!regmap_volatile(map, reg))
239 return map->cache_ops->write(map, reg, value);
244 static int regcache_default_sync(struct regmap *map, unsigned int min,
249 for (reg = min; reg <= max; reg += map->reg_stride) {
253 if (regmap_volatile(map, reg) ||
254 !regmap_writeable(map, reg))
257 ret = regcache_read(map, reg, &val);
261 /* Is this the hardware default? If so skip. */
262 ret = regcache_lookup_reg(map, reg);
263 if (ret >= 0 && val == map->reg_defaults[ret].def)
266 map->cache_bypass = 1;
267 ret = _regmap_write(map, reg, val);
268 map->cache_bypass = 0;
270 dev_err(map->dev, "Unable to sync register %#x. %d\n",
274 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
281 * regcache_sync: Sync the register cache with the hardware.
283 * @map: map to configure.
285 * Any registers that should not be synced should be marked as
286 * volatile. In general drivers can choose not to use the provided
287 * syncing functionality if they so require.
289 * Return a negative value on failure, 0 on success.
291 int regcache_sync(struct regmap *map)
298 BUG_ON(!map->cache_ops);
300 map->lock(map->lock_arg);
301 /* Remember the initial bypass state */
302 bypass = map->cache_bypass;
303 dev_dbg(map->dev, "Syncing %s cache\n",
304 map->cache_ops->name);
305 name = map->cache_ops->name;
306 trace_regcache_sync(map->dev, name, "start");
308 if (!map->cache_dirty)
313 /* Apply any patch first */
314 map->cache_bypass = 1;
315 for (i = 0; i < map->patch_regs; i++) {
316 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
318 dev_err(map->dev, "Failed to write %x = %x: %d\n",
319 map->patch[i].reg, map->patch[i].def, ret);
323 map->cache_bypass = 0;
325 if (map->cache_ops->sync)
326 ret = map->cache_ops->sync(map, 0, map->max_register);
328 ret = regcache_default_sync(map, 0, map->max_register);
331 map->cache_dirty = false;
334 /* Restore the bypass state */
336 map->cache_bypass = bypass;
337 map->unlock(map->lock_arg);
339 regmap_async_complete(map);
341 trace_regcache_sync(map->dev, name, "stop");
345 EXPORT_SYMBOL_GPL(regcache_sync);
348 * regcache_sync_region: Sync part of the register cache with the hardware.
351 * @min: first register to sync
352 * @max: last register to sync
354 * Write all non-default register values in the specified region to
357 * Return a negative value on failure, 0 on success.
359 int regcache_sync_region(struct regmap *map, unsigned int min,
366 BUG_ON(!map->cache_ops);
368 map->lock(map->lock_arg);
370 /* Remember the initial bypass state */
371 bypass = map->cache_bypass;
373 name = map->cache_ops->name;
374 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
376 trace_regcache_sync(map->dev, name, "start region");
378 if (!map->cache_dirty)
383 if (map->cache_ops->sync)
384 ret = map->cache_ops->sync(map, min, max);
386 ret = regcache_default_sync(map, min, max);
389 /* Restore the bypass state */
390 map->cache_bypass = bypass;
392 map->unlock(map->lock_arg);
394 regmap_async_complete(map);
396 trace_regcache_sync(map->dev, name, "stop region");
400 EXPORT_SYMBOL_GPL(regcache_sync_region);
403 * regcache_drop_region: Discard part of the register cache
405 * @map: map to operate on
406 * @min: first register to discard
407 * @max: last register to discard
409 * Discard part of the register cache.
411 * Return a negative value on failure, 0 on success.
413 int regcache_drop_region(struct regmap *map, unsigned int min,
418 if (!map->cache_ops || !map->cache_ops->drop)
421 map->lock(map->lock_arg);
423 trace_regcache_drop_region(map->dev, min, max);
425 ret = map->cache_ops->drop(map, min, max);
427 map->unlock(map->lock_arg);
431 EXPORT_SYMBOL_GPL(regcache_drop_region);
434 * regcache_cache_only: Put a register map into cache only mode
436 * @map: map to configure
437 * @cache_only: flag if changes should be written to the hardware
439 * When a register map is marked as cache only writes to the register
440 * map API will only update the register cache, they will not cause
441 * any hardware changes. This is useful for allowing portions of
442 * drivers to act as though the device were functioning as normal when
443 * it is disabled for power saving reasons.
445 void regcache_cache_only(struct regmap *map, bool enable)
447 map->lock(map->lock_arg);
448 WARN_ON(map->cache_bypass && enable);
449 map->cache_only = enable;
450 trace_regmap_cache_only(map->dev, enable);
451 map->unlock(map->lock_arg);
453 EXPORT_SYMBOL_GPL(regcache_cache_only);
456 * regcache_mark_dirty: Mark the register cache as dirty
460 * Mark the register cache as dirty, for example due to the device
461 * having been powered down for suspend. If the cache is not marked
462 * as dirty then the cache sync will be suppressed.
464 void regcache_mark_dirty(struct regmap *map)
466 map->lock(map->lock_arg);
467 map->cache_dirty = true;
468 map->unlock(map->lock_arg);
470 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
473 * regcache_cache_bypass: Put a register map into cache bypass mode
475 * @map: map to configure
476 * @cache_bypass: flag if changes should not be written to the hardware
478 * When a register map is marked with the cache bypass option, writes
479 * to the register map API will only update the hardware and not the
480 * the cache directly. This is useful when syncing the cache back to
483 void regcache_cache_bypass(struct regmap *map, bool enable)
485 map->lock(map->lock_arg);
486 WARN_ON(map->cache_only && enable);
487 map->cache_bypass = enable;
488 trace_regmap_cache_bypass(map->dev, enable);
489 map->unlock(map->lock_arg);
491 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
493 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
496 if (regcache_get_val(map, base, idx) == val)
499 /* Use device native format if possible */
500 if (map->format.format_val) {
501 map->format.format_val(base + (map->cache_word_size * idx),
506 switch (map->cache_word_size) {
528 unsigned int regcache_get_val(struct regmap *map, const void *base,
534 /* Use device native format if possible */
535 if (map->format.parse_val)
536 return map->format.parse_val(regcache_get_val_addr(map, base,
539 switch (map->cache_word_size) {
541 const u8 *cache = base;
545 const u16 *cache = base;
549 const u32 *cache = base;
559 static int regcache_default_cmp(const void *a, const void *b)
561 const struct reg_default *_a = a;
562 const struct reg_default *_b = b;
564 return _a->reg - _b->reg;
567 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
569 struct reg_default key;
570 struct reg_default *r;
575 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
576 sizeof(struct reg_default), regcache_default_cmp);
579 return r - map->reg_defaults;
584 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
589 return test_bit(idx, cache_present);
592 static int regcache_sync_block_single(struct regmap *map, void *block,
593 unsigned long *cache_present,
594 unsigned int block_base,
595 unsigned int start, unsigned int end)
597 unsigned int i, regtmp, val;
600 for (i = start; i < end; i++) {
601 regtmp = block_base + (i * map->reg_stride);
603 if (!regcache_reg_present(cache_present, i))
606 val = regcache_get_val(map, block, i);
608 /* Is this the hardware default? If so skip. */
609 ret = regcache_lookup_reg(map, regtmp);
610 if (ret >= 0 && val == map->reg_defaults[ret].def)
613 map->cache_bypass = 1;
615 ret = _regmap_write(map, regtmp, val);
617 map->cache_bypass = 0;
619 dev_err(map->dev, "Unable to sync register %#x. %d\n",
623 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
630 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
631 unsigned int base, unsigned int cur)
633 size_t val_bytes = map->format.val_bytes;
639 count = (cur - base) / map->reg_stride;
641 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
642 count * val_bytes, count, base, cur - map->reg_stride);
644 map->cache_bypass = 1;
646 ret = _regmap_raw_write(map, base, *data, count * val_bytes);
648 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
649 base, cur - map->reg_stride, ret);
651 map->cache_bypass = 0;
658 static int regcache_sync_block_raw(struct regmap *map, void *block,
659 unsigned long *cache_present,
660 unsigned int block_base, unsigned int start,
664 unsigned int regtmp = 0;
665 unsigned int base = 0;
666 const void *data = NULL;
669 for (i = start; i < end; i++) {
670 regtmp = block_base + (i * map->reg_stride);
672 if (!regcache_reg_present(cache_present, i)) {
673 ret = regcache_sync_block_raw_flush(map, &data,
680 val = regcache_get_val(map, block, i);
682 /* Is this the hardware default? If so skip. */
683 ret = regcache_lookup_reg(map, regtmp);
684 if (ret >= 0 && val == map->reg_defaults[ret].def) {
685 ret = regcache_sync_block_raw_flush(map, &data,
693 data = regcache_get_val_addr(map, block, i);
698 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
702 int regcache_sync_block(struct regmap *map, void *block,
703 unsigned long *cache_present,
704 unsigned int block_base, unsigned int start,
707 if (regmap_can_raw_write(map) && !map->use_single_rw)
708 return regcache_sync_block_raw(map, block, cache_present,
709 block_base, start, end);
711 return regcache_sync_block_single(map, block, cache_present,
712 block_base, start, end);