2 * Broadcom specific AMBA
3 * Broadcom MIPS32 74K core driver
5 * Copyright 2009, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
8 * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
10 * Licensed under the GNU/GPL. See COPYING for details.
13 #include "bcma_private.h"
15 #include <linux/bcma/bcma.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial_reg.h>
22 #include <linux/time.h>
25 BCMA_BOOT_DEV_UNK = 0,
27 BCMA_BOOT_DEV_PARALLEL,
32 static const char * const part_probes[] = { "bcm47xxpart", NULL };
34 static struct physmap_flash_data bcma_pflash_data = {
35 .part_probe_types = part_probes,
38 static struct resource bcma_pflash_resource = {
39 .name = "bcma_pflash",
40 .flags = IORESOURCE_MEM,
43 struct platform_device bcma_pflash_dev = {
44 .name = "physmap-flash",
46 .platform_data = &bcma_pflash_data,
48 .resource = &bcma_pflash_resource,
52 /* The 47162a0 hangs when reading MIPS DMP registers registers */
53 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
55 return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
56 dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
59 /* The 5357b0 hangs when reading USB20H DMP registers */
60 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
62 return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
63 dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
64 dev->bus->chipinfo.pkg == 11 &&
65 dev->id.id == BCMA_CORE_USB20_HOST;
68 static inline u32 mips_read32(struct bcma_drv_mips *mcore,
71 return bcma_read32(mcore->core, offset);
74 static inline void mips_write32(struct bcma_drv_mips *mcore,
78 bcma_write32(mcore->core, offset, value);
81 static const u32 ipsflag_irq_mask[] = {
83 BCMA_MIPS_IPSFLAG_IRQ1,
84 BCMA_MIPS_IPSFLAG_IRQ2,
85 BCMA_MIPS_IPSFLAG_IRQ3,
86 BCMA_MIPS_IPSFLAG_IRQ4,
89 static const u32 ipsflag_irq_shift[] = {
91 BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
92 BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
93 BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
94 BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
97 static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
101 if (bcma_core_mips_bcm47162a0_quirk(dev))
102 return dev->core_index;
103 if (bcma_core_mips_bcm5357b0_quirk(dev))
104 return dev->core_index;
105 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
113 /* Get the MIPS IRQ assignment for a specified device.
114 * If unassigned, 0 is returned.
115 * If disabled, 5 is returned.
116 * If not supported, 6 is returned.
118 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
120 struct bcma_device *mdev = dev->bus->drv_mips.core;
124 irqflag = bcma_core_mips_irqflag(dev);
128 for (irq = 0; irq <= 4; irq++)
129 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
136 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
138 unsigned int oldirq = bcma_core_mips_irq(dev);
139 struct bcma_bus *bus = dev->bus;
140 struct bcma_device *mdev = bus->drv_mips.core;
143 irqflag = bcma_core_mips_irqflag(dev);
148 /* clear the old irq */
150 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
151 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
153 else if (oldirq != 5)
154 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
156 /* assign the new one */
158 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
159 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
162 u32 irqinitmask = bcma_read32(mdev,
163 BCMA_MIPS_MIPS74K_INTMASK(irq));
165 struct bcma_device *core;
167 /* backplane irq line is in use, find out who uses
168 * it and set user to irq 0
170 list_for_each_entry(core, &bus->cores, list) {
171 if ((1 << bcma_core_mips_irqflag(core)) ==
173 bcma_core_mips_set_irq(core, 0);
178 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
182 bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
183 dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
186 static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
189 struct bcma_device *core;
191 core = bcma_find_core_unit(bus, coreid, unit);
194 "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
199 bcma_core_mips_set_irq(core, irq);
202 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
205 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
206 printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
207 for (i = 0; i <= 6; i++)
208 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
212 static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
214 struct bcma_device *core;
216 list_for_each_entry(core, &bus->cores, list) {
217 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
221 u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
223 struct bcma_bus *bus = mcore->core->bus;
225 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
226 return bcma_pmu_get_cpu_clock(&bus->drv_cc);
228 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
231 EXPORT_SYMBOL(bcma_cpu_clock);
233 static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
235 struct bcma_drv_cc *cc = &bus->drv_cc;
236 u8 cc_rev = cc->core->id.rev;
239 struct bcma_device *core;
241 core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
243 switch (bcma_aread32(core, BCMA_IOST) &
244 BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
245 case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
246 return BCMA_BOOT_DEV_SERIAL;
247 case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
248 return BCMA_BOOT_DEV_NAND;
249 case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
251 return BCMA_BOOT_DEV_ROM;
256 if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
257 return BCMA_BOOT_DEV_NAND;
258 else if (cc->status & BIT(5))
259 return BCMA_BOOT_DEV_ROM;
262 if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
264 return BCMA_BOOT_DEV_PARALLEL;
266 return BCMA_BOOT_DEV_SERIAL;
269 return BCMA_BOOT_DEV_SERIAL;
272 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
274 struct bcma_bus *bus = mcore->core->bus;
275 struct bcma_drv_cc *cc = &bus->drv_cc;
276 struct bcma_pflash *pflash = &cc->pflash;
277 enum bcma_boot_dev boot_dev;
279 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
280 case BCMA_CC_FLASHT_STSER:
281 case BCMA_CC_FLASHT_ATSER:
282 bcma_debug(bus, "Found serial flash\n");
283 bcma_sflash_init(cc);
285 case BCMA_CC_FLASHT_PARA:
286 bcma_debug(bus, "Found parallel flash\n");
287 pflash->present = true;
288 pflash->window = BCMA_SOC_FLASH2;
289 pflash->window_size = BCMA_SOC_FLASH2_SZ;
291 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
292 BCMA_CC_FLASH_CFG_DS) == 0)
293 pflash->buswidth = 1;
295 pflash->buswidth = 2;
297 bcma_pflash_data.width = pflash->buswidth;
298 bcma_pflash_resource.start = pflash->window;
299 bcma_pflash_resource.end = pflash->window + pflash->window_size;
303 bcma_err(bus, "Flash type not supported\n");
306 if (cc->core->id.rev == 38 ||
307 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
308 if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
309 bcma_debug(bus, "Found NAND flash\n");
310 bcma_nflash_init(cc);
314 /* Determine flash type this SoC boots from */
315 boot_dev = bcma_boot_dev(bus);
317 case BCMA_BOOT_DEV_PARALLEL:
318 case BCMA_BOOT_DEV_SERIAL:
319 /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
321 case BCMA_BOOT_DEV_NAND:
322 /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
329 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
331 struct bcma_bus *bus = mcore->core->bus;
333 if (mcore->early_setup_done)
336 bcma_chipco_serial_init(&bus->drv_cc);
337 bcma_core_mips_flash_detect(mcore);
339 mcore->early_setup_done = true;
342 static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
344 struct bcma_device *cpu, *pcie, *i2s;
346 /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
347 * (IRQ flags > 7 are ignored when setting the interrupt masks)
349 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
350 bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
353 cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
354 pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
355 i2s = bcma_find_core(bus, BCMA_CORE_I2S);
356 if (cpu && pcie && i2s &&
357 bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
358 bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
359 bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
360 bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
361 bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
362 bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
364 "Moved i2s interrupt to oob line 7 instead of 8\n");
368 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
370 struct bcma_bus *bus;
371 struct bcma_device *core;
372 bus = mcore->core->bus;
374 if (mcore->setup_done)
377 bcma_debug(bus, "Initializing MIPS core...\n");
379 bcma_core_mips_early_init(mcore);
381 bcma_fix_i2s_irqflag(bus);
383 switch (bus->chipinfo.id) {
384 case BCMA_CHIP_ID_BCM4716:
385 case BCMA_CHIP_ID_BCM4748:
386 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
387 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
388 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
389 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
390 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
391 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
393 case BCMA_CHIP_ID_BCM5356:
394 case BCMA_CHIP_ID_BCM47162:
395 case BCMA_CHIP_ID_BCM53572:
396 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
397 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
398 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
400 case BCMA_CHIP_ID_BCM5357:
401 case BCMA_CHIP_ID_BCM4749:
402 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
403 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
404 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
405 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
406 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
408 case BCMA_CHIP_ID_BCM4706:
409 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
410 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
412 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
413 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
414 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
418 list_for_each_entry(core, &bus->cores, list) {
419 core->irq = bcma_core_irq(core, 0);
422 "Unknown device (0x%x) found, can not configure IRQs\n",
425 bcma_debug(bus, "IRQ reconfiguration done\n");
426 bcma_core_mips_dump_irq(bus);
428 mcore->setup_done = true;