2 * Broadcom specific AMBA
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "bcma_private.h"
12 #include <linux/bcma/bcma.h>
14 /**************************************************
16 **************************************************/
18 static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
20 pcicore_write32(pc, 0x130, address);
21 pcicore_read32(pc, 0x130);
22 return pcicore_read32(pc, 0x134);
26 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
28 pcicore_write32(pc, 0x130, address);
29 pcicore_read32(pc, 0x130);
30 pcicore_write32(pc, 0x134, data);
34 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
36 const u16 mdio_control = 0x128;
37 const u16 mdio_data = 0x12C;
41 v = (1 << 30); /* Start of Transaction */
42 v |= (1 << 28); /* Write Transaction */
43 v |= (1 << 17); /* Turnaround */
46 pcicore_write32(pc, mdio_data, v);
49 for (i = 0; i < 200; i++) {
50 v = pcicore_read32(pc, mdio_control);
51 if (v & 0x100 /* Trans complete */)
57 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
59 const u16 mdio_control = 0x128;
60 const u16 mdio_data = 0x12C;
66 v = 0x80; /* Enable Preamble Sequence */
67 v |= 0x2; /* MDIO Clock Divisor */
68 pcicore_write32(pc, mdio_control, v);
70 if (pc->core->id.rev >= 10) {
72 bcma_pcie_mdio_set_phy(pc, device);
75 v = (1 << 30); /* Start of Transaction */
76 v |= (1 << 29); /* Read Transaction */
77 v |= (1 << 17); /* Turnaround */
78 if (pc->core->id.rev < 10)
79 v |= (u32)device << 22;
80 v |= (u32)address << 18;
81 pcicore_write32(pc, mdio_data, v);
82 /* Wait for the device to complete the transaction */
84 for (i = 0; i < max_retries; i++) {
85 v = pcicore_read32(pc, mdio_control);
86 if (v & 0x100 /* Trans complete */) {
88 ret = pcicore_read32(pc, mdio_data);
93 pcicore_write32(pc, mdio_control, 0);
97 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
100 const u16 mdio_control = 0x128;
101 const u16 mdio_data = 0x12C;
102 int max_retries = 10;
106 v = 0x80; /* Enable Preamble Sequence */
107 v |= 0x2; /* MDIO Clock Divisor */
108 pcicore_write32(pc, mdio_control, v);
110 if (pc->core->id.rev >= 10) {
112 bcma_pcie_mdio_set_phy(pc, device);
115 v = (1 << 30); /* Start of Transaction */
116 v |= (1 << 28); /* Write Transaction */
117 v |= (1 << 17); /* Turnaround */
118 if (pc->core->id.rev < 10)
119 v |= (u32)device << 22;
120 v |= (u32)address << 18;
122 pcicore_write32(pc, mdio_data, v);
123 /* Wait for the device to complete the transaction */
125 for (i = 0; i < max_retries; i++) {
126 v = pcicore_read32(pc, mdio_control);
127 if (v & 0x100 /* Trans complete */)
131 pcicore_write32(pc, mdio_control, 0);
134 /**************************************************
136 **************************************************/
138 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
140 return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
143 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
145 const u8 serdes_pll_device = 0x1D;
146 const u8 serdes_rx_device = 0x1F;
149 bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
150 bcma_pcicore_polarity_workaround(pc));
151 tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
153 bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
156 /**************************************************
158 **************************************************/
160 void bcma_core_pci_init(struct bcma_drv_pci *pc)
162 bcma_pcicore_serdes_workaround(pc);