2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/poison.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/version.h>
41 #define NVME_Q_DEPTH 1024
42 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
43 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
44 #define NVME_MINORS 64
45 #define IO_TIMEOUT (5 * HZ)
46 #define ADMIN_TIMEOUT (60 * HZ)
48 static int nvme_major;
49 module_param(nvme_major, int, 0);
51 static int use_threaded_interrupts;
52 module_param(use_threaded_interrupts, int, 0);
54 static DEFINE_SPINLOCK(dev_list_lock);
55 static LIST_HEAD(dev_list);
56 static struct task_struct *nvme_thread;
59 * Represents an NVM Express device. Each nvme_dev is a PCI function.
62 struct list_head node;
63 struct nvme_queue **queues;
65 struct pci_dev *pci_dev;
66 struct dma_pool *prp_page_pool;
67 struct dma_pool *prp_small_pool;
71 struct msix_entry *entry;
72 struct nvme_bar __iomem *bar;
73 struct list_head namespaces;
80 * An NVM Express namespace is equivalent to a SCSI LUN
83 struct list_head list;
86 struct request_queue *queue;
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
98 struct device *q_dmadev;
101 struct nvme_command *sq_cmds;
102 volatile struct nvme_completion *cqes;
103 dma_addr_t sq_dma_addr;
104 dma_addr_t cq_dma_addr;
105 wait_queue_head_t sq_full;
106 wait_queue_t sq_cong_wait;
107 struct bio_list sq_cong;
115 unsigned long cmdid_data[];
119 * Check we didin't inadvertently grow the command struct
121 static inline void _nvme_check_size(void)
123 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
124 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
130 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
131 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
134 struct nvme_cmd_info {
136 unsigned long timeout;
139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
141 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
145 * alloc_cmdid() - Allocate a Command ID
146 * @nvmeq: The queue that will be used for this command
147 * @ctx: A pointer that will be passed to the handler
148 * @handler: The ID of the handler to call
150 * Allocate a Command ID for a queue. The data passed in will
151 * be passed to the completion handler. This is implemented by using
152 * the bottom two bits of the ctx pointer to store the handler ID.
153 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
154 * We can change this if it becomes a problem.
156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
159 int depth = nvmeq->q_depth - 1;
160 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
163 BUG_ON((unsigned long)ctx & 3);
166 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
169 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
171 info[cmdid].ctx = (unsigned long)ctx | handler;
172 info[cmdid].timeout = jiffies + timeout;
176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
177 int handler, unsigned timeout)
180 wait_event_killable(nvmeq->sq_full,
181 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
182 return (cmdid < 0) ? -EINTR : cmdid;
186 * If you need more than four handlers, you'll need to change how
187 * alloc_cmdid and nvme_process_cq work. Consider using a special
188 * CMD_CTX value instead, if that works for your situation.
191 sync_completion_id = 0,
195 /* Special values must be a multiple of 4, and less than 0x1000 */
196 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
197 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
200 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
202 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
205 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
207 if (cmdid >= nvmeq->q_depth)
208 return CMD_CTX_INVALID;
209 data = info[cmdid].ctx;
210 info[cmdid].ctx = CMD_CTX_COMPLETED;
211 clear_bit(cmdid, nvmeq->cmdid_data);
212 wake_up(&nvmeq->sq_full);
216 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
218 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
219 info[cmdid].ctx = CMD_CTX_CANCELLED;
222 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
224 return ns->dev->queues[get_cpu() + 1];
227 static void put_nvmeq(struct nvme_queue *nvmeq)
233 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
234 * @nvmeq: The queue to use
235 * @cmd: The command to send
237 * Safe to use from interrupt context
239 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
243 spin_lock_irqsave(&nvmeq->q_lock, flags);
244 tail = nvmeq->sq_tail;
245 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
246 if (++tail == nvmeq->q_depth)
248 writel(tail, nvmeq->q_db);
249 nvmeq->sq_tail = tail;
250 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
257 dma_addr_t first_dma;
261 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
263 const int last_prp = PAGE_SIZE / 8 - 1;
270 prp_dma = prps->first_dma;
272 if (prps->npages == 0)
273 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
274 for (i = 0; i < prps->npages; i++) {
275 __le64 *prp_list = prps->list[i];
276 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
277 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
278 prp_dma = next_prp_dma;
286 struct nvme_prps *prps;
287 struct scatterlist sg[0];
290 /* XXX: use a mempool */
291 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
293 return kzalloc(sizeof(struct nvme_bio) +
294 sizeof(struct scatterlist) * nseg, gfp);
297 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
299 nvme_free_prps(nvmeq->dev, nbio->prps);
303 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
304 struct nvme_completion *cqe)
306 struct nvme_bio *nbio = ctx;
307 struct bio *bio = nbio->bio;
308 u16 status = le16_to_cpup(&cqe->status) >> 1;
310 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
311 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
312 free_nbio(nvmeq, nbio);
314 bio_endio(bio, -EIO);
315 if (bio->bi_vcnt > bio->bi_idx) {
316 bio_list_add(&nvmeq->sq_cong, bio);
317 wake_up_process(nvme_thread);
323 /* length is in bytes */
324 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
325 struct nvme_common_command *cmd,
326 struct scatterlist *sg, int length)
328 struct dma_pool *pool;
329 int dma_len = sg_dma_len(sg);
330 u64 dma_addr = sg_dma_address(sg);
331 int offset = offset_in_page(dma_addr);
334 int nprps, npages, i, prp_page;
335 struct nvme_prps *prps = NULL;
337 cmd->prp1 = cpu_to_le64(dma_addr);
338 length -= (PAGE_SIZE - offset);
342 dma_len -= (PAGE_SIZE - offset);
344 dma_addr += (PAGE_SIZE - offset);
347 dma_addr = sg_dma_address(sg);
348 dma_len = sg_dma_len(sg);
351 if (length <= PAGE_SIZE) {
352 cmd->prp2 = cpu_to_le64(dma_addr);
356 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
357 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
358 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
360 if (nprps <= (256 / 8)) {
361 pool = dev->prp_small_pool;
364 pool = dev->prp_page_pool;
365 prps->npages = npages;
368 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
369 prps->list[prp_page++] = prp_list;
370 prps->first_dma = prp_dma;
371 cmd->prp2 = cpu_to_le64(prp_dma);
374 if (i == PAGE_SIZE / 8) {
375 __le64 *old_prp_list = prp_list;
376 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
377 prps->list[prp_page++] = prp_list;
378 prp_list[0] = old_prp_list[i - 1];
379 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
382 prp_list[i++] = cpu_to_le64(dma_addr);
383 dma_len -= PAGE_SIZE;
384 dma_addr += PAGE_SIZE;
392 dma_addr = sg_dma_address(sg);
393 dma_len = sg_dma_len(sg);
399 /* NVMe scatterlists require no holes in the virtual address */
400 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
401 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
403 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
404 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
406 struct bio_vec *bvec, *bvprv = NULL;
407 struct scatterlist *sg = NULL;
408 int i, old_idx, length = 0, nsegs = 0;
410 sg_init_table(nbio->sg, psegs);
411 old_idx = bio->bi_idx;
412 bio_for_each_segment(bvec, bio, i) {
413 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
414 sg->length += bvec->bv_len;
416 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
418 sg = sg ? sg + 1 : nbio->sg;
419 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
423 length += bvec->bv_len;
429 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
430 bio->bi_idx = old_idx;
436 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
439 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
441 memset(cmnd, 0, sizeof(*cmnd));
442 cmnd->common.opcode = nvme_cmd_flush;
443 cmnd->common.command_id = cmdid;
444 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
446 if (++nvmeq->sq_tail == nvmeq->q_depth)
448 writel(nvmeq->sq_tail, nvmeq->q_db);
453 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
455 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
456 sync_completion_id, IO_TIMEOUT);
457 if (unlikely(cmdid < 0))
460 return nvme_submit_flush(nvmeq, ns, cmdid);
463 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
466 struct nvme_command *cmnd;
467 struct nvme_bio *nbio;
468 enum dma_data_direction dma_dir;
469 int cmdid, length, result = -ENOMEM;
472 int psegs = bio_phys_segments(ns->queue, bio);
474 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
475 result = nvme_submit_flush_data(nvmeq, ns);
480 nbio = alloc_nbio(psegs, GFP_ATOMIC);
486 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
487 if (unlikely(cmdid < 0))
490 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
491 return nvme_submit_flush(nvmeq, ns, cmdid);
494 if (bio->bi_rw & REQ_FUA)
495 control |= NVME_RW_FUA;
496 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
497 control |= NVME_RW_LR;
500 if (bio->bi_rw & REQ_RAHEAD)
501 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
503 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
505 memset(cmnd, 0, sizeof(*cmnd));
506 if (bio_data_dir(bio)) {
507 cmnd->rw.opcode = nvme_cmd_write;
508 dma_dir = DMA_TO_DEVICE;
510 cmnd->rw.opcode = nvme_cmd_read;
511 dma_dir = DMA_FROM_DEVICE;
514 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
519 cmnd->rw.command_id = cmdid;
520 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
521 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
523 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
524 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
525 cmnd->rw.control = cpu_to_le16(control);
526 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
528 bio->bi_sector += length >> 9;
530 if (++nvmeq->sq_tail == nvmeq->q_depth)
532 writel(nvmeq->sq_tail, nvmeq->q_db);
537 free_nbio(nvmeq, nbio);
543 * NB: return value of non-zero would mean that we were a stacking driver.
544 * make_request must always succeed.
546 static int nvme_make_request(struct request_queue *q, struct bio *bio)
548 struct nvme_ns *ns = q->queuedata;
549 struct nvme_queue *nvmeq = get_nvmeq(ns);
552 spin_lock_irq(&nvmeq->q_lock);
553 if (bio_list_empty(&nvmeq->sq_cong))
554 result = nvme_submit_bio_queue(nvmeq, ns, bio);
555 if (unlikely(result)) {
556 if (bio_list_empty(&nvmeq->sq_cong))
557 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
558 bio_list_add(&nvmeq->sq_cong, bio);
561 spin_unlock_irq(&nvmeq->q_lock);
567 struct sync_cmd_info {
568 struct task_struct *task;
573 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
574 struct nvme_completion *cqe)
576 struct sync_cmd_info *cmdinfo = ctx;
577 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
579 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
581 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
582 dev_warn(nvmeq->q_dmadev,
583 "completed id %d twice on queue %d\n",
584 cqe->command_id, le16_to_cpup(&cqe->sq_id));
587 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
588 dev_warn(nvmeq->q_dmadev,
589 "invalid id %d completed on queue %d\n",
590 cqe->command_id, le16_to_cpup(&cqe->sq_id));
593 cmdinfo->result = le32_to_cpup(&cqe->result);
594 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
595 wake_up_process(cmdinfo->task);
598 typedef void (*completion_fn)(struct nvme_queue *, void *,
599 struct nvme_completion *);
601 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
605 static const completion_fn completions[4] = {
606 [sync_completion_id] = sync_completion,
607 [bio_completion_id] = bio_completion,
610 head = nvmeq->cq_head;
611 phase = nvmeq->cq_phase;
616 unsigned char handler;
617 struct nvme_completion cqe = nvmeq->cqes[head];
618 if ((le16_to_cpu(cqe.status) & 1) != phase)
620 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
621 if (++head == nvmeq->q_depth) {
626 data = free_cmdid(nvmeq, cqe.command_id);
628 ptr = (void *)(data & ~3UL);
629 completions[handler](nvmeq, ptr, &cqe);
632 /* If the controller ignores the cq head doorbell and continuously
633 * writes to the queue, it is theoretically possible to wrap around
634 * the queue twice and mistakenly return IRQ_NONE. Linux only
635 * requires that 0.1% of your interrupts are handled, so this isn't
638 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
641 writel(head, nvmeq->q_db + 1);
642 nvmeq->cq_head = head;
643 nvmeq->cq_phase = phase;
648 static irqreturn_t nvme_irq(int irq, void *data)
651 struct nvme_queue *nvmeq = data;
652 spin_lock(&nvmeq->q_lock);
653 result = nvme_process_cq(nvmeq);
654 spin_unlock(&nvmeq->q_lock);
658 static irqreturn_t nvme_irq_check(int irq, void *data)
660 struct nvme_queue *nvmeq = data;
661 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
662 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
664 return IRQ_WAKE_THREAD;
667 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
669 spin_lock_irq(&nvmeq->q_lock);
670 cancel_cmdid_data(nvmeq, cmdid);
671 spin_unlock_irq(&nvmeq->q_lock);
675 * Returns 0 on success. If the result is negative, it's a Linux error code;
676 * if the result is positive, it's an NVM Express status code
678 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
679 struct nvme_command *cmd, u32 *result, unsigned timeout)
682 struct sync_cmd_info cmdinfo;
684 cmdinfo.task = current;
685 cmdinfo.status = -EINTR;
687 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
691 cmd->common.command_id = cmdid;
693 set_current_state(TASK_KILLABLE);
694 nvme_submit_cmd(nvmeq, cmd);
697 if (cmdinfo.status == -EINTR) {
698 nvme_abort_command(nvmeq, cmdid);
703 *result = cmdinfo.result;
705 return cmdinfo.status;
708 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
711 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
714 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
717 struct nvme_command c;
719 memset(&c, 0, sizeof(c));
720 c.delete_queue.opcode = opcode;
721 c.delete_queue.qid = cpu_to_le16(id);
723 status = nvme_submit_admin_cmd(dev, &c, NULL);
729 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
730 struct nvme_queue *nvmeq)
733 struct nvme_command c;
734 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
736 memset(&c, 0, sizeof(c));
737 c.create_cq.opcode = nvme_admin_create_cq;
738 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
739 c.create_cq.cqid = cpu_to_le16(qid);
740 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
741 c.create_cq.cq_flags = cpu_to_le16(flags);
742 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
744 status = nvme_submit_admin_cmd(dev, &c, NULL);
750 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
751 struct nvme_queue *nvmeq)
754 struct nvme_command c;
755 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
757 memset(&c, 0, sizeof(c));
758 c.create_sq.opcode = nvme_admin_create_sq;
759 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
760 c.create_sq.sqid = cpu_to_le16(qid);
761 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
762 c.create_sq.sq_flags = cpu_to_le16(flags);
763 c.create_sq.cqid = cpu_to_le16(qid);
765 status = nvme_submit_admin_cmd(dev, &c, NULL);
771 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
773 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
776 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
778 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
781 static void nvme_free_queue(struct nvme_dev *dev, int qid)
783 struct nvme_queue *nvmeq = dev->queues[qid];
785 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
787 /* Don't tell the adapter to delete the admin queue */
789 adapter_delete_sq(dev, qid);
790 adapter_delete_cq(dev, qid);
793 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
794 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
795 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
796 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
800 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
801 int depth, int vector)
803 struct device *dmadev = &dev->pci_dev->dev;
804 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
805 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
809 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
810 &nvmeq->cq_dma_addr, GFP_KERNEL);
813 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
815 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
816 &nvmeq->sq_dma_addr, GFP_KERNEL);
820 nvmeq->q_dmadev = dmadev;
822 spin_lock_init(&nvmeq->q_lock);
825 init_waitqueue_head(&nvmeq->sq_full);
826 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
827 bio_list_init(&nvmeq->sq_cong);
828 nvmeq->q_db = &dev->dbs[qid * 2];
829 nvmeq->q_depth = depth;
830 nvmeq->cq_vector = vector;
835 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
842 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
845 if (use_threaded_interrupts)
846 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
847 nvme_irq_check, nvme_irq,
848 IRQF_DISABLED | IRQF_SHARED,
850 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
851 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
854 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
855 int qid, int cq_size, int vector)
858 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
863 result = adapter_alloc_cq(dev, qid, nvmeq);
867 result = adapter_alloc_sq(dev, qid, nvmeq);
871 result = queue_request_irq(dev, nvmeq, "nvme");
878 adapter_delete_sq(dev, qid);
880 adapter_delete_cq(dev, qid);
882 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
883 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
884 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
885 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
890 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
894 struct nvme_queue *nvmeq;
896 dev->dbs = ((void __iomem *)dev->bar) + 4096;
898 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
902 aqa = nvmeq->q_depth - 1;
905 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
906 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
907 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
908 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
910 writel(0, &dev->bar->cc);
911 writel(aqa, &dev->bar->aqa);
912 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
913 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
914 writel(dev->ctrl_config, &dev->bar->cc);
916 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
918 if (fatal_signal_pending(current))
922 result = queue_request_irq(dev, nvmeq, "nvme admin");
923 dev->queues[0] = nvmeq;
927 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
928 unsigned long addr, unsigned length,
929 struct scatterlist **sgp)
931 int i, err, count, nents, offset;
932 struct scatterlist *sg;
940 offset = offset_in_page(addr);
941 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
942 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
944 err = get_user_pages_fast(addr, count, 1, pages);
951 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
952 sg_init_table(sg, count);
953 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
954 length -= (PAGE_SIZE - offset);
955 for (i = 1; i < count; i++) {
956 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
961 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
962 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
971 for (i = 0; i < count; i++)
977 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
978 unsigned long addr, int length,
979 struct scatterlist *sg, int nents)
983 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
984 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
986 for (i = 0; i < count; i++)
987 put_page(sg_page(&sg[i]));
990 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
991 unsigned long addr, unsigned length,
992 struct nvme_command *cmd)
995 struct scatterlist *sg;
996 struct nvme_prps *prps;
998 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1001 prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1002 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1003 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1004 nvme_free_prps(dev, prps);
1005 return err ? -EIO : 0;
1008 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1010 struct nvme_command c;
1012 memset(&c, 0, sizeof(c));
1013 c.identify.opcode = nvme_admin_identify;
1014 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1015 c.identify.cns = cpu_to_le32(cns);
1017 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1020 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1022 struct nvme_command c;
1024 memset(&c, 0, sizeof(c));
1025 c.features.opcode = nvme_admin_get_features;
1026 c.features.nsid = cpu_to_le32(ns->ns_id);
1027 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1029 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1032 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1034 struct nvme_dev *dev = ns->dev;
1035 struct nvme_queue *nvmeq;
1036 struct nvme_user_io io;
1037 struct nvme_command c;
1040 struct scatterlist *sg;
1041 struct nvme_prps *prps;
1043 if (copy_from_user(&io, uio, sizeof(io)))
1045 length = (io.nblocks + 1) << ns->lba_shift;
1047 switch (io.opcode) {
1048 case nvme_cmd_write:
1050 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1059 memset(&c, 0, sizeof(c));
1060 c.rw.opcode = io.opcode;
1061 c.rw.flags = io.flags;
1062 c.rw.nsid = cpu_to_le32(ns->ns_id);
1063 c.rw.slba = cpu_to_le64(io.slba);
1064 c.rw.length = cpu_to_le16(io.nblocks);
1065 c.rw.control = cpu_to_le16(io.control);
1066 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1067 c.rw.reftag = io.reftag;
1068 c.rw.apptag = io.apptag;
1069 c.rw.appmask = io.appmask;
1071 prps = nvme_setup_prps(dev, &c.common, sg, length);
1073 nvmeq = get_nvmeq(ns);
1075 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1076 * disabled. We may be preempted at any point, and be rescheduled
1077 * to a different CPU. That will cause cacheline bouncing, but no
1078 * additional races since q_lock already protects against other CPUs.
1081 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1083 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1084 nvme_free_prps(dev, prps);
1088 static int nvme_download_firmware(struct nvme_ns *ns,
1089 struct nvme_dlfw __user *udlfw)
1091 struct nvme_dev *dev = ns->dev;
1092 struct nvme_dlfw dlfw;
1093 struct nvme_command c;
1095 struct scatterlist *sg;
1096 struct nvme_prps *prps;
1098 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1100 if (dlfw.length >= (1 << 30))
1103 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1107 memset(&c, 0, sizeof(c));
1108 c.dlfw.opcode = nvme_admin_download_fw;
1109 c.dlfw.numd = cpu_to_le32(dlfw.length);
1110 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1111 prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1113 status = nvme_submit_admin_cmd(dev, &c, NULL);
1114 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1115 nvme_free_prps(dev, prps);
1119 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1121 struct nvme_dev *dev = ns->dev;
1122 struct nvme_command c;
1124 memset(&c, 0, sizeof(c));
1125 c.common.opcode = nvme_admin_activate_fw;
1126 c.common.rsvd10[0] = cpu_to_le32(arg);
1128 return nvme_submit_admin_cmd(dev, &c, NULL);
1131 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1134 struct nvme_ns *ns = bdev->bd_disk->private_data;
1137 case NVME_IOCTL_IDENTIFY_NS:
1138 return nvme_identify(ns, arg, 0);
1139 case NVME_IOCTL_IDENTIFY_CTRL:
1140 return nvme_identify(ns, arg, 1);
1141 case NVME_IOCTL_GET_RANGE_TYPE:
1142 return nvme_get_range_type(ns, arg);
1143 case NVME_IOCTL_SUBMIT_IO:
1144 return nvme_submit_io(ns, (void __user *)arg);
1145 case NVME_IOCTL_DOWNLOAD_FW:
1146 return nvme_download_firmware(ns, (void __user *)arg);
1147 case NVME_IOCTL_ACTIVATE_FW:
1148 return nvme_activate_firmware(ns, arg);
1154 static const struct block_device_operations nvme_fops = {
1155 .owner = THIS_MODULE,
1156 .ioctl = nvme_ioctl,
1157 .compat_ioctl = nvme_ioctl,
1160 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1162 while (bio_list_peek(&nvmeq->sq_cong)) {
1163 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1164 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1165 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1166 bio_list_add_head(&nvmeq->sq_cong, bio);
1169 if (bio_list_empty(&nvmeq->sq_cong))
1170 remove_wait_queue(&nvmeq->sq_full,
1171 &nvmeq->sq_cong_wait);
1175 static int nvme_kthread(void *data)
1177 struct nvme_dev *dev;
1179 while (!kthread_should_stop()) {
1180 __set_current_state(TASK_RUNNING);
1181 spin_lock(&dev_list_lock);
1182 list_for_each_entry(dev, &dev_list, node) {
1184 for (i = 0; i < dev->queue_count; i++) {
1185 struct nvme_queue *nvmeq = dev->queues[i];
1188 spin_lock_irq(&nvmeq->q_lock);
1189 if (nvme_process_cq(nvmeq))
1190 printk("process_cq did something\n");
1191 nvme_resubmit_bios(nvmeq);
1192 spin_unlock_irq(&nvmeq->q_lock);
1195 spin_unlock(&dev_list_lock);
1196 set_current_state(TASK_INTERRUPTIBLE);
1197 schedule_timeout(HZ);
1202 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1203 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1206 struct gendisk *disk;
1209 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1212 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1215 ns->queue = blk_alloc_queue(GFP_KERNEL);
1218 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1219 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1220 blk_queue_make_request(ns->queue, nvme_make_request);
1222 ns->queue->queuedata = ns;
1224 disk = alloc_disk(NVME_MINORS);
1226 goto out_free_queue;
1229 lbaf = id->flbas & 0xf;
1230 ns->lba_shift = id->lbaf[lbaf].ds;
1232 disk->major = nvme_major;
1233 disk->minors = NVME_MINORS;
1234 disk->first_minor = NVME_MINORS * index;
1235 disk->fops = &nvme_fops;
1236 disk->private_data = ns;
1237 disk->queue = ns->queue;
1238 disk->driverfs_dev = &dev->pci_dev->dev;
1239 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1240 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1245 blk_cleanup_queue(ns->queue);
1251 static void nvme_ns_free(struct nvme_ns *ns)
1254 blk_cleanup_queue(ns->queue);
1258 static int set_queue_count(struct nvme_dev *dev, int count)
1262 struct nvme_command c;
1263 u32 q_count = (count - 1) | ((count - 1) << 16);
1265 memset(&c, 0, sizeof(c));
1266 c.features.opcode = nvme_admin_get_features;
1267 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1268 c.features.dword11 = cpu_to_le32(q_count);
1270 status = nvme_submit_admin_cmd(dev, &c, &result);
1273 return min(result & 0xffff, result >> 16) + 1;
1276 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1278 int result, cpu, i, nr_io_queues;
1280 nr_io_queues = num_online_cpus();
1281 result = set_queue_count(dev, nr_io_queues);
1284 if (result < nr_io_queues)
1285 nr_io_queues = result;
1287 /* Deregister the admin queue's interrupt */
1288 free_irq(dev->entry[0].vector, dev->queues[0]);
1290 for (i = 0; i < nr_io_queues; i++)
1291 dev->entry[i].entry = i;
1293 result = pci_enable_msix(dev->pci_dev, dev->entry,
1297 } else if (result > 0) {
1298 nr_io_queues = result;
1306 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1307 /* XXX: handle failure here */
1309 cpu = cpumask_first(cpu_online_mask);
1310 for (i = 0; i < nr_io_queues; i++) {
1311 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1312 cpu = cpumask_next(cpu, cpu_online_mask);
1315 for (i = 0; i < nr_io_queues; i++) {
1316 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1318 if (!dev->queues[i + 1])
1323 for (; i < num_possible_cpus(); i++) {
1324 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1325 dev->queues[i + 1] = dev->queues[target + 1];
1331 static void nvme_free_queues(struct nvme_dev *dev)
1335 for (i = dev->queue_count - 1; i >= 0; i--)
1336 nvme_free_queue(dev, i);
1339 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1342 struct nvme_ns *ns, *next;
1343 struct nvme_id_ctrl *ctrl;
1345 dma_addr_t dma_addr;
1346 struct nvme_command cid, crt;
1348 res = nvme_setup_io_queues(dev);
1352 /* XXX: Switch to a SG list once prp2 works */
1353 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1356 memset(&cid, 0, sizeof(cid));
1357 cid.identify.opcode = nvme_admin_identify;
1358 cid.identify.nsid = 0;
1359 cid.identify.prp1 = cpu_to_le64(dma_addr);
1360 cid.identify.cns = cpu_to_le32(1);
1362 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1369 nn = le32_to_cpup(&ctrl->nn);
1370 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1371 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1372 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1374 cid.identify.cns = 0;
1375 memset(&crt, 0, sizeof(crt));
1376 crt.features.opcode = nvme_admin_get_features;
1377 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1378 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1380 for (i = 0; i <= nn; i++) {
1381 cid.identify.nsid = cpu_to_le32(i);
1382 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1386 if (((struct nvme_id_ns *)id)->ncap == 0)
1389 crt.features.nsid = cpu_to_le32(i);
1390 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1394 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1396 list_add_tail(&ns->list, &dev->namespaces);
1398 list_for_each_entry(ns, &dev->namespaces, list)
1401 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1405 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1406 list_del(&ns->list);
1410 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1414 static int nvme_dev_remove(struct nvme_dev *dev)
1416 struct nvme_ns *ns, *next;
1418 spin_lock(&dev_list_lock);
1419 list_del(&dev->node);
1420 spin_unlock(&dev_list_lock);
1422 /* TODO: wait all I/O finished or cancel them */
1424 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1425 list_del(&ns->list);
1426 del_gendisk(ns->disk);
1430 nvme_free_queues(dev);
1435 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1437 struct device *dmadev = &dev->pci_dev->dev;
1438 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1439 PAGE_SIZE, PAGE_SIZE, 0);
1440 if (!dev->prp_page_pool)
1443 /* Optimisation for I/Os between 4k and 128k */
1444 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1446 if (!dev->prp_small_pool) {
1447 dma_pool_destroy(dev->prp_page_pool);
1453 static void nvme_release_prp_pools(struct nvme_dev *dev)
1455 dma_pool_destroy(dev->prp_page_pool);
1456 dma_pool_destroy(dev->prp_small_pool);
1459 /* XXX: Use an ida or something to let remove / add work correctly */
1460 static void nvme_set_instance(struct nvme_dev *dev)
1462 static int instance;
1463 dev->instance = instance++;
1466 static void nvme_release_instance(struct nvme_dev *dev)
1470 static int __devinit nvme_probe(struct pci_dev *pdev,
1471 const struct pci_device_id *id)
1473 int bars, result = -ENOMEM;
1474 struct nvme_dev *dev;
1476 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1479 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1483 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1488 if (pci_enable_device_mem(pdev))
1490 pci_set_master(pdev);
1491 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1492 if (pci_request_selected_regions(pdev, bars, "nvme"))
1495 INIT_LIST_HEAD(&dev->namespaces);
1496 dev->pci_dev = pdev;
1497 pci_set_drvdata(pdev, dev);
1498 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1499 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1500 nvme_set_instance(dev);
1501 dev->entry[0].vector = pdev->irq;
1503 result = nvme_setup_prp_pools(dev);
1507 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1513 result = nvme_configure_admin_queue(dev);
1518 spin_lock(&dev_list_lock);
1519 list_add(&dev->node, &dev_list);
1520 spin_unlock(&dev_list_lock);
1522 result = nvme_dev_add(dev);
1529 spin_lock(&dev_list_lock);
1530 list_del(&dev->node);
1531 spin_unlock(&dev_list_lock);
1533 nvme_free_queues(dev);
1537 pci_disable_msix(pdev);
1538 nvme_release_instance(dev);
1539 nvme_release_prp_pools(dev);
1541 pci_disable_device(pdev);
1542 pci_release_regions(pdev);
1550 static void __devexit nvme_remove(struct pci_dev *pdev)
1552 struct nvme_dev *dev = pci_get_drvdata(pdev);
1553 nvme_dev_remove(dev);
1554 pci_disable_msix(pdev);
1556 nvme_release_instance(dev);
1557 nvme_release_prp_pools(dev);
1558 pci_disable_device(pdev);
1559 pci_release_regions(pdev);
1565 /* These functions are yet to be implemented */
1566 #define nvme_error_detected NULL
1567 #define nvme_dump_registers NULL
1568 #define nvme_link_reset NULL
1569 #define nvme_slot_reset NULL
1570 #define nvme_error_resume NULL
1571 #define nvme_suspend NULL
1572 #define nvme_resume NULL
1574 static struct pci_error_handlers nvme_err_handler = {
1575 .error_detected = nvme_error_detected,
1576 .mmio_enabled = nvme_dump_registers,
1577 .link_reset = nvme_link_reset,
1578 .slot_reset = nvme_slot_reset,
1579 .resume = nvme_error_resume,
1582 /* Move to pci_ids.h later */
1583 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1585 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1586 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1589 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1591 static struct pci_driver nvme_driver = {
1593 .id_table = nvme_id_table,
1594 .probe = nvme_probe,
1595 .remove = __devexit_p(nvme_remove),
1596 .suspend = nvme_suspend,
1597 .resume = nvme_resume,
1598 .err_handler = &nvme_err_handler,
1601 static int __init nvme_init(void)
1603 int result = -EBUSY;
1605 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1606 if (IS_ERR(nvme_thread))
1607 return PTR_ERR(nvme_thread);
1609 nvme_major = register_blkdev(nvme_major, "nvme");
1610 if (nvme_major <= 0)
1613 result = pci_register_driver(&nvme_driver);
1615 goto unregister_blkdev;
1619 unregister_blkdev(nvme_major, "nvme");
1621 kthread_stop(nvme_thread);
1625 static void __exit nvme_exit(void)
1627 pci_unregister_driver(&nvme_driver);
1628 unregister_blkdev(nvme_major, "nvme");
1629 kthread_stop(nvme_thread);
1632 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1633 MODULE_LICENSE("GPL");
1634 MODULE_VERSION("0.5");
1635 module_init(nvme_init);
1636 module_exit(nvme_exit);