2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/version.h>
44 #define NVME_Q_DEPTH 1024
45 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
46 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
47 #define NVME_MINORS 64
48 #define NVME_IO_TIMEOUT (5 * HZ)
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major;
52 module_param(nvme_major, int, 0);
54 static int use_threaded_interrupts;
55 module_param(use_threaded_interrupts, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock);
58 static LIST_HEAD(dev_list);
59 static struct task_struct *nvme_thread;
62 * Represents an NVM Express device. Each nvme_dev is a PCI function.
65 struct list_head node;
66 struct nvme_queue **queues;
68 struct pci_dev *pci_dev;
69 struct dma_pool *prp_page_pool;
70 struct dma_pool *prp_small_pool;
75 struct msix_entry *entry;
76 struct nvme_bar __iomem *bar;
77 struct list_head namespaces;
84 * An NVM Express namespace is equivalent to a SCSI LUN
87 struct list_head list;
90 struct request_queue *queue;
98 * An NVM Express queue. Each device has at least two (one for admin
99 * commands and one for I/O commands).
102 struct device *q_dmadev;
103 struct nvme_dev *dev;
105 struct nvme_command *sq_cmds;
106 volatile struct nvme_completion *cqes;
107 dma_addr_t sq_dma_addr;
108 dma_addr_t cq_dma_addr;
109 wait_queue_head_t sq_full;
110 wait_queue_t sq_cong_wait;
111 struct bio_list sq_cong;
119 unsigned long cmdid_data[];
123 * Check we didin't inadvertently grow the command struct
125 static inline void _nvme_check_size(void)
127 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
138 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
139 struct nvme_completion *);
141 struct nvme_cmd_info {
142 nvme_completion_fn fn;
144 unsigned long timeout;
147 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
149 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
153 * alloc_cmdid() - Allocate a Command ID
154 * @nvmeq: The queue that will be used for this command
155 * @ctx: A pointer that will be passed to the handler
156 * @handler: The function to call on completion
158 * Allocate a Command ID for a queue. The data passed in will
159 * be passed to the completion handler. This is implemented by using
160 * the bottom two bits of the ctx pointer to store the handler ID.
161 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
162 * We can change this if it becomes a problem.
164 * May be called with local interrupts disabled and the q_lock held,
165 * or with interrupts enabled and no locks held.
167 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
168 nvme_completion_fn handler, unsigned timeout)
170 int depth = nvmeq->q_depth - 1;
171 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
175 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
178 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
180 info[cmdid].fn = handler;
181 info[cmdid].ctx = ctx;
182 info[cmdid].timeout = jiffies + timeout;
186 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
187 nvme_completion_fn handler, unsigned timeout)
190 wait_event_killable(nvmeq->sq_full,
191 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
192 return (cmdid < 0) ? -EINTR : cmdid;
195 /* Special values must be less than 0x1000 */
196 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
197 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
200 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
202 static void special_completion(struct nvme_dev *dev, void *ctx,
203 struct nvme_completion *cqe)
205 if (ctx == CMD_CTX_CANCELLED)
207 if (ctx == CMD_CTX_FLUSH)
209 if (ctx == CMD_CTX_COMPLETED) {
210 dev_warn(&dev->pci_dev->dev,
211 "completed id %d twice on queue %d\n",
212 cqe->command_id, le16_to_cpup(&cqe->sq_id));
215 if (ctx == CMD_CTX_INVALID) {
216 dev_warn(&dev->pci_dev->dev,
217 "invalid id %d completed on queue %d\n",
218 cqe->command_id, le16_to_cpup(&cqe->sq_id));
222 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
226 * Called with local interrupts disabled and the q_lock held. May not sleep.
228 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
229 nvme_completion_fn *fn)
232 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
234 if (cmdid >= nvmeq->q_depth) {
235 *fn = special_completion;
236 return CMD_CTX_INVALID;
238 *fn = info[cmdid].fn;
239 ctx = info[cmdid].ctx;
240 info[cmdid].fn = special_completion;
241 info[cmdid].ctx = CMD_CTX_COMPLETED;
242 clear_bit(cmdid, nvmeq->cmdid_data);
243 wake_up(&nvmeq->sq_full);
247 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
248 nvme_completion_fn *fn)
251 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
253 *fn = info[cmdid].fn;
254 ctx = info[cmdid].ctx;
255 info[cmdid].fn = special_completion;
256 info[cmdid].ctx = CMD_CTX_CANCELLED;
260 static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
262 return dev->queues[get_cpu() + 1];
265 static void put_nvmeq(struct nvme_queue *nvmeq)
271 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
272 * @nvmeq: The queue to use
273 * @cmd: The command to send
275 * Safe to use from interrupt context
277 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
281 spin_lock_irqsave(&nvmeq->q_lock, flags);
282 tail = nvmeq->sq_tail;
283 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
284 if (++tail == nvmeq->q_depth)
286 writel(tail, nvmeq->q_db);
287 nvmeq->sq_tail = tail;
288 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
294 * The nvme_iod describes the data in an I/O, including the list of PRP
295 * entries. You can't see it in this data structure because C doesn't let
296 * me express that. Use nvme_alloc_iod to ensure there's enough space
297 * allocated to store the PRP list.
300 void *private; /* For the use of the submitter of the I/O */
301 int npages; /* In the PRP list. 0 means small pool in use */
302 int offset; /* Of PRP list */
303 int nents; /* Used in scatterlist */
304 int length; /* Of data, in bytes */
305 dma_addr_t first_dma;
306 struct scatterlist sg[0];
309 static __le64 **iod_list(struct nvme_iod *iod)
311 return ((void *)iod) + iod->offset;
315 * Will slightly overestimate the number of pages needed. This is OK
316 * as it only leads to a small amount of wasted memory for the lifetime of
319 static int nvme_npages(unsigned size)
321 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
322 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
325 static struct nvme_iod *
326 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
328 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
329 sizeof(__le64 *) * nvme_npages(nbytes) +
330 sizeof(struct scatterlist) * nseg, gfp);
333 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
335 iod->length = nbytes;
341 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
343 const int last_prp = PAGE_SIZE / 8 - 1;
345 __le64 **list = iod_list(iod);
346 dma_addr_t prp_dma = iod->first_dma;
348 if (iod->npages == 0)
349 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
350 for (i = 0; i < iod->npages; i++) {
351 __le64 *prp_list = list[i];
352 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
353 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
354 prp_dma = next_prp_dma;
359 static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
361 struct nvme_queue *nvmeq = get_nvmeq(dev);
362 if (bio_list_empty(&nvmeq->sq_cong))
363 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
364 bio_list_add(&nvmeq->sq_cong, bio);
366 wake_up_process(nvme_thread);
369 static void bio_completion(struct nvme_dev *dev, void *ctx,
370 struct nvme_completion *cqe)
372 struct nvme_iod *iod = ctx;
373 struct bio *bio = iod->private;
374 u16 status = le16_to_cpup(&cqe->status) >> 1;
376 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
377 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
378 nvme_free_iod(dev, iod);
380 bio_endio(bio, -EIO);
381 } else if (bio->bi_vcnt > bio->bi_idx) {
382 requeue_bio(dev, bio);
388 /* length is in bytes. gfp flags indicates whether we may sleep. */
389 static int nvme_setup_prps(struct nvme_dev *dev,
390 struct nvme_common_command *cmd, struct nvme_iod *iod,
391 int total_len, gfp_t gfp)
393 struct dma_pool *pool;
394 int length = total_len;
395 struct scatterlist *sg = iod->sg;
396 int dma_len = sg_dma_len(sg);
397 u64 dma_addr = sg_dma_address(sg);
398 int offset = offset_in_page(dma_addr);
400 __le64 **list = iod_list(iod);
404 cmd->prp1 = cpu_to_le64(dma_addr);
405 length -= (PAGE_SIZE - offset);
409 dma_len -= (PAGE_SIZE - offset);
411 dma_addr += (PAGE_SIZE - offset);
414 dma_addr = sg_dma_address(sg);
415 dma_len = sg_dma_len(sg);
418 if (length <= PAGE_SIZE) {
419 cmd->prp2 = cpu_to_le64(dma_addr);
423 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
424 if (nprps <= (256 / 8)) {
425 pool = dev->prp_small_pool;
428 pool = dev->prp_page_pool;
432 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
434 cmd->prp2 = cpu_to_le64(dma_addr);
436 return (total_len - length) + PAGE_SIZE;
439 iod->first_dma = prp_dma;
440 cmd->prp2 = cpu_to_le64(prp_dma);
443 if (i == PAGE_SIZE / 8) {
444 __le64 *old_prp_list = prp_list;
445 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
447 return total_len - length;
448 list[iod->npages++] = prp_list;
449 prp_list[0] = old_prp_list[i - 1];
450 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
453 prp_list[i++] = cpu_to_le64(dma_addr);
454 dma_len -= PAGE_SIZE;
455 dma_addr += PAGE_SIZE;
463 dma_addr = sg_dma_address(sg);
464 dma_len = sg_dma_len(sg);
470 /* NVMe scatterlists require no holes in the virtual address */
471 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
472 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
474 static int nvme_map_bio(struct device *dev, struct nvme_iod *iod,
475 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
477 struct bio_vec *bvec, *bvprv = NULL;
478 struct scatterlist *sg = NULL;
479 int i, old_idx, length = 0, nsegs = 0;
481 sg_init_table(iod->sg, psegs);
482 old_idx = bio->bi_idx;
483 bio_for_each_segment(bvec, bio, i) {
484 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
485 sg->length += bvec->bv_len;
487 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
489 sg = sg ? sg + 1 : iod->sg;
490 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
494 length += bvec->bv_len;
500 if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) {
501 bio->bi_idx = old_idx;
507 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
510 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
512 memset(cmnd, 0, sizeof(*cmnd));
513 cmnd->common.opcode = nvme_cmd_flush;
514 cmnd->common.command_id = cmdid;
515 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
517 if (++nvmeq->sq_tail == nvmeq->q_depth)
519 writel(nvmeq->sq_tail, nvmeq->q_db);
524 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
526 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
527 special_completion, NVME_IO_TIMEOUT);
528 if (unlikely(cmdid < 0))
531 return nvme_submit_flush(nvmeq, ns, cmdid);
535 * Called with local interrupts disabled and the q_lock held. May not sleep.
537 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
540 struct nvme_command *cmnd;
541 struct nvme_iod *iod;
542 enum dma_data_direction dma_dir;
543 int cmdid, length, result = -ENOMEM;
546 int psegs = bio_phys_segments(ns->queue, bio);
548 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
549 result = nvme_submit_flush_data(nvmeq, ns);
554 iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
560 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
561 if (unlikely(cmdid < 0))
564 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
565 return nvme_submit_flush(nvmeq, ns, cmdid);
568 if (bio->bi_rw & REQ_FUA)
569 control |= NVME_RW_FUA;
570 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
571 control |= NVME_RW_LR;
574 if (bio->bi_rw & REQ_RAHEAD)
575 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
577 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
579 memset(cmnd, 0, sizeof(*cmnd));
580 if (bio_data_dir(bio)) {
581 cmnd->rw.opcode = nvme_cmd_write;
582 dma_dir = DMA_TO_DEVICE;
584 cmnd->rw.opcode = nvme_cmd_read;
585 dma_dir = DMA_FROM_DEVICE;
588 result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs);
593 cmnd->rw.command_id = cmdid;
594 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
595 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
597 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
598 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
599 cmnd->rw.control = cpu_to_le16(control);
600 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
602 bio->bi_sector += length >> 9;
604 if (++nvmeq->sq_tail == nvmeq->q_depth)
606 writel(nvmeq->sq_tail, nvmeq->q_db);
611 nvme_free_iod(nvmeq->dev, iod);
617 * NB: return value of non-zero would mean that we were a stacking driver.
618 * make_request must always succeed.
620 static int nvme_make_request(struct request_queue *q, struct bio *bio)
622 struct nvme_ns *ns = q->queuedata;
623 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
626 spin_lock_irq(&nvmeq->q_lock);
627 if (bio_list_empty(&nvmeq->sq_cong))
628 result = nvme_submit_bio_queue(nvmeq, ns, bio);
629 if (unlikely(result)) {
630 if (bio_list_empty(&nvmeq->sq_cong))
631 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
632 bio_list_add(&nvmeq->sq_cong, bio);
635 spin_unlock_irq(&nvmeq->q_lock);
641 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
645 head = nvmeq->cq_head;
646 phase = nvmeq->cq_phase;
650 nvme_completion_fn fn;
651 struct nvme_completion cqe = nvmeq->cqes[head];
652 if ((le16_to_cpu(cqe.status) & 1) != phase)
654 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
655 if (++head == nvmeq->q_depth) {
660 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
661 fn(nvmeq->dev, ctx, &cqe);
664 /* If the controller ignores the cq head doorbell and continuously
665 * writes to the queue, it is theoretically possible to wrap around
666 * the queue twice and mistakenly return IRQ_NONE. Linux only
667 * requires that 0.1% of your interrupts are handled, so this isn't
670 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
673 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
674 nvmeq->cq_head = head;
675 nvmeq->cq_phase = phase;
680 static irqreturn_t nvme_irq(int irq, void *data)
683 struct nvme_queue *nvmeq = data;
684 spin_lock(&nvmeq->q_lock);
685 result = nvme_process_cq(nvmeq);
686 spin_unlock(&nvmeq->q_lock);
690 static irqreturn_t nvme_irq_check(int irq, void *data)
692 struct nvme_queue *nvmeq = data;
693 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
694 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
696 return IRQ_WAKE_THREAD;
699 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
701 spin_lock_irq(&nvmeq->q_lock);
702 cancel_cmdid(nvmeq, cmdid, NULL);
703 spin_unlock_irq(&nvmeq->q_lock);
706 struct sync_cmd_info {
707 struct task_struct *task;
712 static void sync_completion(struct nvme_dev *dev, void *ctx,
713 struct nvme_completion *cqe)
715 struct sync_cmd_info *cmdinfo = ctx;
716 cmdinfo->result = le32_to_cpup(&cqe->result);
717 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
718 wake_up_process(cmdinfo->task);
722 * Returns 0 on success. If the result is negative, it's a Linux error code;
723 * if the result is positive, it's an NVM Express status code
725 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
726 struct nvme_command *cmd, u32 *result, unsigned timeout)
729 struct sync_cmd_info cmdinfo;
731 cmdinfo.task = current;
732 cmdinfo.status = -EINTR;
734 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
738 cmd->common.command_id = cmdid;
740 set_current_state(TASK_KILLABLE);
741 nvme_submit_cmd(nvmeq, cmd);
744 if (cmdinfo.status == -EINTR) {
745 nvme_abort_command(nvmeq, cmdid);
750 *result = cmdinfo.result;
752 return cmdinfo.status;
755 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
758 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
761 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
764 struct nvme_command c;
766 memset(&c, 0, sizeof(c));
767 c.delete_queue.opcode = opcode;
768 c.delete_queue.qid = cpu_to_le16(id);
770 status = nvme_submit_admin_cmd(dev, &c, NULL);
776 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
777 struct nvme_queue *nvmeq)
780 struct nvme_command c;
781 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
783 memset(&c, 0, sizeof(c));
784 c.create_cq.opcode = nvme_admin_create_cq;
785 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
786 c.create_cq.cqid = cpu_to_le16(qid);
787 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
788 c.create_cq.cq_flags = cpu_to_le16(flags);
789 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
791 status = nvme_submit_admin_cmd(dev, &c, NULL);
797 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
798 struct nvme_queue *nvmeq)
801 struct nvme_command c;
802 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
804 memset(&c, 0, sizeof(c));
805 c.create_sq.opcode = nvme_admin_create_sq;
806 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
807 c.create_sq.sqid = cpu_to_le16(qid);
808 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
809 c.create_sq.sq_flags = cpu_to_le16(flags);
810 c.create_sq.cqid = cpu_to_le16(qid);
812 status = nvme_submit_admin_cmd(dev, &c, NULL);
818 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
820 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
823 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
825 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
828 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
831 struct nvme_command c;
833 memset(&c, 0, sizeof(c));
834 c.identify.opcode = nvme_admin_identify;
835 c.identify.nsid = cpu_to_le32(nsid);
836 c.identify.prp1 = cpu_to_le64(dma_addr);
837 c.identify.cns = cpu_to_le32(cns);
839 return nvme_submit_admin_cmd(dev, &c, NULL);
842 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
843 unsigned nsid, dma_addr_t dma_addr)
845 struct nvme_command c;
847 memset(&c, 0, sizeof(c));
848 c.features.opcode = nvme_admin_get_features;
849 c.features.nsid = cpu_to_le32(nsid);
850 c.features.prp1 = cpu_to_le64(dma_addr);
851 c.features.fid = cpu_to_le32(fid);
853 return nvme_submit_admin_cmd(dev, &c, NULL);
856 static int nvme_set_features(struct nvme_dev *dev, unsigned fid,
857 unsigned dword11, dma_addr_t dma_addr, u32 *result)
859 struct nvme_command c;
861 memset(&c, 0, sizeof(c));
862 c.features.opcode = nvme_admin_set_features;
863 c.features.prp1 = cpu_to_le64(dma_addr);
864 c.features.fid = cpu_to_le32(fid);
865 c.features.dword11 = cpu_to_le32(dword11);
867 return nvme_submit_admin_cmd(dev, &c, result);
870 static void nvme_free_queue(struct nvme_dev *dev, int qid)
872 struct nvme_queue *nvmeq = dev->queues[qid];
873 int vector = dev->entry[nvmeq->cq_vector].vector;
875 irq_set_affinity_hint(vector, NULL);
876 free_irq(vector, nvmeq);
878 /* Don't tell the adapter to delete the admin queue */
880 adapter_delete_sq(dev, qid);
881 adapter_delete_cq(dev, qid);
884 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
885 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
886 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
887 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
891 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
892 int depth, int vector)
894 struct device *dmadev = &dev->pci_dev->dev;
895 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
896 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
900 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
901 &nvmeq->cq_dma_addr, GFP_KERNEL);
904 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
906 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
907 &nvmeq->sq_dma_addr, GFP_KERNEL);
911 nvmeq->q_dmadev = dmadev;
913 spin_lock_init(&nvmeq->q_lock);
916 init_waitqueue_head(&nvmeq->sq_full);
917 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
918 bio_list_init(&nvmeq->sq_cong);
919 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
920 nvmeq->q_depth = depth;
921 nvmeq->cq_vector = vector;
926 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
933 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
936 if (use_threaded_interrupts)
937 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
938 nvme_irq_check, nvme_irq,
939 IRQF_DISABLED | IRQF_SHARED,
941 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
942 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
945 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
946 int qid, int cq_size, int vector)
949 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
952 return ERR_PTR(-ENOMEM);
954 result = adapter_alloc_cq(dev, qid, nvmeq);
958 result = adapter_alloc_sq(dev, qid, nvmeq);
962 result = queue_request_irq(dev, nvmeq, "nvme");
969 adapter_delete_sq(dev, qid);
971 adapter_delete_cq(dev, qid);
973 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
974 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
975 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
976 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
978 return ERR_PTR(result);
981 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
986 unsigned long timeout;
987 struct nvme_queue *nvmeq;
989 dev->dbs = ((void __iomem *)dev->bar) + 4096;
991 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
995 aqa = nvmeq->q_depth - 1;
998 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
999 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1000 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1001 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1003 writel(0, &dev->bar->cc);
1004 writel(aqa, &dev->bar->aqa);
1005 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1006 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1007 writel(dev->ctrl_config, &dev->bar->cc);
1009 cap = readq(&dev->bar->cap);
1010 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1011 dev->db_stride = NVME_CAP_STRIDE(cap);
1013 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
1015 if (fatal_signal_pending(current))
1017 if (time_after(jiffies, timeout)) {
1018 dev_err(&dev->pci_dev->dev,
1019 "Device not ready; aborting initialisation\n");
1024 result = queue_request_irq(dev, nvmeq, "nvme admin");
1025 dev->queues[0] = nvmeq;
1029 static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1030 unsigned long addr, unsigned length)
1032 int i, err, count, nents, offset;
1033 struct scatterlist *sg;
1034 struct page **pages;
1035 struct nvme_iod *iod;
1038 return ERR_PTR(-EINVAL);
1040 return ERR_PTR(-EINVAL);
1042 offset = offset_in_page(addr);
1043 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1044 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1046 err = get_user_pages_fast(addr, count, 1, pages);
1053 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1055 sg_init_table(sg, count);
1056 for (i = 0; i < count; i++) {
1057 sg_set_page(&sg[i], pages[i],
1058 min_t(int, length, PAGE_SIZE - offset), offset);
1059 length -= (PAGE_SIZE - offset);
1062 sg_mark_end(&sg[i - 1]);
1066 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1067 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1077 for (i = 0; i < count; i++)
1080 return ERR_PTR(err);
1083 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1084 struct nvme_iod *iod)
1088 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1089 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1091 for (i = 0; i < iod->nents; i++)
1092 put_page(sg_page(&iod->sg[i]));
1095 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1097 struct nvme_dev *dev = ns->dev;
1098 struct nvme_queue *nvmeq;
1099 struct nvme_user_io io;
1100 struct nvme_command c;
1103 struct nvme_iod *iod;
1105 if (copy_from_user(&io, uio, sizeof(io)))
1107 length = (io.nblocks + 1) << ns->lba_shift;
1109 switch (io.opcode) {
1110 case nvme_cmd_write:
1112 case nvme_cmd_compare:
1113 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1120 return PTR_ERR(iod);
1122 memset(&c, 0, sizeof(c));
1123 c.rw.opcode = io.opcode;
1124 c.rw.flags = io.flags;
1125 c.rw.nsid = cpu_to_le32(ns->ns_id);
1126 c.rw.slba = cpu_to_le64(io.slba);
1127 c.rw.length = cpu_to_le16(io.nblocks);
1128 c.rw.control = cpu_to_le16(io.control);
1129 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1130 c.rw.reftag = io.reftag;
1131 c.rw.apptag = io.apptag;
1132 c.rw.appmask = io.appmask;
1134 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1136 nvmeq = get_nvmeq(dev);
1138 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1139 * disabled. We may be preempted at any point, and be rescheduled
1140 * to a different CPU. That will cause cacheline bouncing, but no
1141 * additional races since q_lock already protects against other CPUs.
1144 if (length != (io.nblocks + 1) << ns->lba_shift)
1147 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1149 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1150 nvme_free_iod(dev, iod);
1154 static int nvme_user_admin_cmd(struct nvme_dev *dev,
1155 struct nvme_admin_cmd __user *ucmd)
1157 struct nvme_admin_cmd cmd;
1158 struct nvme_command c;
1160 struct nvme_iod *iod;
1162 if (!capable(CAP_SYS_ADMIN))
1164 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1167 memset(&c, 0, sizeof(c));
1168 c.common.opcode = cmd.opcode;
1169 c.common.flags = cmd.flags;
1170 c.common.nsid = cpu_to_le32(cmd.nsid);
1171 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1172 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1173 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1174 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1175 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1176 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1177 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1178 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1180 length = cmd.data_len;
1182 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1185 return PTR_ERR(iod);
1186 length = nvme_setup_prps(dev, &c.common, iod, length,
1190 if (length != cmd.data_len)
1193 status = nvme_submit_admin_cmd(dev, &c, NULL);
1196 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1197 nvme_free_iod(dev, iod);
1202 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1205 struct nvme_ns *ns = bdev->bd_disk->private_data;
1210 case NVME_IOCTL_ADMIN_CMD:
1211 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1212 case NVME_IOCTL_SUBMIT_IO:
1213 return nvme_submit_io(ns, (void __user *)arg);
1219 static const struct block_device_operations nvme_fops = {
1220 .owner = THIS_MODULE,
1221 .ioctl = nvme_ioctl,
1222 .compat_ioctl = nvme_ioctl,
1225 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1227 int depth = nvmeq->q_depth - 1;
1228 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1229 unsigned long now = jiffies;
1232 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1234 nvme_completion_fn fn;
1235 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1237 if (!time_after(now, info[cmdid].timeout))
1239 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1240 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1241 fn(nvmeq->dev, ctx, &cqe);
1245 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1247 while (bio_list_peek(&nvmeq->sq_cong)) {
1248 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1249 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1250 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1251 bio_list_add_head(&nvmeq->sq_cong, bio);
1254 if (bio_list_empty(&nvmeq->sq_cong))
1255 remove_wait_queue(&nvmeq->sq_full,
1256 &nvmeq->sq_cong_wait);
1260 static int nvme_kthread(void *data)
1262 struct nvme_dev *dev;
1264 while (!kthread_should_stop()) {
1265 __set_current_state(TASK_RUNNING);
1266 spin_lock(&dev_list_lock);
1267 list_for_each_entry(dev, &dev_list, node) {
1269 for (i = 0; i < dev->queue_count; i++) {
1270 struct nvme_queue *nvmeq = dev->queues[i];
1273 spin_lock_irq(&nvmeq->q_lock);
1274 if (nvme_process_cq(nvmeq))
1275 printk("process_cq did something\n");
1276 nvme_timeout_ios(nvmeq);
1277 nvme_resubmit_bios(nvmeq);
1278 spin_unlock_irq(&nvmeq->q_lock);
1281 spin_unlock(&dev_list_lock);
1282 set_current_state(TASK_INTERRUPTIBLE);
1283 schedule_timeout(HZ);
1288 static DEFINE_IDA(nvme_index_ida);
1290 static int nvme_get_ns_idx(void)
1295 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1298 spin_lock(&dev_list_lock);
1299 error = ida_get_new(&nvme_index_ida, &index);
1300 spin_unlock(&dev_list_lock);
1301 } while (error == -EAGAIN);
1308 static void nvme_put_ns_idx(int index)
1310 spin_lock(&dev_list_lock);
1311 ida_remove(&nvme_index_ida, index);
1312 spin_unlock(&dev_list_lock);
1315 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1316 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1319 struct gendisk *disk;
1322 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1325 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1328 ns->queue = blk_alloc_queue(GFP_KERNEL);
1331 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1332 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1333 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1334 /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1335 blk_queue_make_request(ns->queue, nvme_make_request);
1337 ns->queue->queuedata = ns;
1339 disk = alloc_disk(NVME_MINORS);
1341 goto out_free_queue;
1344 lbaf = id->flbas & 0xf;
1345 ns->lba_shift = id->lbaf[lbaf].ds;
1346 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1348 disk->major = nvme_major;
1349 disk->minors = NVME_MINORS;
1350 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1351 disk->fops = &nvme_fops;
1352 disk->private_data = ns;
1353 disk->queue = ns->queue;
1354 disk->driverfs_dev = &dev->pci_dev->dev;
1355 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1356 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1361 blk_cleanup_queue(ns->queue);
1367 static void nvme_ns_free(struct nvme_ns *ns)
1369 int index = ns->disk->first_minor / NVME_MINORS;
1371 nvme_put_ns_idx(index);
1372 blk_cleanup_queue(ns->queue);
1376 static int set_queue_count(struct nvme_dev *dev, int count)
1380 u32 q_count = (count - 1) | ((count - 1) << 16);
1382 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1386 return min(result & 0xffff, result >> 16) + 1;
1389 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1391 int result, cpu, i, nr_io_queues, db_bar_size;
1393 nr_io_queues = num_online_cpus();
1394 result = set_queue_count(dev, nr_io_queues);
1397 if (result < nr_io_queues)
1398 nr_io_queues = result;
1400 /* Deregister the admin queue's interrupt */
1401 free_irq(dev->entry[0].vector, dev->queues[0]);
1403 db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1404 if (db_bar_size > 8192) {
1406 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1408 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1409 dev->queues[0]->q_db = dev->dbs;
1412 for (i = 0; i < nr_io_queues; i++)
1413 dev->entry[i].entry = i;
1415 result = pci_enable_msix(dev->pci_dev, dev->entry,
1419 } else if (result > 0) {
1420 nr_io_queues = result;
1428 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1429 /* XXX: handle failure here */
1431 cpu = cpumask_first(cpu_online_mask);
1432 for (i = 0; i < nr_io_queues; i++) {
1433 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1434 cpu = cpumask_next(cpu, cpu_online_mask);
1437 for (i = 0; i < nr_io_queues; i++) {
1438 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1440 if (IS_ERR(dev->queues[i + 1]))
1441 return PTR_ERR(dev->queues[i + 1]);
1445 for (; i < num_possible_cpus(); i++) {
1446 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1447 dev->queues[i + 1] = dev->queues[target + 1];
1453 static void nvme_free_queues(struct nvme_dev *dev)
1457 for (i = dev->queue_count - 1; i >= 0; i--)
1458 nvme_free_queue(dev, i);
1461 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1464 struct nvme_ns *ns, *next;
1465 struct nvme_id_ctrl *ctrl;
1466 struct nvme_id_ns *id_ns;
1468 dma_addr_t dma_addr;
1470 res = nvme_setup_io_queues(dev);
1474 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1477 res = nvme_identify(dev, 0, 1, dma_addr);
1484 nn = le32_to_cpup(&ctrl->nn);
1485 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1486 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1487 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1490 for (i = 1; i <= nn; i++) {
1491 res = nvme_identify(dev, i, 0, dma_addr);
1495 if (id_ns->ncap == 0)
1498 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1503 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1505 list_add_tail(&ns->list, &dev->namespaces);
1507 list_for_each_entry(ns, &dev->namespaces, list)
1513 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1514 list_del(&ns->list);
1519 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1523 static int nvme_dev_remove(struct nvme_dev *dev)
1525 struct nvme_ns *ns, *next;
1527 spin_lock(&dev_list_lock);
1528 list_del(&dev->node);
1529 spin_unlock(&dev_list_lock);
1531 /* TODO: wait all I/O finished or cancel them */
1533 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1534 list_del(&ns->list);
1535 del_gendisk(ns->disk);
1539 nvme_free_queues(dev);
1544 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1546 struct device *dmadev = &dev->pci_dev->dev;
1547 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1548 PAGE_SIZE, PAGE_SIZE, 0);
1549 if (!dev->prp_page_pool)
1552 /* Optimisation for I/Os between 4k and 128k */
1553 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1555 if (!dev->prp_small_pool) {
1556 dma_pool_destroy(dev->prp_page_pool);
1562 static void nvme_release_prp_pools(struct nvme_dev *dev)
1564 dma_pool_destroy(dev->prp_page_pool);
1565 dma_pool_destroy(dev->prp_small_pool);
1568 /* XXX: Use an ida or something to let remove / add work correctly */
1569 static void nvme_set_instance(struct nvme_dev *dev)
1571 static int instance;
1572 dev->instance = instance++;
1575 static void nvme_release_instance(struct nvme_dev *dev)
1579 static int __devinit nvme_probe(struct pci_dev *pdev,
1580 const struct pci_device_id *id)
1582 int bars, result = -ENOMEM;
1583 struct nvme_dev *dev;
1585 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1588 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1592 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1597 if (pci_enable_device_mem(pdev))
1599 pci_set_master(pdev);
1600 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1601 if (pci_request_selected_regions(pdev, bars, "nvme"))
1604 INIT_LIST_HEAD(&dev->namespaces);
1605 dev->pci_dev = pdev;
1606 pci_set_drvdata(pdev, dev);
1607 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1608 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1609 nvme_set_instance(dev);
1610 dev->entry[0].vector = pdev->irq;
1612 result = nvme_setup_prp_pools(dev);
1616 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1622 result = nvme_configure_admin_queue(dev);
1627 spin_lock(&dev_list_lock);
1628 list_add(&dev->node, &dev_list);
1629 spin_unlock(&dev_list_lock);
1631 result = nvme_dev_add(dev);
1638 spin_lock(&dev_list_lock);
1639 list_del(&dev->node);
1640 spin_unlock(&dev_list_lock);
1642 nvme_free_queues(dev);
1646 pci_disable_msix(pdev);
1647 nvme_release_instance(dev);
1648 nvme_release_prp_pools(dev);
1650 pci_disable_device(pdev);
1651 pci_release_regions(pdev);
1659 static void __devexit nvme_remove(struct pci_dev *pdev)
1661 struct nvme_dev *dev = pci_get_drvdata(pdev);
1662 nvme_dev_remove(dev);
1663 pci_disable_msix(pdev);
1665 nvme_release_instance(dev);
1666 nvme_release_prp_pools(dev);
1667 pci_disable_device(pdev);
1668 pci_release_regions(pdev);
1674 /* These functions are yet to be implemented */
1675 #define nvme_error_detected NULL
1676 #define nvme_dump_registers NULL
1677 #define nvme_link_reset NULL
1678 #define nvme_slot_reset NULL
1679 #define nvme_error_resume NULL
1680 #define nvme_suspend NULL
1681 #define nvme_resume NULL
1683 static struct pci_error_handlers nvme_err_handler = {
1684 .error_detected = nvme_error_detected,
1685 .mmio_enabled = nvme_dump_registers,
1686 .link_reset = nvme_link_reset,
1687 .slot_reset = nvme_slot_reset,
1688 .resume = nvme_error_resume,
1691 /* Move to pci_ids.h later */
1692 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1694 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1695 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1698 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1700 static struct pci_driver nvme_driver = {
1702 .id_table = nvme_id_table,
1703 .probe = nvme_probe,
1704 .remove = __devexit_p(nvme_remove),
1705 .suspend = nvme_suspend,
1706 .resume = nvme_resume,
1707 .err_handler = &nvme_err_handler,
1710 static int __init nvme_init(void)
1712 int result = -EBUSY;
1714 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1715 if (IS_ERR(nvme_thread))
1716 return PTR_ERR(nvme_thread);
1718 result = register_blkdev(nvme_major, "nvme");
1721 else if (result > 0)
1722 nvme_major = result;
1724 result = pci_register_driver(&nvme_driver);
1726 goto unregister_blkdev;
1730 unregister_blkdev(nvme_major, "nvme");
1732 kthread_stop(nvme_thread);
1736 static void __exit nvme_exit(void)
1738 pci_unregister_driver(&nvme_driver);
1739 unregister_blkdev(nvme_major, "nvme");
1740 kthread_stop(nvme_thread);
1743 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1744 MODULE_LICENSE("GPL");
1745 MODULE_VERSION("0.8");
1746 module_init(nvme_init);
1747 module_exit(nvme_exit);