2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/pci.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
36 #include <linux/types.h>
37 #include <linux/version.h>
39 #define NVME_Q_DEPTH 1024
40 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
41 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42 #define NVME_MINORS 64
44 static int nvme_major;
45 module_param(nvme_major, int, 0);
47 static int use_threaded_interrupts;
48 module_param(use_threaded_interrupts, int, 0);
51 * Represents an NVM Express device. Each nvme_dev is a PCI function.
54 struct nvme_queue **queues;
56 struct pci_dev *pci_dev;
60 struct msix_entry *entry;
61 struct nvme_bar __iomem *bar;
62 struct list_head namespaces;
69 * An NVM Express namespace is equivalent to a SCSI LUN
72 struct list_head list;
75 struct request_queue *queue;
83 * An NVM Express queue. Each device has at least two (one for admin
84 * commands and one for I/O commands).
87 struct device *q_dmadev;
89 struct nvme_command *sq_cmds;
90 volatile struct nvme_completion *cqes;
91 dma_addr_t sq_dma_addr;
92 dma_addr_t cq_dma_addr;
93 wait_queue_head_t sq_full;
94 struct bio_list sq_cong;
102 unsigned long cmdid_data[];
106 * Check we didin't inadvertently grow the command struct
108 static inline void _nvme_check_size(void)
110 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
111 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
112 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
113 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
114 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
115 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
116 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
117 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
118 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
122 * alloc_cmdid - Allocate a Command ID
123 * @param nvmeq The queue that will be used for this command
124 * @param ctx A pointer that will be passed to the handler
125 * @param handler The ID of the handler to call
127 * Allocate a Command ID for a queue. The data passed in will
128 * be passed to the completion handler. This is implemented by using
129 * the bottom two bits of the ctx pointer to store the handler ID.
130 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
131 * We can change this if it becomes a problem.
133 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
135 int depth = nvmeq->q_depth;
136 unsigned long data = (unsigned long)ctx | handler;
139 BUG_ON((unsigned long)ctx & 3);
142 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
145 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
147 nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
151 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
155 wait_event_killable(nvmeq->sq_full,
156 (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
157 return (cmdid < 0) ? -EINTR : cmdid;
160 /* If you need more than four handlers, you'll need to change how
161 * alloc_cmdid and nvme_process_cq work. Also, aborted commands take
162 * the sync_completion path (if they complete), so don't put anything
166 sync_completion_id = 0,
170 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
174 data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)];
175 clear_bit(cmdid, nvmeq->cmdid_data);
176 wake_up(&nvmeq->sq_full);
180 static void clear_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
182 nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)] = 0;
185 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
187 int qid, cpu = get_cpu();
188 if (cpu < ns->dev->queue_count)
191 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
192 return ns->dev->queues[qid];
195 static void put_nvmeq(struct nvme_queue *nvmeq)
201 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
202 * @nvmeq: The queue to use
203 * @cmd: The command to send
205 * Safe to use from interrupt context
207 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
211 /* XXX: Need to check tail isn't going to overrun head */
212 spin_lock_irqsave(&nvmeq->q_lock, flags);
213 tail = nvmeq->sq_tail;
214 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
215 writel(tail, nvmeq->q_db);
216 if (++tail == nvmeq->q_depth)
218 nvmeq->sq_tail = tail;
219 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
224 struct nvme_req_info {
227 struct scatterlist sg[0];
230 /* XXX: use a mempool */
231 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
233 return kmalloc(sizeof(struct nvme_req_info) +
234 sizeof(struct scatterlist) * nseg, gfp);
237 static void free_info(struct nvme_req_info *info)
242 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
243 struct nvme_completion *cqe)
245 struct nvme_req_info *info = ctx;
246 struct bio *bio = info->bio;
247 u16 status = le16_to_cpup(&cqe->status) >> 1;
249 dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
250 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
252 bio_endio(bio, status ? -EIO : 0);
255 /* length is in bytes */
256 static void nvme_setup_prps(struct nvme_common_command *cmd,
257 struct scatterlist *sg, int length)
259 int dma_len = sg_dma_len(sg);
260 u64 dma_addr = sg_dma_address(sg);
261 int offset = offset_in_page(dma_addr);
263 cmd->prp1 = cpu_to_le64(dma_addr);
264 length -= (PAGE_SIZE - offset);
268 dma_len -= (PAGE_SIZE - offset);
270 dma_addr += (PAGE_SIZE - offset);
273 dma_addr = sg_dma_address(sg);
274 dma_len = sg_dma_len(sg);
277 if (length <= PAGE_SIZE) {
278 cmd->prp2 = cpu_to_le64(dma_addr);
282 /* XXX: support PRP lists */
285 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
286 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
288 struct bio_vec *bvec;
289 struct scatterlist *sg = info->sg;
292 sg_init_table(sg, psegs);
293 bio_for_each_segment(bvec, bio, i) {
294 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
295 /* XXX: handle non-mergable here */
300 return dma_map_sg(dev, info->sg, info->nents, dma_dir);
303 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
306 struct nvme_command *cmnd;
307 struct nvme_req_info *info;
308 enum dma_data_direction dma_dir;
313 int psegs = bio_phys_segments(ns->queue, bio);
315 info = alloc_info(psegs, GFP_NOIO);
320 cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
321 if (unlikely(cmdid < 0))
325 if (bio->bi_rw & REQ_FUA)
326 control |= NVME_RW_FUA;
327 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
328 control |= NVME_RW_LR;
331 if (bio->bi_rw & REQ_RAHEAD)
332 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
334 spin_lock_irqsave(&nvmeq->q_lock, flags);
335 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
337 memset(cmnd, 0, sizeof(*cmnd));
338 if (bio_data_dir(bio)) {
339 cmnd->rw.opcode = nvme_cmd_write;
340 dma_dir = DMA_TO_DEVICE;
342 cmnd->rw.opcode = nvme_cmd_read;
343 dma_dir = DMA_FROM_DEVICE;
346 nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
349 cmnd->rw.command_id = cmdid;
350 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
351 nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
352 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
353 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
354 cmnd->rw.control = cpu_to_le16(control);
355 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
357 writel(nvmeq->sq_tail, nvmeq->q_db);
358 if (++nvmeq->sq_tail == nvmeq->q_depth)
361 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
372 * NB: return value of non-zero would mean that we were a stacking driver.
373 * make_request must always succeed.
375 static int nvme_make_request(struct request_queue *q, struct bio *bio)
377 struct nvme_ns *ns = q->queuedata;
378 struct nvme_queue *nvmeq = get_nvmeq(ns);
380 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
381 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
382 bio_list_add(&nvmeq->sq_cong, bio);
389 struct sync_cmd_info {
390 struct task_struct *task;
395 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
396 struct nvme_completion *cqe)
398 struct sync_cmd_info *cmdinfo = ctx;
400 return; /* Command aborted */
401 cmdinfo->result = le32_to_cpup(&cqe->result);
402 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
403 wake_up_process(cmdinfo->task);
406 typedef void (*completion_fn)(struct nvme_queue *, void *,
407 struct nvme_completion *);
409 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
413 static const completion_fn completions[4] = {
414 [sync_completion_id] = sync_completion,
415 [bio_completion_id] = bio_completion,
418 head = nvmeq->cq_head;
419 phase = nvmeq->cq_phase;
424 unsigned char handler;
425 struct nvme_completion cqe = nvmeq->cqes[head];
426 if ((le16_to_cpu(cqe.status) & 1) != phase)
428 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
429 if (++head == nvmeq->q_depth) {
434 data = free_cmdid(nvmeq, cqe.command_id);
436 ptr = (void *)(data & ~3UL);
437 completions[handler](nvmeq, ptr, &cqe);
440 /* If the controller ignores the cq head doorbell and continuously
441 * writes to the queue, it is theoretically possible to wrap around
442 * the queue twice and mistakenly return IRQ_NONE. Linux only
443 * requires that 0.1% of your interrupts are handled, so this isn't
446 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
449 writel(head, nvmeq->q_db + 1);
450 nvmeq->cq_head = head;
451 nvmeq->cq_phase = phase;
456 static irqreturn_t nvme_irq(int irq, void *data)
458 return nvme_process_cq(data);
461 static irqreturn_t nvme_irq_thread(int irq, void *data)
464 struct nvme_queue *nvmeq = data;
465 spin_lock(&nvmeq->q_lock);
466 result = nvme_process_cq(nvmeq);
467 spin_unlock(&nvmeq->q_lock);
471 static irqreturn_t nvme_irq_check(int irq, void *data)
473 struct nvme_queue *nvmeq = data;
474 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
475 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
477 return IRQ_WAKE_THREAD;
480 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
482 spin_lock_irq(&nvmeq->q_lock);
483 clear_cmdid_data(nvmeq, cmdid);
484 spin_unlock_irq(&nvmeq->q_lock);
488 * Returns 0 on success. If the result is negative, it's a Linux error code;
489 * if the result is positive, it's an NVM Express status code
491 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
492 struct nvme_command *cmd, u32 *result)
495 struct sync_cmd_info cmdinfo;
497 cmdinfo.task = current;
498 cmdinfo.status = -EINTR;
500 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id);
503 cmd->common.command_id = cmdid;
505 set_current_state(TASK_KILLABLE);
506 nvme_submit_cmd(nvmeq, cmd);
509 if (cmdinfo.status == -EINTR) {
510 nvme_abort_command(nvmeq, cmdid);
515 *result = cmdinfo.result;
517 return cmdinfo.status;
520 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
523 return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
526 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
529 struct nvme_command c;
531 memset(&c, 0, sizeof(c));
532 c.delete_queue.opcode = opcode;
533 c.delete_queue.qid = cpu_to_le16(id);
535 status = nvme_submit_admin_cmd(dev, &c, NULL);
541 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
542 struct nvme_queue *nvmeq)
545 struct nvme_command c;
546 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
548 memset(&c, 0, sizeof(c));
549 c.create_cq.opcode = nvme_admin_create_cq;
550 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
551 c.create_cq.cqid = cpu_to_le16(qid);
552 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
553 c.create_cq.cq_flags = cpu_to_le16(flags);
554 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
556 status = nvme_submit_admin_cmd(dev, &c, NULL);
562 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
563 struct nvme_queue *nvmeq)
566 struct nvme_command c;
567 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
569 memset(&c, 0, sizeof(c));
570 c.create_sq.opcode = nvme_admin_create_sq;
571 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
572 c.create_sq.sqid = cpu_to_le16(qid);
573 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
574 c.create_sq.sq_flags = cpu_to_le16(flags);
575 c.create_sq.cqid = cpu_to_le16(qid);
577 status = nvme_submit_admin_cmd(dev, &c, NULL);
583 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
585 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
588 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
590 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
593 static void nvme_free_queue(struct nvme_dev *dev, int qid)
595 struct nvme_queue *nvmeq = dev->queues[qid];
597 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
599 /* Don't tell the adapter to delete the admin queue */
601 adapter_delete_sq(dev, qid);
602 adapter_delete_cq(dev, qid);
605 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
606 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
607 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
608 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
612 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
613 int depth, int vector)
615 struct device *dmadev = &dev->pci_dev->dev;
616 unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
617 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
621 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
622 &nvmeq->cq_dma_addr, GFP_KERNEL);
625 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
627 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
628 &nvmeq->sq_dma_addr, GFP_KERNEL);
632 nvmeq->q_dmadev = dmadev;
633 spin_lock_init(&nvmeq->q_lock);
636 init_waitqueue_head(&nvmeq->sq_full);
637 bio_list_init(&nvmeq->sq_cong);
638 nvmeq->q_db = &dev->dbs[qid * 2];
639 nvmeq->q_depth = depth;
640 nvmeq->cq_vector = vector;
645 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
652 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
655 if (use_threaded_interrupts)
656 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
657 nvme_irq_check, nvme_irq_thread,
658 IRQF_DISABLED | IRQF_SHARED,
660 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
661 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
664 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
665 int qid, int cq_size, int vector)
668 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
673 result = adapter_alloc_cq(dev, qid, nvmeq);
677 result = adapter_alloc_sq(dev, qid, nvmeq);
681 result = queue_request_irq(dev, nvmeq, "nvme");
688 adapter_delete_sq(dev, qid);
690 adapter_delete_cq(dev, qid);
692 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
693 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
694 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
695 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
700 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
704 struct nvme_queue *nvmeq;
706 dev->dbs = ((void __iomem *)dev->bar) + 4096;
708 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
712 aqa = nvmeq->q_depth - 1;
715 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
716 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
717 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
719 writel(0, &dev->bar->cc);
720 writel(aqa, &dev->bar->aqa);
721 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
722 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
723 writel(dev->ctrl_config, &dev->bar->cc);
725 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
727 if (fatal_signal_pending(current))
731 result = queue_request_irq(dev, nvmeq, "nvme admin");
732 dev->queues[0] = nvmeq;
736 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
737 unsigned long addr, unsigned length,
738 struct scatterlist **sgp)
740 int i, err, count, nents, offset;
741 struct scatterlist *sg;
749 offset = offset_in_page(addr);
750 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
751 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
753 err = get_user_pages_fast(addr, count, 1, pages);
760 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
761 sg_init_table(sg, count);
762 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
763 length -= (PAGE_SIZE - offset);
764 for (i = 1; i < count; i++) {
765 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
770 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
771 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
780 for (i = 0; i < count; i++)
786 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
787 unsigned long addr, int length,
788 struct scatterlist *sg, int nents)
792 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
793 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
795 for (i = 0; i < count; i++)
796 put_page(sg_page(&sg[i]));
799 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
800 unsigned long addr, unsigned length,
801 struct nvme_command *cmd)
804 struct scatterlist *sg;
806 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
809 nvme_setup_prps(&cmd->common, sg, length);
810 err = nvme_submit_admin_cmd(dev, cmd, NULL);
811 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
812 return err ? -EIO : 0;
815 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
817 struct nvme_command c;
819 memset(&c, 0, sizeof(c));
820 c.identify.opcode = nvme_admin_identify;
821 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
822 c.identify.cns = cpu_to_le32(cns);
824 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
827 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
829 struct nvme_command c;
831 memset(&c, 0, sizeof(c));
832 c.features.opcode = nvme_admin_get_features;
833 c.features.nsid = cpu_to_le32(ns->ns_id);
834 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
836 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
839 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
841 struct nvme_dev *dev = ns->dev;
842 struct nvme_queue *nvmeq;
843 struct nvme_user_io io;
844 struct nvme_command c;
848 struct scatterlist *sg;
850 if (copy_from_user(&io, uio, sizeof(io)))
852 length = io.nblocks << io.block_shift;
853 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
857 memset(&c, 0, sizeof(c));
858 c.rw.opcode = io.opcode;
859 c.rw.flags = io.flags;
860 c.rw.nsid = cpu_to_le32(io.nsid);
861 c.rw.slba = cpu_to_le64(io.slba);
862 c.rw.length = cpu_to_le16(io.nblocks - 1);
863 c.rw.control = cpu_to_le16(io.control);
864 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
865 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
866 c.rw.apptag = cpu_to_le16(io.apptag);
867 c.rw.appmask = cpu_to_le16(io.appmask);
869 nvme_setup_prps(&c.common, sg, length);
871 nvmeq = get_nvmeq(ns);
872 /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
873 * disabled. We may be preempted at any point, and be rescheduled
874 * to a different CPU. That will cause cacheline bouncing, but no
875 * additional races since q_lock already protects against other CPUs.
878 status = nvme_submit_sync_cmd(nvmeq, &c, &result);
880 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
881 put_user(result, &uio->result);
885 static int nvme_download_firmware(struct nvme_ns *ns,
886 struct nvme_dlfw __user *udlfw)
888 struct nvme_dev *dev = ns->dev;
889 struct nvme_dlfw dlfw;
890 struct nvme_command c;
892 struct scatterlist *sg;
894 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
896 if (dlfw.length >= (1 << 30))
899 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
903 memset(&c, 0, sizeof(c));
904 c.dlfw.opcode = nvme_admin_download_fw;
905 c.dlfw.numd = cpu_to_le32(dlfw.length);
906 c.dlfw.offset = cpu_to_le32(dlfw.offset);
907 nvme_setup_prps(&c.common, sg, dlfw.length * 4);
909 status = nvme_submit_admin_cmd(dev, &c, NULL);
910 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
914 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
916 struct nvme_dev *dev = ns->dev;
917 struct nvme_command c;
919 memset(&c, 0, sizeof(c));
920 c.common.opcode = nvme_admin_activate_fw;
921 c.common.rsvd10[0] = cpu_to_le32(arg);
923 return nvme_submit_admin_cmd(dev, &c, NULL);
926 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
929 struct nvme_ns *ns = bdev->bd_disk->private_data;
932 case NVME_IOCTL_IDENTIFY_NS:
933 return nvme_identify(ns, arg, 0);
934 case NVME_IOCTL_IDENTIFY_CTRL:
935 return nvme_identify(ns, arg, 1);
936 case NVME_IOCTL_GET_RANGE_TYPE:
937 return nvme_get_range_type(ns, arg);
938 case NVME_IOCTL_SUBMIT_IO:
939 return nvme_submit_io(ns, (void __user *)arg);
940 case NVME_IOCTL_DOWNLOAD_FW:
941 return nvme_download_firmware(ns, (void __user *)arg);
942 case NVME_IOCTL_ACTIVATE_FW:
943 return nvme_activate_firmware(ns, arg);
949 static const struct block_device_operations nvme_fops = {
950 .owner = THIS_MODULE,
954 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
955 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
958 struct gendisk *disk;
961 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
964 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
967 ns->queue = blk_alloc_queue(GFP_KERNEL);
970 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
971 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
972 blk_queue_make_request(ns->queue, nvme_make_request);
974 ns->queue->queuedata = ns;
976 disk = alloc_disk(NVME_MINORS);
981 lbaf = id->flbas & 0xf;
982 ns->lba_shift = id->lbaf[lbaf].ds;
984 disk->major = nvme_major;
985 disk->minors = NVME_MINORS;
986 disk->first_minor = NVME_MINORS * index;
987 disk->fops = &nvme_fops;
988 disk->private_data = ns;
989 disk->queue = ns->queue;
990 disk->driverfs_dev = &dev->pci_dev->dev;
991 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
992 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
997 blk_cleanup_queue(ns->queue);
1003 static void nvme_ns_free(struct nvme_ns *ns)
1006 blk_cleanup_queue(ns->queue);
1010 static int set_queue_count(struct nvme_dev *dev, int count)
1014 struct nvme_command c;
1015 u32 q_count = (count - 1) | ((count - 1) << 16);
1017 memset(&c, 0, sizeof(c));
1018 c.features.opcode = nvme_admin_get_features;
1019 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1020 c.features.dword11 = cpu_to_le32(q_count);
1022 status = nvme_submit_admin_cmd(dev, &c, &result);
1025 return min(result & 0xffff, result >> 16) + 1;
1028 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1030 int result, cpu, i, nr_queues;
1032 nr_queues = num_online_cpus();
1033 result = set_queue_count(dev, nr_queues);
1036 if (result < nr_queues)
1039 /* Deregister the admin queue's interrupt */
1040 free_irq(dev->entry[0].vector, dev->queues[0]);
1042 for (i = 0; i < nr_queues; i++)
1043 dev->entry[i].entry = i;
1045 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1048 } else if (result > 0) {
1057 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1058 /* XXX: handle failure here */
1060 cpu = cpumask_first(cpu_online_mask);
1061 for (i = 0; i < nr_queues; i++) {
1062 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1063 cpu = cpumask_next(cpu, cpu_online_mask);
1066 for (i = 0; i < nr_queues; i++) {
1067 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1069 if (!dev->queues[i + 1])
1077 static void nvme_free_queues(struct nvme_dev *dev)
1081 for (i = dev->queue_count - 1; i >= 0; i--)
1082 nvme_free_queue(dev, i);
1085 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1088 struct nvme_ns *ns, *next;
1089 struct nvme_id_ctrl *ctrl;
1091 dma_addr_t dma_addr;
1092 struct nvme_command cid, crt;
1094 res = nvme_setup_io_queues(dev);
1098 /* XXX: Switch to a SG list once prp2 works */
1099 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1102 memset(&cid, 0, sizeof(cid));
1103 cid.identify.opcode = nvme_admin_identify;
1104 cid.identify.nsid = 0;
1105 cid.identify.prp1 = cpu_to_le64(dma_addr);
1106 cid.identify.cns = cpu_to_le32(1);
1108 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1115 nn = le32_to_cpup(&ctrl->nn);
1116 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1117 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1118 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1120 cid.identify.cns = 0;
1121 memset(&crt, 0, sizeof(crt));
1122 crt.features.opcode = nvme_admin_get_features;
1123 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1124 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1126 for (i = 0; i < nn; i++) {
1127 cid.identify.nsid = cpu_to_le32(i);
1128 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1132 if (((struct nvme_id_ns *)id)->ncap == 0)
1135 crt.features.nsid = cpu_to_le32(i);
1136 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1140 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1142 list_add_tail(&ns->list, &dev->namespaces);
1144 list_for_each_entry(ns, &dev->namespaces, list)
1147 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1151 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1152 list_del(&ns->list);
1156 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1160 static int nvme_dev_remove(struct nvme_dev *dev)
1162 struct nvme_ns *ns, *next;
1164 /* TODO: wait all I/O finished or cancel them */
1166 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1167 list_del(&ns->list);
1168 del_gendisk(ns->disk);
1172 nvme_free_queues(dev);
1177 /* XXX: Use an ida or something to let remove / add work correctly */
1178 static void nvme_set_instance(struct nvme_dev *dev)
1180 static int instance;
1181 dev->instance = instance++;
1184 static void nvme_release_instance(struct nvme_dev *dev)
1188 static int __devinit nvme_probe(struct pci_dev *pdev,
1189 const struct pci_device_id *id)
1191 int bars, result = -ENOMEM;
1192 struct nvme_dev *dev;
1194 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1197 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1201 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1206 if (pci_enable_device_mem(pdev))
1208 pci_set_master(pdev);
1209 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1210 if (pci_request_selected_regions(pdev, bars, "nvme"))
1213 INIT_LIST_HEAD(&dev->namespaces);
1214 dev->pci_dev = pdev;
1215 pci_set_drvdata(pdev, dev);
1216 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1217 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1218 nvme_set_instance(dev);
1219 dev->entry[0].vector = pdev->irq;
1221 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1227 result = nvme_configure_admin_queue(dev);
1232 result = nvme_dev_add(dev);
1238 nvme_free_queues(dev);
1242 pci_disable_msix(pdev);
1243 nvme_release_instance(dev);
1245 pci_disable_device(pdev);
1246 pci_release_regions(pdev);
1254 static void __devexit nvme_remove(struct pci_dev *pdev)
1256 struct nvme_dev *dev = pci_get_drvdata(pdev);
1257 nvme_dev_remove(dev);
1258 pci_disable_msix(pdev);
1260 nvme_release_instance(dev);
1261 pci_disable_device(pdev);
1262 pci_release_regions(pdev);
1268 /* These functions are yet to be implemented */
1269 #define nvme_error_detected NULL
1270 #define nvme_dump_registers NULL
1271 #define nvme_link_reset NULL
1272 #define nvme_slot_reset NULL
1273 #define nvme_error_resume NULL
1274 #define nvme_suspend NULL
1275 #define nvme_resume NULL
1277 static struct pci_error_handlers nvme_err_handler = {
1278 .error_detected = nvme_error_detected,
1279 .mmio_enabled = nvme_dump_registers,
1280 .link_reset = nvme_link_reset,
1281 .slot_reset = nvme_slot_reset,
1282 .resume = nvme_error_resume,
1285 /* Move to pci_ids.h later */
1286 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1288 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1289 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1292 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1294 static struct pci_driver nvme_driver = {
1296 .id_table = nvme_id_table,
1297 .probe = nvme_probe,
1298 .remove = __devexit_p(nvme_remove),
1299 .suspend = nvme_suspend,
1300 .resume = nvme_resume,
1301 .err_handler = &nvme_err_handler,
1304 static int __init nvme_init(void)
1308 nvme_major = register_blkdev(nvme_major, "nvme");
1309 if (nvme_major <= 0)
1312 result = pci_register_driver(&nvme_driver);
1316 unregister_blkdev(nvme_major, "nvme");
1320 static void __exit nvme_exit(void)
1322 pci_unregister_driver(&nvme_driver);
1323 unregister_blkdev(nvme_major, "nvme");
1326 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1327 MODULE_LICENSE("GPL");
1328 MODULE_VERSION("0.2");
1329 module_init(nvme_init);
1330 module_exit(nvme_exit);