2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/version.h>
44 #define NVME_Q_DEPTH 1024
45 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
46 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
47 #define NVME_MINORS 64
48 #define IO_TIMEOUT (5 * HZ)
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major;
52 module_param(nvme_major, int, 0);
54 static int use_threaded_interrupts;
55 module_param(use_threaded_interrupts, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock);
58 static LIST_HEAD(dev_list);
59 static struct task_struct *nvme_thread;
62 * Represents an NVM Express device. Each nvme_dev is a PCI function.
65 struct list_head node;
66 struct nvme_queue **queues;
68 struct pci_dev *pci_dev;
69 struct dma_pool *prp_page_pool;
70 struct dma_pool *prp_small_pool;
75 struct msix_entry *entry;
76 struct nvme_bar __iomem *bar;
77 struct list_head namespaces;
84 * An NVM Express namespace is equivalent to a SCSI LUN
87 struct list_head list;
90 struct request_queue *queue;
98 * An NVM Express queue. Each device has at least two (one for admin
99 * commands and one for I/O commands).
102 struct device *q_dmadev;
103 struct nvme_dev *dev;
105 struct nvme_command *sq_cmds;
106 volatile struct nvme_completion *cqes;
107 dma_addr_t sq_dma_addr;
108 dma_addr_t cq_dma_addr;
109 wait_queue_head_t sq_full;
110 wait_queue_t sq_cong_wait;
111 struct bio_list sq_cong;
119 unsigned long cmdid_data[];
123 * Check we didin't inadvertently grow the command struct
125 static inline void _nvme_check_size(void)
127 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
138 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
139 struct nvme_completion *);
141 struct nvme_cmd_info {
142 nvme_completion_fn fn;
144 unsigned long timeout;
147 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
149 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
153 * alloc_cmdid() - Allocate a Command ID
154 * @nvmeq: The queue that will be used for this command
155 * @ctx: A pointer that will be passed to the handler
156 * @handler: The function to call on completion
158 * Allocate a Command ID for a queue. The data passed in will
159 * be passed to the completion handler. This is implemented by using
160 * the bottom two bits of the ctx pointer to store the handler ID.
161 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
162 * We can change this if it becomes a problem.
164 * May be called with local interrupts disabled and the q_lock held,
165 * or with interrupts enabled and no locks held.
167 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
168 nvme_completion_fn handler, unsigned timeout)
170 int depth = nvmeq->q_depth - 1;
171 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
175 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
178 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
180 info[cmdid].fn = handler;
181 info[cmdid].ctx = ctx;
182 info[cmdid].timeout = jiffies + timeout;
186 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
187 nvme_completion_fn handler, unsigned timeout)
190 wait_event_killable(nvmeq->sq_full,
191 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
192 return (cmdid < 0) ? -EINTR : cmdid;
195 /* Special values must be less than 0x1000 */
196 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
197 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
198 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
199 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
200 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
202 static void special_completion(struct nvme_dev *dev, void *ctx,
203 struct nvme_completion *cqe)
205 if (ctx == CMD_CTX_CANCELLED)
207 if (ctx == CMD_CTX_FLUSH)
209 if (ctx == CMD_CTX_COMPLETED) {
210 dev_warn(&dev->pci_dev->dev,
211 "completed id %d twice on queue %d\n",
212 cqe->command_id, le16_to_cpup(&cqe->sq_id));
215 if (ctx == CMD_CTX_INVALID) {
216 dev_warn(&dev->pci_dev->dev,
217 "invalid id %d completed on queue %d\n",
218 cqe->command_id, le16_to_cpup(&cqe->sq_id));
222 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
226 * Called with local interrupts disabled and the q_lock held. May not sleep.
228 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
229 nvme_completion_fn *fn)
232 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
234 if (cmdid >= nvmeq->q_depth) {
235 *fn = special_completion;
236 return CMD_CTX_INVALID;
238 *fn = info[cmdid].fn;
239 ctx = info[cmdid].ctx;
240 info[cmdid].fn = special_completion;
241 info[cmdid].ctx = CMD_CTX_COMPLETED;
242 clear_bit(cmdid, nvmeq->cmdid_data);
243 wake_up(&nvmeq->sq_full);
247 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
248 nvme_completion_fn *fn)
251 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
253 *fn = info[cmdid].fn;
254 ctx = info[cmdid].ctx;
255 info[cmdid].fn = special_completion;
256 info[cmdid].ctx = CMD_CTX_CANCELLED;
260 static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
262 return dev->queues[get_cpu() + 1];
265 static void put_nvmeq(struct nvme_queue *nvmeq)
271 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
272 * @nvmeq: The queue to use
273 * @cmd: The command to send
275 * Safe to use from interrupt context
277 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
281 spin_lock_irqsave(&nvmeq->q_lock, flags);
282 tail = nvmeq->sq_tail;
283 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
284 if (++tail == nvmeq->q_depth)
286 writel(tail, nvmeq->q_db);
287 nvmeq->sq_tail = tail;
288 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
294 int npages; /* 0 means small pool in use */
295 dma_addr_t first_dma;
299 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
301 const int last_prp = PAGE_SIZE / 8 - 1;
308 prp_dma = prps->first_dma;
310 if (prps->npages == 0)
311 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
312 for (i = 0; i < prps->npages; i++) {
313 __le64 *prp_list = prps->list[i];
314 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
315 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
316 prp_dma = next_prp_dma;
324 struct nvme_prps *prps;
325 struct scatterlist sg[0];
328 /* XXX: use a mempool */
329 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
331 return kzalloc(sizeof(struct nvme_bio) +
332 sizeof(struct scatterlist) * nseg, gfp);
335 static void free_nbio(struct nvme_dev *dev, struct nvme_bio *nbio)
337 nvme_free_prps(dev, nbio->prps);
341 static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
343 struct nvme_queue *nvmeq = get_nvmeq(dev);
344 if (bio_list_empty(&nvmeq->sq_cong))
345 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
346 bio_list_add(&nvmeq->sq_cong, bio);
348 wake_up_process(nvme_thread);
351 static void bio_completion(struct nvme_dev *dev, void *ctx,
352 struct nvme_completion *cqe)
354 struct nvme_bio *nbio = ctx;
355 struct bio *bio = nbio->bio;
356 u16 status = le16_to_cpup(&cqe->status) >> 1;
358 dma_unmap_sg(&dev->pci_dev->dev, nbio->sg, nbio->nents,
359 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
360 free_nbio(dev, nbio);
362 bio_endio(bio, -EIO);
363 } else if (bio->bi_vcnt > bio->bi_idx) {
364 requeue_bio(dev, bio);
370 /* length is in bytes. gfp flags indicates whether we may sleep. */
371 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
372 struct nvme_common_command *cmd,
373 struct scatterlist *sg, int *len,
376 struct dma_pool *pool;
378 int dma_len = sg_dma_len(sg);
379 u64 dma_addr = sg_dma_address(sg);
380 int offset = offset_in_page(dma_addr);
383 int nprps, npages, i;
384 struct nvme_prps *prps = NULL;
386 cmd->prp1 = cpu_to_le64(dma_addr);
387 length -= (PAGE_SIZE - offset);
391 dma_len -= (PAGE_SIZE - offset);
393 dma_addr += (PAGE_SIZE - offset);
396 dma_addr = sg_dma_address(sg);
397 dma_len = sg_dma_len(sg);
400 if (length <= PAGE_SIZE) {
401 cmd->prp2 = cpu_to_le64(dma_addr);
405 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
406 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
407 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp);
409 cmd->prp2 = cpu_to_le64(dma_addr);
410 *len = (*len - length) + PAGE_SIZE;
414 if (nprps <= (256 / 8)) {
415 pool = dev->prp_small_pool;
418 pool = dev->prp_page_pool;
422 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
424 cmd->prp2 = cpu_to_le64(dma_addr);
425 *len = (*len - length) + PAGE_SIZE;
429 prps->list[0] = prp_list;
430 prps->first_dma = prp_dma;
431 cmd->prp2 = cpu_to_le64(prp_dma);
434 if (i == PAGE_SIZE / 8) {
435 __le64 *old_prp_list = prp_list;
436 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
438 *len = (*len - length);
441 prps->list[prps->npages++] = prp_list;
442 prp_list[0] = old_prp_list[i - 1];
443 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
446 prp_list[i++] = cpu_to_le64(dma_addr);
447 dma_len -= PAGE_SIZE;
448 dma_addr += PAGE_SIZE;
456 dma_addr = sg_dma_address(sg);
457 dma_len = sg_dma_len(sg);
463 /* NVMe scatterlists require no holes in the virtual address */
464 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
465 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
467 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
468 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
470 struct bio_vec *bvec, *bvprv = NULL;
471 struct scatterlist *sg = NULL;
472 int i, old_idx, length = 0, nsegs = 0;
474 sg_init_table(nbio->sg, psegs);
475 old_idx = bio->bi_idx;
476 bio_for_each_segment(bvec, bio, i) {
477 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
478 sg->length += bvec->bv_len;
480 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
482 sg = sg ? sg + 1 : nbio->sg;
483 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
487 length += bvec->bv_len;
493 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
494 bio->bi_idx = old_idx;
500 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
503 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
505 memset(cmnd, 0, sizeof(*cmnd));
506 cmnd->common.opcode = nvme_cmd_flush;
507 cmnd->common.command_id = cmdid;
508 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
510 if (++nvmeq->sq_tail == nvmeq->q_depth)
512 writel(nvmeq->sq_tail, nvmeq->q_db);
517 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
519 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
520 special_completion, IO_TIMEOUT);
521 if (unlikely(cmdid < 0))
524 return nvme_submit_flush(nvmeq, ns, cmdid);
528 * Called with local interrupts disabled and the q_lock held. May not sleep.
530 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
533 struct nvme_command *cmnd;
534 struct nvme_bio *nbio;
535 enum dma_data_direction dma_dir;
536 int cmdid, length, result = -ENOMEM;
539 int psegs = bio_phys_segments(ns->queue, bio);
541 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
542 result = nvme_submit_flush_data(nvmeq, ns);
547 nbio = alloc_nbio(psegs, GFP_ATOMIC);
553 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion, IO_TIMEOUT);
554 if (unlikely(cmdid < 0))
557 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
558 return nvme_submit_flush(nvmeq, ns, cmdid);
561 if (bio->bi_rw & REQ_FUA)
562 control |= NVME_RW_FUA;
563 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
564 control |= NVME_RW_LR;
567 if (bio->bi_rw & REQ_RAHEAD)
568 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
570 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
572 memset(cmnd, 0, sizeof(*cmnd));
573 if (bio_data_dir(bio)) {
574 cmnd->rw.opcode = nvme_cmd_write;
575 dma_dir = DMA_TO_DEVICE;
577 cmnd->rw.opcode = nvme_cmd_read;
578 dma_dir = DMA_FROM_DEVICE;
581 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
586 cmnd->rw.command_id = cmdid;
587 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
588 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
589 &length, GFP_ATOMIC);
590 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
591 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
592 cmnd->rw.control = cpu_to_le16(control);
593 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
595 bio->bi_sector += length >> 9;
597 if (++nvmeq->sq_tail == nvmeq->q_depth)
599 writel(nvmeq->sq_tail, nvmeq->q_db);
604 free_nbio(nvmeq->dev, nbio);
610 * NB: return value of non-zero would mean that we were a stacking driver.
611 * make_request must always succeed.
613 static int nvme_make_request(struct request_queue *q, struct bio *bio)
615 struct nvme_ns *ns = q->queuedata;
616 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
619 spin_lock_irq(&nvmeq->q_lock);
620 if (bio_list_empty(&nvmeq->sq_cong))
621 result = nvme_submit_bio_queue(nvmeq, ns, bio);
622 if (unlikely(result)) {
623 if (bio_list_empty(&nvmeq->sq_cong))
624 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
625 bio_list_add(&nvmeq->sq_cong, bio);
628 spin_unlock_irq(&nvmeq->q_lock);
634 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
638 head = nvmeq->cq_head;
639 phase = nvmeq->cq_phase;
643 nvme_completion_fn fn;
644 struct nvme_completion cqe = nvmeq->cqes[head];
645 if ((le16_to_cpu(cqe.status) & 1) != phase)
647 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
648 if (++head == nvmeq->q_depth) {
653 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
654 fn(nvmeq->dev, ctx, &cqe);
657 /* If the controller ignores the cq head doorbell and continuously
658 * writes to the queue, it is theoretically possible to wrap around
659 * the queue twice and mistakenly return IRQ_NONE. Linux only
660 * requires that 0.1% of your interrupts are handled, so this isn't
663 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
666 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
667 nvmeq->cq_head = head;
668 nvmeq->cq_phase = phase;
673 static irqreturn_t nvme_irq(int irq, void *data)
676 struct nvme_queue *nvmeq = data;
677 spin_lock(&nvmeq->q_lock);
678 result = nvme_process_cq(nvmeq);
679 spin_unlock(&nvmeq->q_lock);
683 static irqreturn_t nvme_irq_check(int irq, void *data)
685 struct nvme_queue *nvmeq = data;
686 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
687 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
689 return IRQ_WAKE_THREAD;
692 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
694 spin_lock_irq(&nvmeq->q_lock);
695 cancel_cmdid(nvmeq, cmdid, NULL);
696 spin_unlock_irq(&nvmeq->q_lock);
699 struct sync_cmd_info {
700 struct task_struct *task;
705 static void sync_completion(struct nvme_dev *dev, void *ctx,
706 struct nvme_completion *cqe)
708 struct sync_cmd_info *cmdinfo = ctx;
709 cmdinfo->result = le32_to_cpup(&cqe->result);
710 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
711 wake_up_process(cmdinfo->task);
715 * Returns 0 on success. If the result is negative, it's a Linux error code;
716 * if the result is positive, it's an NVM Express status code
718 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
719 struct nvme_command *cmd, u32 *result, unsigned timeout)
722 struct sync_cmd_info cmdinfo;
724 cmdinfo.task = current;
725 cmdinfo.status = -EINTR;
727 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
731 cmd->common.command_id = cmdid;
733 set_current_state(TASK_KILLABLE);
734 nvme_submit_cmd(nvmeq, cmd);
737 if (cmdinfo.status == -EINTR) {
738 nvme_abort_command(nvmeq, cmdid);
743 *result = cmdinfo.result;
745 return cmdinfo.status;
748 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
751 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
754 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
757 struct nvme_command c;
759 memset(&c, 0, sizeof(c));
760 c.delete_queue.opcode = opcode;
761 c.delete_queue.qid = cpu_to_le16(id);
763 status = nvme_submit_admin_cmd(dev, &c, NULL);
769 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
770 struct nvme_queue *nvmeq)
773 struct nvme_command c;
774 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
776 memset(&c, 0, sizeof(c));
777 c.create_cq.opcode = nvme_admin_create_cq;
778 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
779 c.create_cq.cqid = cpu_to_le16(qid);
780 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
781 c.create_cq.cq_flags = cpu_to_le16(flags);
782 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
784 status = nvme_submit_admin_cmd(dev, &c, NULL);
790 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
791 struct nvme_queue *nvmeq)
794 struct nvme_command c;
795 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
797 memset(&c, 0, sizeof(c));
798 c.create_sq.opcode = nvme_admin_create_sq;
799 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
800 c.create_sq.sqid = cpu_to_le16(qid);
801 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
802 c.create_sq.sq_flags = cpu_to_le16(flags);
803 c.create_sq.cqid = cpu_to_le16(qid);
805 status = nvme_submit_admin_cmd(dev, &c, NULL);
811 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
813 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
816 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
818 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
821 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
824 struct nvme_command c;
826 memset(&c, 0, sizeof(c));
827 c.identify.opcode = nvme_admin_identify;
828 c.identify.nsid = cpu_to_le32(nsid);
829 c.identify.prp1 = cpu_to_le64(dma_addr);
830 c.identify.cns = cpu_to_le32(cns);
832 return nvme_submit_admin_cmd(dev, &c, NULL);
835 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
836 unsigned dword11, dma_addr_t dma_addr, u32 *result)
838 struct nvme_command c;
840 memset(&c, 0, sizeof(c));
841 c.features.opcode = nvme_admin_get_features;
842 c.features.prp1 = cpu_to_le64(dma_addr);
843 c.features.fid = cpu_to_le32(fid);
844 c.features.dword11 = cpu_to_le32(dword11);
846 return nvme_submit_admin_cmd(dev, &c, result);
849 static void nvme_free_queue(struct nvme_dev *dev, int qid)
851 struct nvme_queue *nvmeq = dev->queues[qid];
852 int vector = dev->entry[nvmeq->cq_vector].vector;
854 irq_set_affinity_hint(vector, NULL);
855 free_irq(vector, nvmeq);
857 /* Don't tell the adapter to delete the admin queue */
859 adapter_delete_sq(dev, qid);
860 adapter_delete_cq(dev, qid);
863 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
864 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
865 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
866 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
870 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
871 int depth, int vector)
873 struct device *dmadev = &dev->pci_dev->dev;
874 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
875 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
879 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
880 &nvmeq->cq_dma_addr, GFP_KERNEL);
883 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
885 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
886 &nvmeq->sq_dma_addr, GFP_KERNEL);
890 nvmeq->q_dmadev = dmadev;
892 spin_lock_init(&nvmeq->q_lock);
895 init_waitqueue_head(&nvmeq->sq_full);
896 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
897 bio_list_init(&nvmeq->sq_cong);
898 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
899 nvmeq->q_depth = depth;
900 nvmeq->cq_vector = vector;
905 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
912 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
915 if (use_threaded_interrupts)
916 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
917 nvme_irq_check, nvme_irq,
918 IRQF_DISABLED | IRQF_SHARED,
920 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
921 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
924 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
925 int qid, int cq_size, int vector)
928 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
931 return ERR_PTR(-ENOMEM);
933 result = adapter_alloc_cq(dev, qid, nvmeq);
937 result = adapter_alloc_sq(dev, qid, nvmeq);
941 result = queue_request_irq(dev, nvmeq, "nvme");
948 adapter_delete_sq(dev, qid);
950 adapter_delete_cq(dev, qid);
952 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
953 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
954 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
955 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
957 return ERR_PTR(result);
960 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
965 unsigned long timeout;
966 struct nvme_queue *nvmeq;
968 dev->dbs = ((void __iomem *)dev->bar) + 4096;
970 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
974 aqa = nvmeq->q_depth - 1;
977 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
978 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
979 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
980 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
982 writel(0, &dev->bar->cc);
983 writel(aqa, &dev->bar->aqa);
984 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
985 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
986 writel(dev->ctrl_config, &dev->bar->cc);
988 cap = readq(&dev->bar->cap);
989 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
990 dev->db_stride = NVME_CAP_STRIDE(cap);
992 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
994 if (fatal_signal_pending(current))
996 if (time_after(jiffies, timeout)) {
997 dev_err(&dev->pci_dev->dev,
998 "Device not ready; aborting initialisation\n");
1003 result = queue_request_irq(dev, nvmeq, "nvme admin");
1004 dev->queues[0] = nvmeq;
1008 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
1009 unsigned long addr, unsigned length,
1010 struct scatterlist **sgp)
1012 int i, err, count, nents, offset;
1013 struct scatterlist *sg;
1014 struct page **pages;
1021 offset = offset_in_page(addr);
1022 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1023 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1025 err = get_user_pages_fast(addr, count, 1, pages);
1032 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
1033 sg_init_table(sg, count);
1034 for (i = 0; i < count; i++) {
1035 sg_set_page(&sg[i], pages[i],
1036 min_t(int, length, PAGE_SIZE - offset), offset);
1037 length -= (PAGE_SIZE - offset);
1042 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1043 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1052 for (i = 0; i < count; i++)
1058 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1059 unsigned long addr, int length, struct scatterlist *sg)
1063 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1064 dma_unmap_sg(&dev->pci_dev->dev, sg, count, DMA_FROM_DEVICE);
1066 for (i = 0; i < count; i++)
1067 put_page(sg_page(&sg[i]));
1070 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1072 struct nvme_dev *dev = ns->dev;
1073 struct nvme_queue *nvmeq;
1074 struct nvme_user_io io;
1075 struct nvme_command c;
1078 struct scatterlist *sg;
1079 struct nvme_prps *prps;
1081 if (copy_from_user(&io, uio, sizeof(io)))
1083 length = (io.nblocks + 1) << ns->lba_shift;
1085 switch (io.opcode) {
1086 case nvme_cmd_write:
1088 case nvme_cmd_compare:
1089 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1099 memset(&c, 0, sizeof(c));
1100 c.rw.opcode = io.opcode;
1101 c.rw.flags = io.flags;
1102 c.rw.nsid = cpu_to_le32(ns->ns_id);
1103 c.rw.slba = cpu_to_le64(io.slba);
1104 c.rw.length = cpu_to_le16(io.nblocks);
1105 c.rw.control = cpu_to_le16(io.control);
1106 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1107 c.rw.reftag = io.reftag;
1108 c.rw.apptag = io.apptag;
1109 c.rw.appmask = io.appmask;
1111 prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1113 nvmeq = get_nvmeq(dev);
1115 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1116 * disabled. We may be preempted at any point, and be rescheduled
1117 * to a different CPU. That will cause cacheline bouncing, but no
1118 * additional races since q_lock already protects against other CPUs.
1121 if (length != (io.nblocks + 1) << ns->lba_shift)
1124 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1126 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg);
1127 nvme_free_prps(dev, prps);
1131 static int nvme_user_admin_cmd(struct nvme_ns *ns,
1132 struct nvme_admin_cmd __user *ucmd)
1134 struct nvme_dev *dev = ns->dev;
1135 struct nvme_admin_cmd cmd;
1136 struct nvme_command c;
1137 int status, length, nents = 0;
1138 struct scatterlist *sg;
1139 struct nvme_prps *prps = NULL;
1141 if (!capable(CAP_SYS_ADMIN))
1143 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1146 memset(&c, 0, sizeof(c));
1147 c.common.opcode = cmd.opcode;
1148 c.common.flags = cmd.flags;
1149 c.common.nsid = cpu_to_le32(cmd.nsid);
1150 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1151 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1152 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1153 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1154 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1155 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1156 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1157 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1159 length = cmd.data_len;
1161 nents = nvme_map_user_pages(dev, 1, cmd.addr, length, &sg);
1164 prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1167 if (length != cmd.data_len)
1170 status = nvme_submit_admin_cmd(dev, &c, NULL);
1172 nvme_unmap_user_pages(dev, 0, cmd.addr, cmd.data_len, sg);
1173 nvme_free_prps(dev, prps);
1178 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1181 struct nvme_ns *ns = bdev->bd_disk->private_data;
1186 case NVME_IOCTL_ADMIN_CMD:
1187 return nvme_user_admin_cmd(ns, (void __user *)arg);
1188 case NVME_IOCTL_SUBMIT_IO:
1189 return nvme_submit_io(ns, (void __user *)arg);
1195 static const struct block_device_operations nvme_fops = {
1196 .owner = THIS_MODULE,
1197 .ioctl = nvme_ioctl,
1198 .compat_ioctl = nvme_ioctl,
1201 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1203 int depth = nvmeq->q_depth - 1;
1204 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1205 unsigned long now = jiffies;
1208 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1210 nvme_completion_fn fn;
1211 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1213 if (!time_after(now, info[cmdid].timeout))
1215 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1216 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1217 fn(nvmeq->dev, ctx, &cqe);
1221 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1223 while (bio_list_peek(&nvmeq->sq_cong)) {
1224 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1225 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1226 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1227 bio_list_add_head(&nvmeq->sq_cong, bio);
1230 if (bio_list_empty(&nvmeq->sq_cong))
1231 remove_wait_queue(&nvmeq->sq_full,
1232 &nvmeq->sq_cong_wait);
1236 static int nvme_kthread(void *data)
1238 struct nvme_dev *dev;
1240 while (!kthread_should_stop()) {
1241 __set_current_state(TASK_RUNNING);
1242 spin_lock(&dev_list_lock);
1243 list_for_each_entry(dev, &dev_list, node) {
1245 for (i = 0; i < dev->queue_count; i++) {
1246 struct nvme_queue *nvmeq = dev->queues[i];
1249 spin_lock_irq(&nvmeq->q_lock);
1250 if (nvme_process_cq(nvmeq))
1251 printk("process_cq did something\n");
1252 nvme_timeout_ios(nvmeq);
1253 nvme_resubmit_bios(nvmeq);
1254 spin_unlock_irq(&nvmeq->q_lock);
1257 spin_unlock(&dev_list_lock);
1258 set_current_state(TASK_INTERRUPTIBLE);
1259 schedule_timeout(HZ);
1264 static DEFINE_IDA(nvme_index_ida);
1266 static int nvme_get_ns_idx(void)
1271 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1274 spin_lock(&dev_list_lock);
1275 error = ida_get_new(&nvme_index_ida, &index);
1276 spin_unlock(&dev_list_lock);
1277 } while (error == -EAGAIN);
1284 static void nvme_put_ns_idx(int index)
1286 spin_lock(&dev_list_lock);
1287 ida_remove(&nvme_index_ida, index);
1288 spin_unlock(&dev_list_lock);
1291 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1292 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1295 struct gendisk *disk;
1298 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1301 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1304 ns->queue = blk_alloc_queue(GFP_KERNEL);
1307 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1308 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1309 blk_queue_make_request(ns->queue, nvme_make_request);
1311 ns->queue->queuedata = ns;
1313 disk = alloc_disk(NVME_MINORS);
1315 goto out_free_queue;
1318 lbaf = id->flbas & 0xf;
1319 ns->lba_shift = id->lbaf[lbaf].ds;
1321 disk->major = nvme_major;
1322 disk->minors = NVME_MINORS;
1323 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1324 disk->fops = &nvme_fops;
1325 disk->private_data = ns;
1326 disk->queue = ns->queue;
1327 disk->driverfs_dev = &dev->pci_dev->dev;
1328 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1329 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1334 blk_cleanup_queue(ns->queue);
1340 static void nvme_ns_free(struct nvme_ns *ns)
1342 int index = ns->disk->first_minor / NVME_MINORS;
1344 nvme_put_ns_idx(index);
1345 blk_cleanup_queue(ns->queue);
1349 static int set_queue_count(struct nvme_dev *dev, int count)
1353 u32 q_count = (count - 1) | ((count - 1) << 16);
1355 status = nvme_get_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1359 return min(result & 0xffff, result >> 16) + 1;
1362 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1364 int result, cpu, i, nr_io_queues, db_bar_size;
1366 nr_io_queues = num_online_cpus();
1367 result = set_queue_count(dev, nr_io_queues);
1370 if (result < nr_io_queues)
1371 nr_io_queues = result;
1373 /* Deregister the admin queue's interrupt */
1374 free_irq(dev->entry[0].vector, dev->queues[0]);
1376 db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1377 if (db_bar_size > 8192) {
1379 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1381 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1382 dev->queues[0]->q_db = dev->dbs;
1385 for (i = 0; i < nr_io_queues; i++)
1386 dev->entry[i].entry = i;
1388 result = pci_enable_msix(dev->pci_dev, dev->entry,
1392 } else if (result > 0) {
1393 nr_io_queues = result;
1401 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1402 /* XXX: handle failure here */
1404 cpu = cpumask_first(cpu_online_mask);
1405 for (i = 0; i < nr_io_queues; i++) {
1406 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1407 cpu = cpumask_next(cpu, cpu_online_mask);
1410 for (i = 0; i < nr_io_queues; i++) {
1411 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1413 if (IS_ERR(dev->queues[i + 1]))
1414 return PTR_ERR(dev->queues[i + 1]);
1418 for (; i < num_possible_cpus(); i++) {
1419 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1420 dev->queues[i + 1] = dev->queues[target + 1];
1426 static void nvme_free_queues(struct nvme_dev *dev)
1430 for (i = dev->queue_count - 1; i >= 0; i--)
1431 nvme_free_queue(dev, i);
1434 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1437 struct nvme_ns *ns, *next;
1438 struct nvme_id_ctrl *ctrl;
1439 struct nvme_id_ns *id_ns;
1441 dma_addr_t dma_addr;
1443 res = nvme_setup_io_queues(dev);
1447 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1450 res = nvme_identify(dev, 0, 1, dma_addr);
1457 nn = le32_to_cpup(&ctrl->nn);
1458 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1459 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1460 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1463 for (i = 1; i <= nn; i++) {
1464 res = nvme_identify(dev, i, 0, dma_addr);
1468 if (id_ns->ncap == 0)
1471 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1472 dma_addr + 4096, NULL);
1476 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1478 list_add_tail(&ns->list, &dev->namespaces);
1480 list_for_each_entry(ns, &dev->namespaces, list)
1486 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1487 list_del(&ns->list);
1492 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1496 static int nvme_dev_remove(struct nvme_dev *dev)
1498 struct nvme_ns *ns, *next;
1500 spin_lock(&dev_list_lock);
1501 list_del(&dev->node);
1502 spin_unlock(&dev_list_lock);
1504 /* TODO: wait all I/O finished or cancel them */
1506 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1507 list_del(&ns->list);
1508 del_gendisk(ns->disk);
1512 nvme_free_queues(dev);
1517 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1519 struct device *dmadev = &dev->pci_dev->dev;
1520 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1521 PAGE_SIZE, PAGE_SIZE, 0);
1522 if (!dev->prp_page_pool)
1525 /* Optimisation for I/Os between 4k and 128k */
1526 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1528 if (!dev->prp_small_pool) {
1529 dma_pool_destroy(dev->prp_page_pool);
1535 static void nvme_release_prp_pools(struct nvme_dev *dev)
1537 dma_pool_destroy(dev->prp_page_pool);
1538 dma_pool_destroy(dev->prp_small_pool);
1541 /* XXX: Use an ida or something to let remove / add work correctly */
1542 static void nvme_set_instance(struct nvme_dev *dev)
1544 static int instance;
1545 dev->instance = instance++;
1548 static void nvme_release_instance(struct nvme_dev *dev)
1552 static int __devinit nvme_probe(struct pci_dev *pdev,
1553 const struct pci_device_id *id)
1555 int bars, result = -ENOMEM;
1556 struct nvme_dev *dev;
1558 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1561 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1565 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1570 if (pci_enable_device_mem(pdev))
1572 pci_set_master(pdev);
1573 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1574 if (pci_request_selected_regions(pdev, bars, "nvme"))
1577 INIT_LIST_HEAD(&dev->namespaces);
1578 dev->pci_dev = pdev;
1579 pci_set_drvdata(pdev, dev);
1580 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1581 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1582 nvme_set_instance(dev);
1583 dev->entry[0].vector = pdev->irq;
1585 result = nvme_setup_prp_pools(dev);
1589 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1595 result = nvme_configure_admin_queue(dev);
1600 spin_lock(&dev_list_lock);
1601 list_add(&dev->node, &dev_list);
1602 spin_unlock(&dev_list_lock);
1604 result = nvme_dev_add(dev);
1611 spin_lock(&dev_list_lock);
1612 list_del(&dev->node);
1613 spin_unlock(&dev_list_lock);
1615 nvme_free_queues(dev);
1619 pci_disable_msix(pdev);
1620 nvme_release_instance(dev);
1621 nvme_release_prp_pools(dev);
1623 pci_disable_device(pdev);
1624 pci_release_regions(pdev);
1632 static void __devexit nvme_remove(struct pci_dev *pdev)
1634 struct nvme_dev *dev = pci_get_drvdata(pdev);
1635 nvme_dev_remove(dev);
1636 pci_disable_msix(pdev);
1638 nvme_release_instance(dev);
1639 nvme_release_prp_pools(dev);
1640 pci_disable_device(pdev);
1641 pci_release_regions(pdev);
1647 /* These functions are yet to be implemented */
1648 #define nvme_error_detected NULL
1649 #define nvme_dump_registers NULL
1650 #define nvme_link_reset NULL
1651 #define nvme_slot_reset NULL
1652 #define nvme_error_resume NULL
1653 #define nvme_suspend NULL
1654 #define nvme_resume NULL
1656 static struct pci_error_handlers nvme_err_handler = {
1657 .error_detected = nvme_error_detected,
1658 .mmio_enabled = nvme_dump_registers,
1659 .link_reset = nvme_link_reset,
1660 .slot_reset = nvme_slot_reset,
1661 .resume = nvme_error_resume,
1664 /* Move to pci_ids.h later */
1665 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1667 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1668 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1671 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1673 static struct pci_driver nvme_driver = {
1675 .id_table = nvme_id_table,
1676 .probe = nvme_probe,
1677 .remove = __devexit_p(nvme_remove),
1678 .suspend = nvme_suspend,
1679 .resume = nvme_resume,
1680 .err_handler = &nvme_err_handler,
1683 static int __init nvme_init(void)
1685 int result = -EBUSY;
1687 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1688 if (IS_ERR(nvme_thread))
1689 return PTR_ERR(nvme_thread);
1691 nvme_major = register_blkdev(nvme_major, "nvme");
1692 if (nvme_major <= 0)
1695 result = pci_register_driver(&nvme_driver);
1697 goto unregister_blkdev;
1701 unregister_blkdev(nvme_major, "nvme");
1703 kthread_stop(nvme_thread);
1707 static void __exit nvme_exit(void)
1709 pci_unregister_driver(&nvme_driver);
1710 unregister_blkdev(nvme_major, "nvme");
1711 kthread_stop(nvme_thread);
1714 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1715 MODULE_LICENSE("GPL");
1716 MODULE_VERSION("0.7");
1717 module_init(nvme_init);
1718 module_exit(nvme_exit);