2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/version.h>
44 #define NVME_Q_DEPTH 1024
45 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
46 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
47 #define NVME_MINORS 64
48 #define IO_TIMEOUT (5 * HZ)
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major;
52 module_param(nvme_major, int, 0);
54 static int use_threaded_interrupts;
55 module_param(use_threaded_interrupts, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock);
58 static LIST_HEAD(dev_list);
59 static struct task_struct *nvme_thread;
62 * Represents an NVM Express device. Each nvme_dev is a PCI function.
65 struct list_head node;
66 struct nvme_queue **queues;
68 struct pci_dev *pci_dev;
69 struct dma_pool *prp_page_pool;
70 struct dma_pool *prp_small_pool;
74 struct msix_entry *entry;
75 struct nvme_bar __iomem *bar;
76 struct list_head namespaces;
83 * An NVM Express namespace is equivalent to a SCSI LUN
86 struct list_head list;
89 struct request_queue *queue;
97 * An NVM Express queue. Each device has at least two (one for admin
98 * commands and one for I/O commands).
101 struct device *q_dmadev;
102 struct nvme_dev *dev;
104 struct nvme_command *sq_cmds;
105 volatile struct nvme_completion *cqes;
106 dma_addr_t sq_dma_addr;
107 dma_addr_t cq_dma_addr;
108 wait_queue_head_t sq_full;
109 wait_queue_t sq_cong_wait;
110 struct bio_list sq_cong;
118 unsigned long cmdid_data[];
122 * Check we didin't inadvertently grow the command struct
124 static inline void _nvme_check_size(void)
126 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
137 struct nvme_cmd_info {
139 unsigned long timeout;
142 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
144 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
148 * alloc_cmdid() - Allocate a Command ID
149 * @nvmeq: The queue that will be used for this command
150 * @ctx: A pointer that will be passed to the handler
151 * @handler: The ID of the handler to call
153 * Allocate a Command ID for a queue. The data passed in will
154 * be passed to the completion handler. This is implemented by using
155 * the bottom two bits of the ctx pointer to store the handler ID.
156 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
157 * We can change this if it becomes a problem.
159 * May be called with local interrupts disabled and the q_lock held,
160 * or with interrupts enabled and no locks held.
162 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
165 int depth = nvmeq->q_depth - 1;
166 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
169 BUG_ON((unsigned long)ctx & 3);
172 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
175 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
177 info[cmdid].ctx = (unsigned long)ctx | handler;
178 info[cmdid].timeout = jiffies + timeout;
182 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
183 int handler, unsigned timeout)
186 wait_event_killable(nvmeq->sq_full,
187 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
188 return (cmdid < 0) ? -EINTR : cmdid;
192 * If you need more than four handlers, you'll need to change how
193 * alloc_cmdid and nvme_process_cq work. Consider using a special
194 * CMD_CTX value instead, if that works for your situation.
197 sync_completion_id = 0,
201 /* Special values must be a multiple of 4, and less than 0x1000 */
202 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
203 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
204 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
205 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
206 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
209 * Called with local interrupts disabled and the q_lock held. May not sleep.
211 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
214 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
216 if (cmdid >= nvmeq->q_depth)
217 return CMD_CTX_INVALID;
218 data = info[cmdid].ctx;
219 info[cmdid].ctx = CMD_CTX_COMPLETED;
220 clear_bit(cmdid, nvmeq->cmdid_data);
221 wake_up(&nvmeq->sq_full);
225 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
228 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
229 data = info[cmdid].ctx;
230 info[cmdid].ctx = CMD_CTX_CANCELLED;
234 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
236 return ns->dev->queues[get_cpu() + 1];
239 static void put_nvmeq(struct nvme_queue *nvmeq)
245 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
246 * @nvmeq: The queue to use
247 * @cmd: The command to send
249 * Safe to use from interrupt context
251 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
255 spin_lock_irqsave(&nvmeq->q_lock, flags);
256 tail = nvmeq->sq_tail;
257 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
258 if (++tail == nvmeq->q_depth)
260 writel(tail, nvmeq->q_db);
261 nvmeq->sq_tail = tail;
262 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
269 dma_addr_t first_dma;
273 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
275 const int last_prp = PAGE_SIZE / 8 - 1;
282 prp_dma = prps->first_dma;
284 if (prps->npages == 0)
285 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
286 for (i = 0; i < prps->npages; i++) {
287 __le64 *prp_list = prps->list[i];
288 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
289 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
290 prp_dma = next_prp_dma;
298 struct nvme_prps *prps;
299 struct scatterlist sg[0];
302 /* XXX: use a mempool */
303 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
305 return kzalloc(sizeof(struct nvme_bio) +
306 sizeof(struct scatterlist) * nseg, gfp);
309 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
311 nvme_free_prps(nvmeq->dev, nbio->prps);
315 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
316 struct nvme_completion *cqe)
318 struct nvme_bio *nbio = ctx;
319 struct bio *bio = nbio->bio;
320 u16 status = le16_to_cpup(&cqe->status) >> 1;
322 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
323 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
324 free_nbio(nvmeq, nbio);
326 bio_endio(bio, -EIO);
327 } else if (bio->bi_vcnt > bio->bi_idx) {
328 if (bio_list_empty(&nvmeq->sq_cong))
329 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
330 bio_list_add(&nvmeq->sq_cong, bio);
331 wake_up_process(nvme_thread);
337 /* length is in bytes. gfp flags indicates whether we may sleep. */
338 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
339 struct nvme_common_command *cmd,
340 struct scatterlist *sg, int *len,
343 struct dma_pool *pool;
345 int dma_len = sg_dma_len(sg);
346 u64 dma_addr = sg_dma_address(sg);
347 int offset = offset_in_page(dma_addr);
350 int nprps, npages, i, prp_page;
351 struct nvme_prps *prps = NULL;
353 cmd->prp1 = cpu_to_le64(dma_addr);
354 length -= (PAGE_SIZE - offset);
358 dma_len -= (PAGE_SIZE - offset);
360 dma_addr += (PAGE_SIZE - offset);
363 dma_addr = sg_dma_address(sg);
364 dma_len = sg_dma_len(sg);
367 if (length <= PAGE_SIZE) {
368 cmd->prp2 = cpu_to_le64(dma_addr);
372 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
373 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
374 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp);
376 cmd->prp2 = cpu_to_le64(dma_addr);
377 *len = (*len - length) + PAGE_SIZE;
381 if (nprps <= (256 / 8)) {
382 pool = dev->prp_small_pool;
385 pool = dev->prp_page_pool;
386 prps->npages = npages;
389 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
391 cmd->prp2 = cpu_to_le64(dma_addr);
392 *len = (*len - length) + PAGE_SIZE;
396 prps->list[prp_page++] = prp_list;
397 prps->first_dma = prp_dma;
398 cmd->prp2 = cpu_to_le64(prp_dma);
401 if (i == PAGE_SIZE / 8) {
402 __le64 *old_prp_list = prp_list;
403 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
405 *len = (*len - length);
408 prps->list[prp_page++] = prp_list;
409 prp_list[0] = old_prp_list[i - 1];
410 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
413 prp_list[i++] = cpu_to_le64(dma_addr);
414 dma_len -= PAGE_SIZE;
415 dma_addr += PAGE_SIZE;
423 dma_addr = sg_dma_address(sg);
424 dma_len = sg_dma_len(sg);
430 /* NVMe scatterlists require no holes in the virtual address */
431 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
432 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
434 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
435 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
437 struct bio_vec *bvec, *bvprv = NULL;
438 struct scatterlist *sg = NULL;
439 int i, old_idx, length = 0, nsegs = 0;
441 sg_init_table(nbio->sg, psegs);
442 old_idx = bio->bi_idx;
443 bio_for_each_segment(bvec, bio, i) {
444 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
445 sg->length += bvec->bv_len;
447 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
449 sg = sg ? sg + 1 : nbio->sg;
450 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
454 length += bvec->bv_len;
460 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
461 bio->bi_idx = old_idx;
467 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
470 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
472 memset(cmnd, 0, sizeof(*cmnd));
473 cmnd->common.opcode = nvme_cmd_flush;
474 cmnd->common.command_id = cmdid;
475 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
477 if (++nvmeq->sq_tail == nvmeq->q_depth)
479 writel(nvmeq->sq_tail, nvmeq->q_db);
484 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
486 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
487 sync_completion_id, IO_TIMEOUT);
488 if (unlikely(cmdid < 0))
491 return nvme_submit_flush(nvmeq, ns, cmdid);
495 * Called with local interrupts disabled and the q_lock held. May not sleep.
497 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
500 struct nvme_command *cmnd;
501 struct nvme_bio *nbio;
502 enum dma_data_direction dma_dir;
503 int cmdid, length, result = -ENOMEM;
506 int psegs = bio_phys_segments(ns->queue, bio);
508 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
509 result = nvme_submit_flush_data(nvmeq, ns);
514 nbio = alloc_nbio(psegs, GFP_ATOMIC);
520 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
521 if (unlikely(cmdid < 0))
524 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
525 return nvme_submit_flush(nvmeq, ns, cmdid);
528 if (bio->bi_rw & REQ_FUA)
529 control |= NVME_RW_FUA;
530 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
531 control |= NVME_RW_LR;
534 if (bio->bi_rw & REQ_RAHEAD)
535 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
537 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
539 memset(cmnd, 0, sizeof(*cmnd));
540 if (bio_data_dir(bio)) {
541 cmnd->rw.opcode = nvme_cmd_write;
542 dma_dir = DMA_TO_DEVICE;
544 cmnd->rw.opcode = nvme_cmd_read;
545 dma_dir = DMA_FROM_DEVICE;
548 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
553 cmnd->rw.command_id = cmdid;
554 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
555 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
556 &length, GFP_ATOMIC);
557 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
558 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
559 cmnd->rw.control = cpu_to_le16(control);
560 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
562 bio->bi_sector += length >> 9;
564 if (++nvmeq->sq_tail == nvmeq->q_depth)
566 writel(nvmeq->sq_tail, nvmeq->q_db);
571 free_nbio(nvmeq, nbio);
577 * NB: return value of non-zero would mean that we were a stacking driver.
578 * make_request must always succeed.
580 static int nvme_make_request(struct request_queue *q, struct bio *bio)
582 struct nvme_ns *ns = q->queuedata;
583 struct nvme_queue *nvmeq = get_nvmeq(ns);
586 spin_lock_irq(&nvmeq->q_lock);
587 if (bio_list_empty(&nvmeq->sq_cong))
588 result = nvme_submit_bio_queue(nvmeq, ns, bio);
589 if (unlikely(result)) {
590 if (bio_list_empty(&nvmeq->sq_cong))
591 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
592 bio_list_add(&nvmeq->sq_cong, bio);
595 spin_unlock_irq(&nvmeq->q_lock);
601 struct sync_cmd_info {
602 struct task_struct *task;
607 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
608 struct nvme_completion *cqe)
610 struct sync_cmd_info *cmdinfo = ctx;
611 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
613 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
615 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
616 dev_warn(nvmeq->q_dmadev,
617 "completed id %d twice on queue %d\n",
618 cqe->command_id, le16_to_cpup(&cqe->sq_id));
621 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
622 dev_warn(nvmeq->q_dmadev,
623 "invalid id %d completed on queue %d\n",
624 cqe->command_id, le16_to_cpup(&cqe->sq_id));
627 cmdinfo->result = le32_to_cpup(&cqe->result);
628 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
629 wake_up_process(cmdinfo->task);
632 typedef void (*completion_fn)(struct nvme_queue *, void *,
633 struct nvme_completion *);
635 static const completion_fn nvme_completions[4] = {
636 [sync_completion_id] = sync_completion,
637 [bio_completion_id] = bio_completion,
640 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
644 head = nvmeq->cq_head;
645 phase = nvmeq->cq_phase;
650 unsigned char handler;
651 struct nvme_completion cqe = nvmeq->cqes[head];
652 if ((le16_to_cpu(cqe.status) & 1) != phase)
654 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
655 if (++head == nvmeq->q_depth) {
660 data = free_cmdid(nvmeq, cqe.command_id);
662 ptr = (void *)(data & ~3UL);
663 nvme_completions[handler](nvmeq, ptr, &cqe);
666 /* If the controller ignores the cq head doorbell and continuously
667 * writes to the queue, it is theoretically possible to wrap around
668 * the queue twice and mistakenly return IRQ_NONE. Linux only
669 * requires that 0.1% of your interrupts are handled, so this isn't
672 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
675 writel(head, nvmeq->q_db + 1);
676 nvmeq->cq_head = head;
677 nvmeq->cq_phase = phase;
682 static irqreturn_t nvme_irq(int irq, void *data)
685 struct nvme_queue *nvmeq = data;
686 spin_lock(&nvmeq->q_lock);
687 result = nvme_process_cq(nvmeq);
688 spin_unlock(&nvmeq->q_lock);
692 static irqreturn_t nvme_irq_check(int irq, void *data)
694 struct nvme_queue *nvmeq = data;
695 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
696 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
698 return IRQ_WAKE_THREAD;
701 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
703 spin_lock_irq(&nvmeq->q_lock);
704 cancel_cmdid(nvmeq, cmdid);
705 spin_unlock_irq(&nvmeq->q_lock);
709 * Returns 0 on success. If the result is negative, it's a Linux error code;
710 * if the result is positive, it's an NVM Express status code
712 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
713 struct nvme_command *cmd, u32 *result, unsigned timeout)
716 struct sync_cmd_info cmdinfo;
718 cmdinfo.task = current;
719 cmdinfo.status = -EINTR;
721 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
725 cmd->common.command_id = cmdid;
727 set_current_state(TASK_KILLABLE);
728 nvme_submit_cmd(nvmeq, cmd);
731 if (cmdinfo.status == -EINTR) {
732 nvme_abort_command(nvmeq, cmdid);
737 *result = cmdinfo.result;
739 return cmdinfo.status;
742 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
745 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
748 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
751 struct nvme_command c;
753 memset(&c, 0, sizeof(c));
754 c.delete_queue.opcode = opcode;
755 c.delete_queue.qid = cpu_to_le16(id);
757 status = nvme_submit_admin_cmd(dev, &c, NULL);
763 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
764 struct nvme_queue *nvmeq)
767 struct nvme_command c;
768 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
770 memset(&c, 0, sizeof(c));
771 c.create_cq.opcode = nvme_admin_create_cq;
772 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
773 c.create_cq.cqid = cpu_to_le16(qid);
774 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
775 c.create_cq.cq_flags = cpu_to_le16(flags);
776 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
778 status = nvme_submit_admin_cmd(dev, &c, NULL);
784 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
785 struct nvme_queue *nvmeq)
788 struct nvme_command c;
789 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
791 memset(&c, 0, sizeof(c));
792 c.create_sq.opcode = nvme_admin_create_sq;
793 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
794 c.create_sq.sqid = cpu_to_le16(qid);
795 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
796 c.create_sq.sq_flags = cpu_to_le16(flags);
797 c.create_sq.cqid = cpu_to_le16(qid);
799 status = nvme_submit_admin_cmd(dev, &c, NULL);
805 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
807 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
810 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
812 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
815 static void nvme_free_queue(struct nvme_dev *dev, int qid)
817 struct nvme_queue *nvmeq = dev->queues[qid];
818 int vector = dev->entry[nvmeq->cq_vector].vector;
820 irq_set_affinity_hint(vector, NULL);
821 free_irq(vector, nvmeq);
823 /* Don't tell the adapter to delete the admin queue */
825 adapter_delete_sq(dev, qid);
826 adapter_delete_cq(dev, qid);
829 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
830 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
831 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
832 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
836 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
837 int depth, int vector)
839 struct device *dmadev = &dev->pci_dev->dev;
840 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
841 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
845 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
846 &nvmeq->cq_dma_addr, GFP_KERNEL);
849 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
851 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
852 &nvmeq->sq_dma_addr, GFP_KERNEL);
856 nvmeq->q_dmadev = dmadev;
858 spin_lock_init(&nvmeq->q_lock);
861 init_waitqueue_head(&nvmeq->sq_full);
862 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
863 bio_list_init(&nvmeq->sq_cong);
864 nvmeq->q_db = &dev->dbs[qid * 2];
865 nvmeq->q_depth = depth;
866 nvmeq->cq_vector = vector;
871 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
878 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
881 if (use_threaded_interrupts)
882 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
883 nvme_irq_check, nvme_irq,
884 IRQF_DISABLED | IRQF_SHARED,
886 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
887 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
890 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
891 int qid, int cq_size, int vector)
894 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
897 return ERR_PTR(-ENOMEM);
899 result = adapter_alloc_cq(dev, qid, nvmeq);
903 result = adapter_alloc_sq(dev, qid, nvmeq);
907 result = queue_request_irq(dev, nvmeq, "nvme");
914 adapter_delete_sq(dev, qid);
916 adapter_delete_cq(dev, qid);
918 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
919 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
920 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
921 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
923 return ERR_PTR(result);
926 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
931 unsigned long timeout;
932 struct nvme_queue *nvmeq;
934 dev->dbs = ((void __iomem *)dev->bar) + 4096;
936 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
940 aqa = nvmeq->q_depth - 1;
943 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
944 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
945 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
946 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
948 writel(0, &dev->bar->cc);
949 writel(aqa, &dev->bar->aqa);
950 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
951 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
952 writel(dev->ctrl_config, &dev->bar->cc);
954 cap = readq(&dev->bar->cap);
955 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
957 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
959 if (fatal_signal_pending(current))
961 if (time_after(jiffies, timeout)) {
962 dev_err(&dev->pci_dev->dev,
963 "Device not ready; aborting initialisation\n");
968 result = queue_request_irq(dev, nvmeq, "nvme admin");
969 dev->queues[0] = nvmeq;
973 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
974 unsigned long addr, unsigned length,
975 struct scatterlist **sgp)
977 int i, err, count, nents, offset;
978 struct scatterlist *sg;
986 offset = offset_in_page(addr);
987 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
988 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
990 err = get_user_pages_fast(addr, count, 1, pages);
997 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
998 sg_init_table(sg, count);
999 for (i = 0; i < count; i++) {
1000 sg_set_page(&sg[i], pages[i],
1001 min_t(int, length, PAGE_SIZE - offset), offset);
1002 length -= (PAGE_SIZE - offset);
1007 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1008 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1017 for (i = 0; i < count; i++)
1023 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1024 unsigned long addr, int length, struct scatterlist *sg)
1028 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1029 dma_unmap_sg(&dev->pci_dev->dev, sg, count, DMA_FROM_DEVICE);
1031 for (i = 0; i < count; i++)
1032 put_page(sg_page(&sg[i]));
1035 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1037 struct nvme_dev *dev = ns->dev;
1038 struct nvme_queue *nvmeq;
1039 struct nvme_user_io io;
1040 struct nvme_command c;
1043 struct scatterlist *sg;
1044 struct nvme_prps *prps;
1046 if (copy_from_user(&io, uio, sizeof(io)))
1048 length = (io.nblocks + 1) << ns->lba_shift;
1050 switch (io.opcode) {
1051 case nvme_cmd_write:
1053 case nvme_cmd_compare:
1054 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1064 memset(&c, 0, sizeof(c));
1065 c.rw.opcode = io.opcode;
1066 c.rw.flags = io.flags;
1067 c.rw.nsid = cpu_to_le32(ns->ns_id);
1068 c.rw.slba = cpu_to_le64(io.slba);
1069 c.rw.length = cpu_to_le16(io.nblocks);
1070 c.rw.control = cpu_to_le16(io.control);
1071 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1072 c.rw.reftag = io.reftag;
1073 c.rw.apptag = io.apptag;
1074 c.rw.appmask = io.appmask;
1076 prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1078 nvmeq = get_nvmeq(ns);
1080 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1081 * disabled. We may be preempted at any point, and be rescheduled
1082 * to a different CPU. That will cause cacheline bouncing, but no
1083 * additional races since q_lock already protects against other CPUs.
1086 if (length != (io.nblocks + 1) << ns->lba_shift)
1089 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1091 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg);
1092 nvme_free_prps(dev, prps);
1096 static int nvme_user_admin_cmd(struct nvme_ns *ns,
1097 struct nvme_admin_cmd __user *ucmd)
1099 struct nvme_dev *dev = ns->dev;
1100 struct nvme_admin_cmd cmd;
1101 struct nvme_command c;
1102 int status, length, nents = 0;
1103 struct scatterlist *sg;
1104 struct nvme_prps *prps = NULL;
1106 if (!capable(CAP_SYS_ADMIN))
1108 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1111 memset(&c, 0, sizeof(c));
1112 c.common.opcode = cmd.opcode;
1113 c.common.flags = cmd.flags;
1114 c.common.nsid = cpu_to_le32(cmd.nsid);
1115 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1116 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1117 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1118 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1119 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1120 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1121 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1122 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1124 length = cmd.data_len;
1126 nents = nvme_map_user_pages(dev, 1, cmd.addr, length, &sg);
1129 prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1132 if (length != cmd.data_len)
1135 status = nvme_submit_admin_cmd(dev, &c, NULL);
1137 nvme_unmap_user_pages(dev, 0, cmd.addr, cmd.data_len, sg);
1138 nvme_free_prps(dev, prps);
1143 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1146 struct nvme_ns *ns = bdev->bd_disk->private_data;
1151 case NVME_IOCTL_ADMIN_CMD:
1152 return nvme_user_admin_cmd(ns, (void __user *)arg);
1153 case NVME_IOCTL_SUBMIT_IO:
1154 return nvme_submit_io(ns, (void __user *)arg);
1160 static const struct block_device_operations nvme_fops = {
1161 .owner = THIS_MODULE,
1162 .ioctl = nvme_ioctl,
1163 .compat_ioctl = nvme_ioctl,
1166 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1168 int depth = nvmeq->q_depth - 1;
1169 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1170 unsigned long now = jiffies;
1173 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1176 unsigned char handler;
1177 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1179 if (!time_after(now, info[cmdid].timeout))
1181 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1182 data = cancel_cmdid(nvmeq, cmdid);
1184 ptr = (void *)(data & ~3UL);
1185 nvme_completions[handler](nvmeq, ptr, &cqe);
1189 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1191 while (bio_list_peek(&nvmeq->sq_cong)) {
1192 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1193 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1194 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1195 bio_list_add_head(&nvmeq->sq_cong, bio);
1198 if (bio_list_empty(&nvmeq->sq_cong))
1199 remove_wait_queue(&nvmeq->sq_full,
1200 &nvmeq->sq_cong_wait);
1204 static int nvme_kthread(void *data)
1206 struct nvme_dev *dev;
1208 while (!kthread_should_stop()) {
1209 __set_current_state(TASK_RUNNING);
1210 spin_lock(&dev_list_lock);
1211 list_for_each_entry(dev, &dev_list, node) {
1213 for (i = 0; i < dev->queue_count; i++) {
1214 struct nvme_queue *nvmeq = dev->queues[i];
1217 spin_lock_irq(&nvmeq->q_lock);
1218 if (nvme_process_cq(nvmeq))
1219 printk("process_cq did something\n");
1220 nvme_timeout_ios(nvmeq);
1221 nvme_resubmit_bios(nvmeq);
1222 spin_unlock_irq(&nvmeq->q_lock);
1225 spin_unlock(&dev_list_lock);
1226 set_current_state(TASK_INTERRUPTIBLE);
1227 schedule_timeout(HZ);
1232 static DEFINE_IDA(nvme_index_ida);
1234 static int nvme_get_ns_idx(void)
1239 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1242 spin_lock(&dev_list_lock);
1243 error = ida_get_new(&nvme_index_ida, &index);
1244 spin_unlock(&dev_list_lock);
1245 } while (error == -EAGAIN);
1252 static void nvme_put_ns_idx(int index)
1254 spin_lock(&dev_list_lock);
1255 ida_remove(&nvme_index_ida, index);
1256 spin_unlock(&dev_list_lock);
1259 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1260 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1263 struct gendisk *disk;
1266 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1269 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1272 ns->queue = blk_alloc_queue(GFP_KERNEL);
1275 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1276 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1277 blk_queue_make_request(ns->queue, nvme_make_request);
1279 ns->queue->queuedata = ns;
1281 disk = alloc_disk(NVME_MINORS);
1283 goto out_free_queue;
1286 lbaf = id->flbas & 0xf;
1287 ns->lba_shift = id->lbaf[lbaf].ds;
1289 disk->major = nvme_major;
1290 disk->minors = NVME_MINORS;
1291 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1292 disk->fops = &nvme_fops;
1293 disk->private_data = ns;
1294 disk->queue = ns->queue;
1295 disk->driverfs_dev = &dev->pci_dev->dev;
1296 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1297 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1302 blk_cleanup_queue(ns->queue);
1308 static void nvme_ns_free(struct nvme_ns *ns)
1310 int index = ns->disk->first_minor / NVME_MINORS;
1312 nvme_put_ns_idx(index);
1313 blk_cleanup_queue(ns->queue);
1317 static int set_queue_count(struct nvme_dev *dev, int count)
1321 struct nvme_command c;
1322 u32 q_count = (count - 1) | ((count - 1) << 16);
1324 memset(&c, 0, sizeof(c));
1325 c.features.opcode = nvme_admin_get_features;
1326 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1327 c.features.dword11 = cpu_to_le32(q_count);
1329 status = nvme_submit_admin_cmd(dev, &c, &result);
1332 return min(result & 0xffff, result >> 16) + 1;
1335 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1337 int result, cpu, i, nr_io_queues;
1339 nr_io_queues = num_online_cpus();
1340 result = set_queue_count(dev, nr_io_queues);
1343 if (result < nr_io_queues)
1344 nr_io_queues = result;
1346 /* Deregister the admin queue's interrupt */
1347 free_irq(dev->entry[0].vector, dev->queues[0]);
1349 for (i = 0; i < nr_io_queues; i++)
1350 dev->entry[i].entry = i;
1352 result = pci_enable_msix(dev->pci_dev, dev->entry,
1356 } else if (result > 0) {
1357 nr_io_queues = result;
1365 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1366 /* XXX: handle failure here */
1368 cpu = cpumask_first(cpu_online_mask);
1369 for (i = 0; i < nr_io_queues; i++) {
1370 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1371 cpu = cpumask_next(cpu, cpu_online_mask);
1374 for (i = 0; i < nr_io_queues; i++) {
1375 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1377 if (IS_ERR(dev->queues[i + 1]))
1378 return PTR_ERR(dev->queues[i + 1]);
1382 for (; i < num_possible_cpus(); i++) {
1383 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1384 dev->queues[i + 1] = dev->queues[target + 1];
1390 static void nvme_free_queues(struct nvme_dev *dev)
1394 for (i = dev->queue_count - 1; i >= 0; i--)
1395 nvme_free_queue(dev, i);
1398 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1401 struct nvme_ns *ns, *next;
1402 struct nvme_id_ctrl *ctrl;
1404 dma_addr_t dma_addr;
1405 struct nvme_command cid, crt;
1407 res = nvme_setup_io_queues(dev);
1411 /* XXX: Switch to a SG list once prp2 works */
1412 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1415 memset(&cid, 0, sizeof(cid));
1416 cid.identify.opcode = nvme_admin_identify;
1417 cid.identify.nsid = 0;
1418 cid.identify.prp1 = cpu_to_le64(dma_addr);
1419 cid.identify.cns = cpu_to_le32(1);
1421 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1428 nn = le32_to_cpup(&ctrl->nn);
1429 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1430 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1431 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1433 cid.identify.cns = 0;
1434 memset(&crt, 0, sizeof(crt));
1435 crt.features.opcode = nvme_admin_get_features;
1436 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1437 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1439 for (i = 0; i <= nn; i++) {
1440 cid.identify.nsid = cpu_to_le32(i);
1441 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1445 if (((struct nvme_id_ns *)id)->ncap == 0)
1448 crt.features.nsid = cpu_to_le32(i);
1449 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1453 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1455 list_add_tail(&ns->list, &dev->namespaces);
1457 list_for_each_entry(ns, &dev->namespaces, list)
1460 dma_free_coherent(&dev->pci_dev->dev, 8192, id, dma_addr);
1464 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1465 list_del(&ns->list);
1469 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1473 static int nvme_dev_remove(struct nvme_dev *dev)
1475 struct nvme_ns *ns, *next;
1477 spin_lock(&dev_list_lock);
1478 list_del(&dev->node);
1479 spin_unlock(&dev_list_lock);
1481 /* TODO: wait all I/O finished or cancel them */
1483 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1484 list_del(&ns->list);
1485 del_gendisk(ns->disk);
1489 nvme_free_queues(dev);
1494 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1496 struct device *dmadev = &dev->pci_dev->dev;
1497 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1498 PAGE_SIZE, PAGE_SIZE, 0);
1499 if (!dev->prp_page_pool)
1502 /* Optimisation for I/Os between 4k and 128k */
1503 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1505 if (!dev->prp_small_pool) {
1506 dma_pool_destroy(dev->prp_page_pool);
1512 static void nvme_release_prp_pools(struct nvme_dev *dev)
1514 dma_pool_destroy(dev->prp_page_pool);
1515 dma_pool_destroy(dev->prp_small_pool);
1518 /* XXX: Use an ida or something to let remove / add work correctly */
1519 static void nvme_set_instance(struct nvme_dev *dev)
1521 static int instance;
1522 dev->instance = instance++;
1525 static void nvme_release_instance(struct nvme_dev *dev)
1529 static int __devinit nvme_probe(struct pci_dev *pdev,
1530 const struct pci_device_id *id)
1532 int bars, result = -ENOMEM;
1533 struct nvme_dev *dev;
1535 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1538 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1542 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1547 if (pci_enable_device_mem(pdev))
1549 pci_set_master(pdev);
1550 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1551 if (pci_request_selected_regions(pdev, bars, "nvme"))
1554 INIT_LIST_HEAD(&dev->namespaces);
1555 dev->pci_dev = pdev;
1556 pci_set_drvdata(pdev, dev);
1557 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1558 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1559 nvme_set_instance(dev);
1560 dev->entry[0].vector = pdev->irq;
1562 result = nvme_setup_prp_pools(dev);
1566 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1572 result = nvme_configure_admin_queue(dev);
1577 spin_lock(&dev_list_lock);
1578 list_add(&dev->node, &dev_list);
1579 spin_unlock(&dev_list_lock);
1581 result = nvme_dev_add(dev);
1588 spin_lock(&dev_list_lock);
1589 list_del(&dev->node);
1590 spin_unlock(&dev_list_lock);
1592 nvme_free_queues(dev);
1596 pci_disable_msix(pdev);
1597 nvme_release_instance(dev);
1598 nvme_release_prp_pools(dev);
1600 pci_disable_device(pdev);
1601 pci_release_regions(pdev);
1609 static void __devexit nvme_remove(struct pci_dev *pdev)
1611 struct nvme_dev *dev = pci_get_drvdata(pdev);
1612 nvme_dev_remove(dev);
1613 pci_disable_msix(pdev);
1615 nvme_release_instance(dev);
1616 nvme_release_prp_pools(dev);
1617 pci_disable_device(pdev);
1618 pci_release_regions(pdev);
1624 /* These functions are yet to be implemented */
1625 #define nvme_error_detected NULL
1626 #define nvme_dump_registers NULL
1627 #define nvme_link_reset NULL
1628 #define nvme_slot_reset NULL
1629 #define nvme_error_resume NULL
1630 #define nvme_suspend NULL
1631 #define nvme_resume NULL
1633 static struct pci_error_handlers nvme_err_handler = {
1634 .error_detected = nvme_error_detected,
1635 .mmio_enabled = nvme_dump_registers,
1636 .link_reset = nvme_link_reset,
1637 .slot_reset = nvme_slot_reset,
1638 .resume = nvme_error_resume,
1641 /* Move to pci_ids.h later */
1642 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1644 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1645 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1648 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1650 static struct pci_driver nvme_driver = {
1652 .id_table = nvme_id_table,
1653 .probe = nvme_probe,
1654 .remove = __devexit_p(nvme_remove),
1655 .suspend = nvme_suspend,
1656 .resume = nvme_resume,
1657 .err_handler = &nvme_err_handler,
1660 static int __init nvme_init(void)
1662 int result = -EBUSY;
1664 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1665 if (IS_ERR(nvme_thread))
1666 return PTR_ERR(nvme_thread);
1668 nvme_major = register_blkdev(nvme_major, "nvme");
1669 if (nvme_major <= 0)
1672 result = pci_register_driver(&nvme_driver);
1674 goto unregister_blkdev;
1678 unregister_blkdev(nvme_major, "nvme");
1680 kthread_stop(nvme_thread);
1684 static void __exit nvme_exit(void)
1686 pci_unregister_driver(&nvme_driver);
1687 unregister_blkdev(nvme_major, "nvme");
1688 kthread_stop(nvme_thread);
1691 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1692 MODULE_LICENSE("GPL");
1693 MODULE_VERSION("0.6");
1694 module_init(nvme_init);
1695 module_exit(nvme_exit);