2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/poison.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/types.h>
39 #include <linux/version.h>
41 #define NVME_Q_DEPTH 1024
42 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
43 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
44 #define NVME_MINORS 64
45 #define IO_TIMEOUT (5 * HZ)
46 #define ADMIN_TIMEOUT (60 * HZ)
48 static int nvme_major;
49 module_param(nvme_major, int, 0);
51 static int use_threaded_interrupts;
52 module_param(use_threaded_interrupts, int, 0);
54 static DEFINE_SPINLOCK(dev_list_lock);
55 static LIST_HEAD(dev_list);
56 static struct task_struct *nvme_thread;
59 * Represents an NVM Express device. Each nvme_dev is a PCI function.
62 struct list_head node;
63 struct nvme_queue **queues;
65 struct pci_dev *pci_dev;
66 struct dma_pool *prp_page_pool;
67 struct dma_pool *prp_small_pool;
71 struct msix_entry *entry;
72 struct nvme_bar __iomem *bar;
73 struct list_head namespaces;
80 * An NVM Express namespace is equivalent to a SCSI LUN
83 struct list_head list;
86 struct request_queue *queue;
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
98 struct device *q_dmadev;
101 struct nvme_command *sq_cmds;
102 volatile struct nvme_completion *cqes;
103 dma_addr_t sq_dma_addr;
104 dma_addr_t cq_dma_addr;
105 wait_queue_head_t sq_full;
106 wait_queue_t sq_cong_wait;
107 struct bio_list sq_cong;
115 unsigned long cmdid_data[];
119 * Check we didin't inadvertently grow the command struct
121 static inline void _nvme_check_size(void)
123 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
124 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
125 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
130 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
131 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
134 struct nvme_cmd_info {
136 unsigned long timeout;
139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
141 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
145 * alloc_cmdid() - Allocate a Command ID
146 * @nvmeq: The queue that will be used for this command
147 * @ctx: A pointer that will be passed to the handler
148 * @handler: The ID of the handler to call
150 * Allocate a Command ID for a queue. The data passed in will
151 * be passed to the completion handler. This is implemented by using
152 * the bottom two bits of the ctx pointer to store the handler ID.
153 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
154 * We can change this if it becomes a problem.
156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
159 int depth = nvmeq->q_depth - 1;
160 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
163 BUG_ON((unsigned long)ctx & 3);
166 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
169 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
171 info[cmdid].ctx = (unsigned long)ctx | handler;
172 info[cmdid].timeout = jiffies + timeout;
176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
177 int handler, unsigned timeout)
180 wait_event_killable(nvmeq->sq_full,
181 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
182 return (cmdid < 0) ? -EINTR : cmdid;
185 /* If you need more than four handlers, you'll need to change how
186 * alloc_cmdid and nvme_process_cq work. Consider using a special
187 * CMD_CTX value instead, if that works for your situation.
190 sync_completion_id = 0,
194 /* Special values must be a multiple of 4, and less than 0x1000 */
195 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
196 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
197 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
198 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
199 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
201 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
204 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
206 if (cmdid >= nvmeq->q_depth)
207 return CMD_CTX_INVALID;
208 data = info[cmdid].ctx;
209 info[cmdid].ctx = CMD_CTX_COMPLETED;
210 clear_bit(cmdid, nvmeq->cmdid_data);
211 wake_up(&nvmeq->sq_full);
215 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
217 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
218 info[cmdid].ctx = CMD_CTX_CANCELLED;
221 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
223 int qid, cpu = get_cpu();
224 if (cpu < ns->dev->queue_count)
227 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
228 return ns->dev->queues[qid];
231 static void put_nvmeq(struct nvme_queue *nvmeq)
237 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
238 * @nvmeq: The queue to use
239 * @cmd: The command to send
241 * Safe to use from interrupt context
243 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
247 /* XXX: Need to check tail isn't going to overrun head */
248 spin_lock_irqsave(&nvmeq->q_lock, flags);
249 tail = nvmeq->sq_tail;
250 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
251 if (++tail == nvmeq->q_depth)
253 writel(tail, nvmeq->q_db);
254 nvmeq->sq_tail = tail;
255 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
262 dma_addr_t first_dma;
266 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
268 const int last_prp = PAGE_SIZE / 8 - 1;
275 prp_dma = prps->first_dma;
277 if (prps->npages == 0)
278 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
279 for (i = 0; i < prps->npages; i++) {
280 __le64 *prp_list = prps->list[i];
281 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
282 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
283 prp_dma = next_prp_dma;
291 struct nvme_prps *prps;
292 struct scatterlist sg[0];
295 /* XXX: use a mempool */
296 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
298 return kzalloc(sizeof(struct nvme_bio) +
299 sizeof(struct scatterlist) * nseg, gfp);
302 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
304 nvme_free_prps(nvmeq->dev, nbio->prps);
308 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
309 struct nvme_completion *cqe)
311 struct nvme_bio *nbio = ctx;
312 struct bio *bio = nbio->bio;
313 u16 status = le16_to_cpup(&cqe->status) >> 1;
315 dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
316 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
317 free_nbio(nvmeq, nbio);
319 bio_endio(bio, -EIO);
320 if (bio->bi_vcnt > bio->bi_idx) {
321 bio_list_add(&nvmeq->sq_cong, bio);
322 wake_up_process(nvme_thread);
328 /* length is in bytes */
329 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
330 struct nvme_common_command *cmd,
331 struct scatterlist *sg, int length)
333 struct dma_pool *pool;
334 int dma_len = sg_dma_len(sg);
335 u64 dma_addr = sg_dma_address(sg);
336 int offset = offset_in_page(dma_addr);
339 int nprps, npages, i, prp_page;
340 struct nvme_prps *prps = NULL;
342 cmd->prp1 = cpu_to_le64(dma_addr);
343 length -= (PAGE_SIZE - offset);
347 dma_len -= (PAGE_SIZE - offset);
349 dma_addr += (PAGE_SIZE - offset);
352 dma_addr = sg_dma_address(sg);
353 dma_len = sg_dma_len(sg);
356 if (length <= PAGE_SIZE) {
357 cmd->prp2 = cpu_to_le64(dma_addr);
361 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
362 npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
363 prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
365 if (nprps <= (256 / 8)) {
366 pool = dev->prp_small_pool;
369 pool = dev->prp_page_pool;
370 prps->npages = npages;
373 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
374 prps->list[prp_page++] = prp_list;
375 prps->first_dma = prp_dma;
376 cmd->prp2 = cpu_to_le64(prp_dma);
379 if (i == PAGE_SIZE / 8 - 1) {
380 __le64 *old_prp_list = prp_list;
381 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
382 prps->list[prp_page++] = prp_list;
383 old_prp_list[i] = cpu_to_le64(prp_dma);
386 prp_list[i++] = cpu_to_le64(dma_addr);
387 dma_len -= PAGE_SIZE;
388 dma_addr += PAGE_SIZE;
396 dma_addr = sg_dma_address(sg);
397 dma_len = sg_dma_len(sg);
403 /* NVMe scatterlists require no holes in the virtual address */
404 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
405 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
407 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
408 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
410 struct bio_vec *bvec, *bvprv = NULL;
411 struct scatterlist *sg = NULL;
412 int i, old_idx, length = 0, nsegs = 0;
414 sg_init_table(nbio->sg, psegs);
415 old_idx = bio->bi_idx;
416 bio_for_each_segment(bvec, bio, i) {
417 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
418 sg->length += bvec->bv_len;
420 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
422 sg = sg ? sg + 1 : nbio->sg;
423 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
427 length += bvec->bv_len;
433 if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
434 bio->bi_idx = old_idx;
440 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
443 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
445 memset(cmnd, 0, sizeof(*cmnd));
446 cmnd->common.opcode = nvme_cmd_flush;
447 cmnd->common.command_id = cmdid;
448 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
450 if (++nvmeq->sq_tail == nvmeq->q_depth)
452 writel(nvmeq->sq_tail, nvmeq->q_db);
457 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
459 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
460 sync_completion_id, IO_TIMEOUT);
461 if (unlikely(cmdid < 0))
464 return nvme_submit_flush(nvmeq, ns, cmdid);
467 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
470 struct nvme_command *cmnd;
471 struct nvme_bio *nbio;
472 enum dma_data_direction dma_dir;
473 int cmdid, length, result = -ENOMEM;
476 int psegs = bio_phys_segments(ns->queue, bio);
478 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
479 result = nvme_submit_flush_data(nvmeq, ns);
484 nbio = alloc_nbio(psegs, GFP_ATOMIC);
490 cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
491 if (unlikely(cmdid < 0))
494 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
495 return nvme_submit_flush(nvmeq, ns, cmdid);
498 if (bio->bi_rw & REQ_FUA)
499 control |= NVME_RW_FUA;
500 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
501 control |= NVME_RW_LR;
504 if (bio->bi_rw & REQ_RAHEAD)
505 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
507 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
509 memset(cmnd, 0, sizeof(*cmnd));
510 if (bio_data_dir(bio)) {
511 cmnd->rw.opcode = nvme_cmd_write;
512 dma_dir = DMA_TO_DEVICE;
514 cmnd->rw.opcode = nvme_cmd_read;
515 dma_dir = DMA_FROM_DEVICE;
518 result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
523 cmnd->rw.command_id = cmdid;
524 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
525 nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
527 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
528 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
529 cmnd->rw.control = cpu_to_le16(control);
530 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
532 bio->bi_sector += length >> 9;
534 if (++nvmeq->sq_tail == nvmeq->q_depth)
536 writel(nvmeq->sq_tail, nvmeq->q_db);
541 free_nbio(nvmeq, nbio);
547 * NB: return value of non-zero would mean that we were a stacking driver.
548 * make_request must always succeed.
550 static int nvme_make_request(struct request_queue *q, struct bio *bio)
552 struct nvme_ns *ns = q->queuedata;
553 struct nvme_queue *nvmeq = get_nvmeq(ns);
556 spin_lock_irq(&nvmeq->q_lock);
557 if (bio_list_empty(&nvmeq->sq_cong))
558 result = nvme_submit_bio_queue(nvmeq, ns, bio);
559 if (unlikely(result)) {
560 if (bio_list_empty(&nvmeq->sq_cong))
561 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
562 bio_list_add(&nvmeq->sq_cong, bio);
565 spin_unlock_irq(&nvmeq->q_lock);
571 struct sync_cmd_info {
572 struct task_struct *task;
577 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
578 struct nvme_completion *cqe)
580 struct sync_cmd_info *cmdinfo = ctx;
581 if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
583 if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
585 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
586 dev_warn(nvmeq->q_dmadev,
587 "completed id %d twice on queue %d\n",
588 cqe->command_id, le16_to_cpup(&cqe->sq_id));
591 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
592 dev_warn(nvmeq->q_dmadev,
593 "invalid id %d completed on queue %d\n",
594 cqe->command_id, le16_to_cpup(&cqe->sq_id));
597 cmdinfo->result = le32_to_cpup(&cqe->result);
598 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
599 wake_up_process(cmdinfo->task);
602 typedef void (*completion_fn)(struct nvme_queue *, void *,
603 struct nvme_completion *);
605 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
609 static const completion_fn completions[4] = {
610 [sync_completion_id] = sync_completion,
611 [bio_completion_id] = bio_completion,
614 head = nvmeq->cq_head;
615 phase = nvmeq->cq_phase;
620 unsigned char handler;
621 struct nvme_completion cqe = nvmeq->cqes[head];
622 if ((le16_to_cpu(cqe.status) & 1) != phase)
624 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
625 if (++head == nvmeq->q_depth) {
630 data = free_cmdid(nvmeq, cqe.command_id);
632 ptr = (void *)(data & ~3UL);
633 completions[handler](nvmeq, ptr, &cqe);
636 /* If the controller ignores the cq head doorbell and continuously
637 * writes to the queue, it is theoretically possible to wrap around
638 * the queue twice and mistakenly return IRQ_NONE. Linux only
639 * requires that 0.1% of your interrupts are handled, so this isn't
642 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
645 writel(head, nvmeq->q_db + 1);
646 nvmeq->cq_head = head;
647 nvmeq->cq_phase = phase;
652 static irqreturn_t nvme_irq(int irq, void *data)
655 struct nvme_queue *nvmeq = data;
656 spin_lock(&nvmeq->q_lock);
657 result = nvme_process_cq(nvmeq);
658 spin_unlock(&nvmeq->q_lock);
662 static irqreturn_t nvme_irq_check(int irq, void *data)
664 struct nvme_queue *nvmeq = data;
665 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
666 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
668 return IRQ_WAKE_THREAD;
671 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
673 spin_lock_irq(&nvmeq->q_lock);
674 cancel_cmdid_data(nvmeq, cmdid);
675 spin_unlock_irq(&nvmeq->q_lock);
679 * Returns 0 on success. If the result is negative, it's a Linux error code;
680 * if the result is positive, it's an NVM Express status code
682 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
683 struct nvme_command *cmd, u32 *result, unsigned timeout)
686 struct sync_cmd_info cmdinfo;
688 cmdinfo.task = current;
689 cmdinfo.status = -EINTR;
691 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
695 cmd->common.command_id = cmdid;
697 set_current_state(TASK_KILLABLE);
698 nvme_submit_cmd(nvmeq, cmd);
701 if (cmdinfo.status == -EINTR) {
702 nvme_abort_command(nvmeq, cmdid);
707 *result = cmdinfo.result;
709 return cmdinfo.status;
712 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
715 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
718 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
721 struct nvme_command c;
723 memset(&c, 0, sizeof(c));
724 c.delete_queue.opcode = opcode;
725 c.delete_queue.qid = cpu_to_le16(id);
727 status = nvme_submit_admin_cmd(dev, &c, NULL);
733 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
734 struct nvme_queue *nvmeq)
737 struct nvme_command c;
738 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
740 memset(&c, 0, sizeof(c));
741 c.create_cq.opcode = nvme_admin_create_cq;
742 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
743 c.create_cq.cqid = cpu_to_le16(qid);
744 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
745 c.create_cq.cq_flags = cpu_to_le16(flags);
746 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
748 status = nvme_submit_admin_cmd(dev, &c, NULL);
754 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
755 struct nvme_queue *nvmeq)
758 struct nvme_command c;
759 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
761 memset(&c, 0, sizeof(c));
762 c.create_sq.opcode = nvme_admin_create_sq;
763 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
764 c.create_sq.sqid = cpu_to_le16(qid);
765 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
766 c.create_sq.sq_flags = cpu_to_le16(flags);
767 c.create_sq.cqid = cpu_to_le16(qid);
769 status = nvme_submit_admin_cmd(dev, &c, NULL);
775 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
777 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
780 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
782 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
785 static void nvme_free_queue(struct nvme_dev *dev, int qid)
787 struct nvme_queue *nvmeq = dev->queues[qid];
789 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
791 /* Don't tell the adapter to delete the admin queue */
793 adapter_delete_sq(dev, qid);
794 adapter_delete_cq(dev, qid);
797 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
798 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
799 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
800 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
804 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
805 int depth, int vector)
807 struct device *dmadev = &dev->pci_dev->dev;
808 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
809 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
813 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
814 &nvmeq->cq_dma_addr, GFP_KERNEL);
817 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
819 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
820 &nvmeq->sq_dma_addr, GFP_KERNEL);
824 nvmeq->q_dmadev = dmadev;
826 spin_lock_init(&nvmeq->q_lock);
829 init_waitqueue_head(&nvmeq->sq_full);
830 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
831 bio_list_init(&nvmeq->sq_cong);
832 nvmeq->q_db = &dev->dbs[qid * 2];
833 nvmeq->q_depth = depth;
834 nvmeq->cq_vector = vector;
839 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
846 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
849 if (use_threaded_interrupts)
850 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
851 nvme_irq_check, nvme_irq,
852 IRQF_DISABLED | IRQF_SHARED,
854 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
855 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
858 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
859 int qid, int cq_size, int vector)
862 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
867 result = adapter_alloc_cq(dev, qid, nvmeq);
871 result = adapter_alloc_sq(dev, qid, nvmeq);
875 result = queue_request_irq(dev, nvmeq, "nvme");
882 adapter_delete_sq(dev, qid);
884 adapter_delete_cq(dev, qid);
886 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
887 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
888 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
889 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
894 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
898 struct nvme_queue *nvmeq;
900 dev->dbs = ((void __iomem *)dev->bar) + 4096;
902 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
906 aqa = nvmeq->q_depth - 1;
909 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
910 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
911 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
913 writel(0, &dev->bar->cc);
914 writel(aqa, &dev->bar->aqa);
915 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
916 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
917 writel(dev->ctrl_config, &dev->bar->cc);
919 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
921 if (fatal_signal_pending(current))
925 result = queue_request_irq(dev, nvmeq, "nvme admin");
926 dev->queues[0] = nvmeq;
930 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
931 unsigned long addr, unsigned length,
932 struct scatterlist **sgp)
934 int i, err, count, nents, offset;
935 struct scatterlist *sg;
943 offset = offset_in_page(addr);
944 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
945 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
947 err = get_user_pages_fast(addr, count, 1, pages);
954 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
955 sg_init_table(sg, count);
956 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
957 length -= (PAGE_SIZE - offset);
958 for (i = 1; i < count; i++) {
959 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
964 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
965 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
974 for (i = 0; i < count; i++)
980 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
981 unsigned long addr, int length,
982 struct scatterlist *sg, int nents)
986 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
987 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
989 for (i = 0; i < count; i++)
990 put_page(sg_page(&sg[i]));
993 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
994 unsigned long addr, unsigned length,
995 struct nvme_command *cmd)
998 struct scatterlist *sg;
999 struct nvme_prps *prps;
1001 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1004 prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1005 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1006 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1007 nvme_free_prps(dev, prps);
1008 return err ? -EIO : 0;
1011 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1013 struct nvme_command c;
1015 memset(&c, 0, sizeof(c));
1016 c.identify.opcode = nvme_admin_identify;
1017 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1018 c.identify.cns = cpu_to_le32(cns);
1020 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1023 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1025 struct nvme_command c;
1027 memset(&c, 0, sizeof(c));
1028 c.features.opcode = nvme_admin_get_features;
1029 c.features.nsid = cpu_to_le32(ns->ns_id);
1030 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1032 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1035 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1037 struct nvme_dev *dev = ns->dev;
1038 struct nvme_queue *nvmeq;
1039 struct nvme_user_io io;
1040 struct nvme_command c;
1044 struct scatterlist *sg;
1045 struct nvme_prps *prps;
1047 if (copy_from_user(&io, uio, sizeof(io)))
1049 length = io.nblocks << io.block_shift;
1050 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
1054 memset(&c, 0, sizeof(c));
1055 c.rw.opcode = io.opcode;
1056 c.rw.flags = io.flags;
1057 c.rw.nsid = cpu_to_le32(io.nsid);
1058 c.rw.slba = cpu_to_le64(io.slba);
1059 c.rw.length = cpu_to_le16(io.nblocks - 1);
1060 c.rw.control = cpu_to_le16(io.control);
1061 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1062 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
1063 c.rw.apptag = cpu_to_le16(io.apptag);
1064 c.rw.appmask = cpu_to_le16(io.appmask);
1066 prps = nvme_setup_prps(dev, &c.common, sg, length);
1068 nvmeq = get_nvmeq(ns);
1069 /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1070 * disabled. We may be preempted at any point, and be rescheduled
1071 * to a different CPU. That will cause cacheline bouncing, but no
1072 * additional races since q_lock already protects against other CPUs.
1075 status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1077 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1078 nvme_free_prps(dev, prps);
1079 put_user(result, &uio->result);
1083 static int nvme_download_firmware(struct nvme_ns *ns,
1084 struct nvme_dlfw __user *udlfw)
1086 struct nvme_dev *dev = ns->dev;
1087 struct nvme_dlfw dlfw;
1088 struct nvme_command c;
1090 struct scatterlist *sg;
1091 struct nvme_prps *prps;
1093 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1095 if (dlfw.length >= (1 << 30))
1098 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1102 memset(&c, 0, sizeof(c));
1103 c.dlfw.opcode = nvme_admin_download_fw;
1104 c.dlfw.numd = cpu_to_le32(dlfw.length);
1105 c.dlfw.offset = cpu_to_le32(dlfw.offset);
1106 prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1108 status = nvme_submit_admin_cmd(dev, &c, NULL);
1109 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1110 nvme_free_prps(dev, prps);
1114 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1116 struct nvme_dev *dev = ns->dev;
1117 struct nvme_command c;
1119 memset(&c, 0, sizeof(c));
1120 c.common.opcode = nvme_admin_activate_fw;
1121 c.common.rsvd10[0] = cpu_to_le32(arg);
1123 return nvme_submit_admin_cmd(dev, &c, NULL);
1126 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1129 struct nvme_ns *ns = bdev->bd_disk->private_data;
1132 case NVME_IOCTL_IDENTIFY_NS:
1133 return nvme_identify(ns, arg, 0);
1134 case NVME_IOCTL_IDENTIFY_CTRL:
1135 return nvme_identify(ns, arg, 1);
1136 case NVME_IOCTL_GET_RANGE_TYPE:
1137 return nvme_get_range_type(ns, arg);
1138 case NVME_IOCTL_SUBMIT_IO:
1139 return nvme_submit_io(ns, (void __user *)arg);
1140 case NVME_IOCTL_DOWNLOAD_FW:
1141 return nvme_download_firmware(ns, (void __user *)arg);
1142 case NVME_IOCTL_ACTIVATE_FW:
1143 return nvme_activate_firmware(ns, arg);
1149 static const struct block_device_operations nvme_fops = {
1150 .owner = THIS_MODULE,
1151 .ioctl = nvme_ioctl,
1154 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1156 while (bio_list_peek(&nvmeq->sq_cong)) {
1157 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1158 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1159 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1160 bio_list_add_head(&nvmeq->sq_cong, bio);
1166 static int nvme_kthread(void *data)
1168 struct nvme_dev *dev;
1170 while (!kthread_should_stop()) {
1171 __set_current_state(TASK_RUNNING);
1172 spin_lock(&dev_list_lock);
1173 list_for_each_entry(dev, &dev_list, node) {
1175 for (i = 0; i < dev->queue_count; i++) {
1176 struct nvme_queue *nvmeq = dev->queues[i];
1179 spin_lock_irq(&nvmeq->q_lock);
1180 if (nvme_process_cq(nvmeq))
1181 printk("process_cq did something\n");
1182 nvme_resubmit_bios(nvmeq);
1183 spin_unlock_irq(&nvmeq->q_lock);
1186 spin_unlock(&dev_list_lock);
1187 set_current_state(TASK_INTERRUPTIBLE);
1188 schedule_timeout(HZ);
1193 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1194 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1197 struct gendisk *disk;
1200 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1203 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1206 ns->queue = blk_alloc_queue(GFP_KERNEL);
1209 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1210 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1211 blk_queue_make_request(ns->queue, nvme_make_request);
1213 ns->queue->queuedata = ns;
1215 disk = alloc_disk(NVME_MINORS);
1217 goto out_free_queue;
1220 lbaf = id->flbas & 0xf;
1221 ns->lba_shift = id->lbaf[lbaf].ds;
1223 disk->major = nvme_major;
1224 disk->minors = NVME_MINORS;
1225 disk->first_minor = NVME_MINORS * index;
1226 disk->fops = &nvme_fops;
1227 disk->private_data = ns;
1228 disk->queue = ns->queue;
1229 disk->driverfs_dev = &dev->pci_dev->dev;
1230 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1231 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1236 blk_cleanup_queue(ns->queue);
1242 static void nvme_ns_free(struct nvme_ns *ns)
1245 blk_cleanup_queue(ns->queue);
1249 static int set_queue_count(struct nvme_dev *dev, int count)
1253 struct nvme_command c;
1254 u32 q_count = (count - 1) | ((count - 1) << 16);
1256 memset(&c, 0, sizeof(c));
1257 c.features.opcode = nvme_admin_get_features;
1258 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1259 c.features.dword11 = cpu_to_le32(q_count);
1261 status = nvme_submit_admin_cmd(dev, &c, &result);
1264 return min(result & 0xffff, result >> 16) + 1;
1267 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1269 int result, cpu, i, nr_io_queues;
1271 nr_io_queues = num_online_cpus();
1272 result = set_queue_count(dev, nr_io_queues);
1275 if (result < nr_io_queues)
1276 nr_io_queues = result;
1278 /* Deregister the admin queue's interrupt */
1279 free_irq(dev->entry[0].vector, dev->queues[0]);
1281 for (i = 0; i < nr_io_queues; i++)
1282 dev->entry[i].entry = i;
1284 result = pci_enable_msix(dev->pci_dev, dev->entry,
1288 } else if (result > 0) {
1289 nr_io_queues = result;
1297 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1298 /* XXX: handle failure here */
1300 cpu = cpumask_first(cpu_online_mask);
1301 for (i = 0; i < nr_io_queues; i++) {
1302 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1303 cpu = cpumask_next(cpu, cpu_online_mask);
1306 for (i = 0; i < nr_io_queues; i++) {
1307 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1309 if (!dev->queues[i + 1])
1317 static void nvme_free_queues(struct nvme_dev *dev)
1321 for (i = dev->queue_count - 1; i >= 0; i--)
1322 nvme_free_queue(dev, i);
1325 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1328 struct nvme_ns *ns, *next;
1329 struct nvme_id_ctrl *ctrl;
1331 dma_addr_t dma_addr;
1332 struct nvme_command cid, crt;
1334 res = nvme_setup_io_queues(dev);
1338 /* XXX: Switch to a SG list once prp2 works */
1339 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1342 memset(&cid, 0, sizeof(cid));
1343 cid.identify.opcode = nvme_admin_identify;
1344 cid.identify.nsid = 0;
1345 cid.identify.prp1 = cpu_to_le64(dma_addr);
1346 cid.identify.cns = cpu_to_le32(1);
1348 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1355 nn = le32_to_cpup(&ctrl->nn);
1356 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1357 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1358 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1360 cid.identify.cns = 0;
1361 memset(&crt, 0, sizeof(crt));
1362 crt.features.opcode = nvme_admin_get_features;
1363 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1364 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1366 for (i = 0; i < nn; i++) {
1367 cid.identify.nsid = cpu_to_le32(i);
1368 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1372 if (((struct nvme_id_ns *)id)->ncap == 0)
1375 crt.features.nsid = cpu_to_le32(i);
1376 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1380 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1382 list_add_tail(&ns->list, &dev->namespaces);
1384 list_for_each_entry(ns, &dev->namespaces, list)
1387 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1391 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1392 list_del(&ns->list);
1396 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1400 static int nvme_dev_remove(struct nvme_dev *dev)
1402 struct nvme_ns *ns, *next;
1404 spin_lock(&dev_list_lock);
1405 list_del(&dev->node);
1406 spin_unlock(&dev_list_lock);
1408 /* TODO: wait all I/O finished or cancel them */
1410 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1411 list_del(&ns->list);
1412 del_gendisk(ns->disk);
1416 nvme_free_queues(dev);
1421 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1423 struct device *dmadev = &dev->pci_dev->dev;
1424 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1425 PAGE_SIZE, PAGE_SIZE, 0);
1426 if (!dev->prp_page_pool)
1429 /* Optimisation for I/Os between 4k and 128k */
1430 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1432 if (!dev->prp_small_pool) {
1433 dma_pool_destroy(dev->prp_page_pool);
1439 static void nvme_release_prp_pools(struct nvme_dev *dev)
1441 dma_pool_destroy(dev->prp_page_pool);
1442 dma_pool_destroy(dev->prp_small_pool);
1445 /* XXX: Use an ida or something to let remove / add work correctly */
1446 static void nvme_set_instance(struct nvme_dev *dev)
1448 static int instance;
1449 dev->instance = instance++;
1452 static void nvme_release_instance(struct nvme_dev *dev)
1456 static int __devinit nvme_probe(struct pci_dev *pdev,
1457 const struct pci_device_id *id)
1459 int bars, result = -ENOMEM;
1460 struct nvme_dev *dev;
1462 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1465 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1469 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1474 if (pci_enable_device_mem(pdev))
1476 pci_set_master(pdev);
1477 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1478 if (pci_request_selected_regions(pdev, bars, "nvme"))
1481 INIT_LIST_HEAD(&dev->namespaces);
1482 dev->pci_dev = pdev;
1483 pci_set_drvdata(pdev, dev);
1484 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1485 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1486 nvme_set_instance(dev);
1487 dev->entry[0].vector = pdev->irq;
1489 result = nvme_setup_prp_pools(dev);
1493 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1499 result = nvme_configure_admin_queue(dev);
1504 spin_lock(&dev_list_lock);
1505 list_add(&dev->node, &dev_list);
1506 spin_unlock(&dev_list_lock);
1508 result = nvme_dev_add(dev);
1515 spin_lock(&dev_list_lock);
1516 list_del(&dev->node);
1517 spin_unlock(&dev_list_lock);
1519 nvme_free_queues(dev);
1523 pci_disable_msix(pdev);
1524 nvme_release_instance(dev);
1525 nvme_release_prp_pools(dev);
1527 pci_disable_device(pdev);
1528 pci_release_regions(pdev);
1536 static void __devexit nvme_remove(struct pci_dev *pdev)
1538 struct nvme_dev *dev = pci_get_drvdata(pdev);
1539 nvme_dev_remove(dev);
1540 pci_disable_msix(pdev);
1542 nvme_release_instance(dev);
1543 nvme_release_prp_pools(dev);
1544 pci_disable_device(pdev);
1545 pci_release_regions(pdev);
1551 /* These functions are yet to be implemented */
1552 #define nvme_error_detected NULL
1553 #define nvme_dump_registers NULL
1554 #define nvme_link_reset NULL
1555 #define nvme_slot_reset NULL
1556 #define nvme_error_resume NULL
1557 #define nvme_suspend NULL
1558 #define nvme_resume NULL
1560 static struct pci_error_handlers nvme_err_handler = {
1561 .error_detected = nvme_error_detected,
1562 .mmio_enabled = nvme_dump_registers,
1563 .link_reset = nvme_link_reset,
1564 .slot_reset = nvme_slot_reset,
1565 .resume = nvme_error_resume,
1568 /* Move to pci_ids.h later */
1569 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1571 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1572 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1575 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1577 static struct pci_driver nvme_driver = {
1579 .id_table = nvme_id_table,
1580 .probe = nvme_probe,
1581 .remove = __devexit_p(nvme_remove),
1582 .suspend = nvme_suspend,
1583 .resume = nvme_resume,
1584 .err_handler = &nvme_err_handler,
1587 static int __init nvme_init(void)
1589 int result = -EBUSY;
1591 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1592 if (IS_ERR(nvme_thread))
1593 return PTR_ERR(nvme_thread);
1595 nvme_major = register_blkdev(nvme_major, "nvme");
1596 if (nvme_major <= 0)
1599 result = pci_register_driver(&nvme_driver);
1601 goto unregister_blkdev;
1605 unregister_blkdev(nvme_major, "nvme");
1607 kthread_stop(nvme_thread);
1611 static void __exit nvme_exit(void)
1613 pci_unregister_driver(&nvme_driver);
1614 unregister_blkdev(nvme_major, "nvme");
1615 kthread_stop(nvme_thread);
1618 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1619 MODULE_LICENSE("GPL");
1620 MODULE_VERSION("0.4");
1621 module_init(nvme_init);
1622 module_exit(nvme_exit);