drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         struct dma_pool *prp_page_pool;
  61         struct dma_pool *prp_small_pool;
  62         int instance;
  63         int queue_count;
  64         u32 ctrl_config;
  65         struct msix_entry *entry;
  66         struct nvme_bar __iomem *bar;
  67         struct list_head namespaces;
  68         char serial[20];
  69         char model[40];
  70         char firmware_rev[8];
  71 };
  72
  73 /*
  74  * An NVM Express namespace is equivalent to a SCSI LUN
  75  */
  76 struct nvme_ns {
  77         struct list_head list;
  78
  79         struct nvme_dev *dev;
  80         struct request_queue *queue;
  81         struct gendisk *disk;
  82
  83         int ns_id;
  84         int lba_shift;
  85 };
  86
  87 /*
  88  * An NVM Express queue.  Each device has at least two (one for admin
  89  * commands and one for I/O commands).
  90  */
  91 struct nvme_queue {
  92         struct device *q_dmadev;
  93         struct nvme_dev *dev;
  94         spinlock_t q_lock;
  95         struct nvme_command *sq_cmds;
  96         volatile struct nvme_completion *cqes;
  97         dma_addr_t sq_dma_addr;
  98         dma_addr_t cq_dma_addr;
  99         wait_queue_head_t sq_full;
 100         struct bio_list sq_cong;
 101         u32 __iomem *q_db;
 102         u16 q_depth;
 103         u16 cq_vector;
 104         u16 sq_head;
 105         u16 sq_tail;
 106         u16 cq_head;
 107         u16 cq_phase;
 108         unsigned long cmdid_data[];
 109 };
 110
 111 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 112
 113 /*
 114  * Check we didin't inadvertently grow the command struct
 115  */
 116 static inline void _nvme_check_size(void)
 117 {
 118         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 122         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 123         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 125         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 126         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 127 }
 128
 129 struct nvme_cmd_info {
 130         unsigned long ctx;
 131         unsigned long timeout;
 132 };
 133
 134 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 135 {
 136         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 137 }
 138
 139 /**
 140  * alloc_cmdid - Allocate a Command ID
 141  * @param nvmeq The queue that will be used for this command
 142  * @param ctx A pointer that will be passed to the handler
 143  * @param handler The ID of the handler to call
 144  *
 145  * Allocate a Command ID for a queue.  The data passed in will
 146  * be passed to the completion handler.  This is implemented by using
 147  * the bottom two bits of the ctx pointer to store the handler ID.
 148  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 149  * We can change this if it becomes a problem.
 150  */
 151 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 152                                                         unsigned timeout)
 153 {
 154         int depth = nvmeq->q_depth;
 155         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 156         int cmdid;
 157
 158         BUG_ON((unsigned long)ctx & 3);
 159
 160         do {
 161                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 162                 if (cmdid >= depth)
 163                         return -EBUSY;
 164         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 165
 166         info[cmdid].ctx = (unsigned long)ctx | handler;
 167         info[cmdid].timeout = jiffies + timeout;
 168         return cmdid;
 169 }
 170
 171 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 172                                                 int handler, unsigned timeout)
 173 {
 174         int cmdid;
 175         wait_event_killable(nvmeq->sq_full,
 176                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 177         return (cmdid < 0) ? -EINTR : cmdid;
 178 }
 179
 180 /* If you need more than four handlers, you'll need to change how
 181  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 182  * CMD_CTX value instead, if that works for your situation.
 183  */
 184 enum {
 185         sync_completion_id = 0,
 186         bio_completion_id,
 187 };
 188
 189 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 190 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 191 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 192 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 193
 194 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 195 {
 196         unsigned long data;
 197         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 198
 199         if (cmdid >= nvmeq->q_depth)
 200                 return CMD_CTX_INVALID;
 201         data = info[cmdid].ctx;
 202         info[cmdid].ctx = CMD_CTX_COMPLETED;
 203         clear_bit(cmdid, nvmeq->cmdid_data);
 204         wake_up(&nvmeq->sq_full);
 205         return data;
 206 }
 207
 208 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 209 {
 210         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 211         info[cmdid].ctx = CMD_CTX_CANCELLED;
 212 }
 213
 214 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 215 {
 216         int qid, cpu = get_cpu();
 217         if (cpu < ns->dev->queue_count)
 218                 qid = cpu + 1;
 219         else
 220                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 221         return ns->dev->queues[qid];
 222 }
 223
 224 static void put_nvmeq(struct nvme_queue *nvmeq)
 225 {
 226         put_cpu();
 227 }
 228
 229 /**
 230  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 231  * @nvmeq: The queue to use
 232  * @cmd: The command to send
 233  *
 234  * Safe to use from interrupt context
 235  */
 236 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 237 {
 238         unsigned long flags;
 239         u16 tail;
 240         /* XXX: Need to check tail isn't going to overrun head */
 241         spin_lock_irqsave(&nvmeq->q_lock, flags);
 242         tail = nvmeq->sq_tail;
 243         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 244         writel(tail, nvmeq->q_db);
 245         if (++tail == nvmeq->q_depth)
 246                 tail = 0;
 247         nvmeq->sq_tail = tail;
 248         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 249
 250         return 0;
 251 }
 252
 253 struct nvme_prps {
 254         int npages;
 255         dma_addr_t first_dma;
 256         __le64 *list[0];
 257 };
 258
 259 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 260 {
 261         const int last_prp = PAGE_SIZE / 8 - 1;
 262         int i;
 263         dma_addr_t prp_dma;
 264
 265         if (!prps)
 266                 return;
 267
 268         prp_dma = prps->first_dma;
 269
 270         if (prps->npages == 0)
 271                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 272         for (i = 0; i < prps->npages; i++) {
 273                 __le64 *prp_list = prps->list[i];
 274                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 275                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 276                 prp_dma = next_prp_dma;
 277         }
 278         kfree(prps);
 279 }
 280
 281 struct nvme_bio {
 282         struct bio *bio;
 283         int nents;
 284         struct nvme_prps *prps;
 285         struct scatterlist sg[0];
 286 };
 287
 288 /* XXX: use a mempool */
 289 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 290 {
 291         return kzalloc(sizeof(struct nvme_bio) +
 292                         sizeof(struct scatterlist) * nseg, gfp);
 293 }
 294
 295 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 296 {
 297         nvme_free_prps(nvmeq->dev, nbio->prps);
 298         kfree(nbio);
 299 }
 300
 301 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 302                                                 struct nvme_completion *cqe)
 303 {
 304         struct nvme_bio *nbio = ctx;
 305         struct bio *bio = nbio->bio;
 306         u16 status = le16_to_cpup(&cqe->status) >> 1;
 307
 308         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 309                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 310         free_nbio(nvmeq, nbio);
 311         bio_endio(bio, status ? -EIO : 0);
 312         bio = bio_list_pop(&nvmeq->sq_cong);
 313         if (bio)
 314                 nvme_resubmit_bio(nvmeq, bio);
 315 }
 316
 317 /* length is in bytes */
 318 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 319                                         struct nvme_common_command *cmd,
 320                                         struct scatterlist *sg, int length)
 321 {
 322         struct dma_pool *pool;
 323         int dma_len = sg_dma_len(sg);
 324         u64 dma_addr = sg_dma_address(sg);
 325         int offset = offset_in_page(dma_addr);
 326         __le64 *prp_list;
 327         dma_addr_t prp_dma;
 328         int nprps, npages, i, prp_page;
 329         struct nvme_prps *prps = NULL;
 330
 331         cmd->prp1 = cpu_to_le64(dma_addr);
 332         length -= (PAGE_SIZE - offset);
 333         if (length <= 0)
 334                 return prps;
 335
 336         dma_len -= (PAGE_SIZE - offset);
 337         if (dma_len) {
 338                 dma_addr += (PAGE_SIZE - offset);
 339         } else {
 340                 sg = sg_next(sg);
 341                 dma_addr = sg_dma_address(sg);
 342                 dma_len = sg_dma_len(sg);
 343         }
 344
 345         if (length <= PAGE_SIZE) {
 346                 cmd->prp2 = cpu_to_le64(dma_addr);
 347                 return prps;
 348         }
 349
 350         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 351         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 352         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 353         prp_page = 0;
 354         if (nprps <= (256 / 8)) {
 355                 pool = dev->prp_small_pool;
 356                 prps->npages = 0;
 357         } else {
 358                 pool = dev->prp_page_pool;
 359                 prps->npages = npages;
 360         }
 361
 362         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 363         prps->list[prp_page++] = prp_list;
 364         prps->first_dma = prp_dma;
 365         cmd->prp2 = cpu_to_le64(prp_dma);
 366         i = 0;
 367         for (;;) {
 368                 if (i == PAGE_SIZE / 8 - 1) {
 369                         __le64 *old_prp_list = prp_list;
 370                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 371                         prps->list[prp_page++] = prp_list;
 372                         old_prp_list[i] = cpu_to_le64(prp_dma);
 373                         i = 0;
 374                 }
 375                 prp_list[i++] = cpu_to_le64(dma_addr);
 376                 dma_len -= PAGE_SIZE;
 377                 dma_addr += PAGE_SIZE;
 378                 length -= PAGE_SIZE;
 379                 if (length <= 0)
 380                         break;
 381                 if (dma_len > 0)
 382                         continue;
 383                 BUG_ON(dma_len < 0);
 384                 sg = sg_next(sg);
 385                 dma_addr = sg_dma_address(sg);
 386                 dma_len = sg_dma_len(sg);
 387         }
 388
 389         return prps;
 390 }
 391
 392 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 393                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 394 {
 395         struct bio_vec *bvec, *bvprv = NULL;
 396         struct scatterlist *sg = NULL;
 397         int i, nsegs = 0;
 398
 399         sg_init_table(nbio->sg, psegs);
 400         bio_for_each_segment(bvec, bio, i) {
 401                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 402                         sg->length += bvec->bv_len;
 403                 } else {
 404                         /* Check bvprv && offset == 0 */
 405                         sg = sg ? sg + 1 : nbio->sg;
 406                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 407                                                         bvec->bv_offset);
 408                         nsegs++;
 409                 }
 410                 bvprv = bvec;
 411         }
 412         nbio->nents = nsegs;
 413         sg_mark_end(sg);
 414         return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
 415 }
 416
 417 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 418                                                                 struct bio *bio)
 419 {
 420         struct nvme_command *cmnd;
 421         struct nvme_bio *nbio;
 422         enum dma_data_direction dma_dir;
 423         int cmdid;
 424         u16 control;
 425         u32 dsmgmt;
 426         unsigned long flags;
 427         int psegs = bio_phys_segments(ns->queue, bio);
 428
 429         nbio = alloc_nbio(psegs, GFP_NOIO);
 430         if (!nbio)
 431                 goto congestion;
 432         nbio->bio = bio;
 433
 434         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 435         if (unlikely(cmdid < 0))
 436                 goto free_nbio;
 437
 438         control = 0;
 439         if (bio->bi_rw & REQ_FUA)
 440                 control |= NVME_RW_FUA;
 441         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 442                 control |= NVME_RW_LR;
 443
 444         dsmgmt = 0;
 445         if (bio->bi_rw & REQ_RAHEAD)
 446                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 447
 448         spin_lock_irqsave(&nvmeq->q_lock, flags);
 449         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 450
 451         memset(cmnd, 0, sizeof(*cmnd));
 452         if (bio_data_dir(bio)) {
 453                 cmnd->rw.opcode = nvme_cmd_write;
 454                 dma_dir = DMA_TO_DEVICE;
 455         } else {
 456                 cmnd->rw.opcode = nvme_cmd_read;
 457                 dma_dir = DMA_FROM_DEVICE;
 458         }
 459
 460         if (nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs) == 0)
 461                 goto mapping_failed;
 462
 463         cmnd->rw.flags = 1;
 464         cmnd->rw.command_id = cmdid;
 465         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 466         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 467                                                                 bio->bi_size);
 468         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 469         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 470         cmnd->rw.control = cpu_to_le16(control);
 471         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 472
 473         writel(nvmeq->sq_tail, nvmeq->q_db);
 474         if (++nvmeq->sq_tail == nvmeq->q_depth)
 475                 nvmeq->sq_tail = 0;
 476
 477         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 478
 479         return 0;
 480
 481  mapping_failed:
 482         free_nbio(nvmeq, nbio);
 483         bio_endio(bio, -ENOMEM);
 484         return 0;
 485
 486  free_nbio:
 487         free_nbio(nvmeq, nbio);
 488  congestion:
 489         return -EBUSY;
 490 }
 491
 492 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 493 {
 494         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 495         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 496                 bio_list_add_head(&nvmeq->sq_cong, bio);
 497         else if (bio_list_empty(&nvmeq->sq_cong))
 498                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 499         /* XXX: Need to duplicate the logic from __freed_request here */
 500 }
 501
 502 /*
 503  * NB: return value of non-zero would mean that we were a stacking driver.
 504  * make_request must always succeed.
 505  */
 506 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 507 {
 508         struct nvme_ns *ns = q->queuedata;
 509         struct nvme_queue *nvmeq = get_nvmeq(ns);
 510
 511         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 512                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 513                 spin_lock_irq(&nvmeq->q_lock);
 514                 bio_list_add(&nvmeq->sq_cong, bio);
 515                 spin_unlock_irq(&nvmeq->q_lock);
 516         }
 517         put_nvmeq(nvmeq);
 518
 519         return 0;
 520 }
 521
 522 struct sync_cmd_info {
 523         struct task_struct *task;
 524         u32 result;
 525         int status;
 526 };
 527
 528 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 529                                                 struct nvme_completion *cqe)
 530 {
 531         struct sync_cmd_info *cmdinfo = ctx;
 532         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 533                 return;
 534         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 535                 dev_warn(nvmeq->q_dmadev,
 536                                 "completed id %d twice on queue %d\n",
 537                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 538                 return;
 539         }
 540         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 541                 dev_warn(nvmeq->q_dmadev,
 542                                 "invalid id %d completed on queue %d\n",
 543                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 544                 return;
 545         }
 546         cmdinfo->result = le32_to_cpup(&cqe->result);
 547         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 548         wake_up_process(cmdinfo->task);
 549 }
 550
 551 typedef void (*completion_fn)(struct nvme_queue *, void *,
 552                                                 struct nvme_completion *);
 553
 554 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 555 {
 556         u16 head, phase;
 557
 558         static const completion_fn completions[4] = {
 559                 [sync_completion_id] = sync_completion,
 560                 [bio_completion_id]  = bio_completion,
 561         };
 562
 563         head = nvmeq->cq_head;
 564         phase = nvmeq->cq_phase;
 565
 566         for (;;) {
 567                 unsigned long data;
 568                 void *ptr;
 569                 unsigned char handler;
 570                 struct nvme_completion cqe = nvmeq->cqes[head];
 571                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 572                         break;
 573                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 574                 if (++head == nvmeq->q_depth) {
 575                         head = 0;
 576                         phase = !phase;
 577                 }
 578
 579                 data = free_cmdid(nvmeq, cqe.command_id);
 580                 handler = data & 3;
 581                 ptr = (void *)(data & ~3UL);
 582                 completions[handler](nvmeq, ptr, &cqe);
 583         }
 584
 585         /* If the controller ignores the cq head doorbell and continuously
 586          * writes to the queue, it is theoretically possible to wrap around
 587          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 588          * requires that 0.1% of your interrupts are handled, so this isn't
 589          * a big problem.
 590          */
 591         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 592                 return IRQ_NONE;
 593
 594         writel(head, nvmeq->q_db + 1);
 595         nvmeq->cq_head = head;
 596         nvmeq->cq_phase = phase;
 597
 598         return IRQ_HANDLED;
 599 }
 600
 601 static irqreturn_t nvme_irq(int irq, void *data)
 602 {
 603         irqreturn_t result;
 604         struct nvme_queue *nvmeq = data;
 605         spin_lock(&nvmeq->q_lock);
 606         result = nvme_process_cq(nvmeq);
 607         spin_unlock(&nvmeq->q_lock);
 608         return result;
 609 }
 610
 611 static irqreturn_t nvme_irq_check(int irq, void *data)
 612 {
 613         struct nvme_queue *nvmeq = data;
 614         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 615         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 616                 return IRQ_NONE;
 617         return IRQ_WAKE_THREAD;
 618 }
 619
 620 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 621 {
 622         spin_lock_irq(&nvmeq->q_lock);
 623         cancel_cmdid_data(nvmeq, cmdid);
 624         spin_unlock_irq(&nvmeq->q_lock);
 625 }
 626
 627 /*
 628  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 629  * if the result is positive, it's an NVM Express status code
 630  */
 631 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 632                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 633 {
 634         int cmdid;
 635         struct sync_cmd_info cmdinfo;
 636
 637         cmdinfo.task = current;
 638         cmdinfo.status = -EINTR;
 639
 640         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 641                                                                 timeout);
 642         if (cmdid < 0)
 643                 return cmdid;
 644         cmd->common.command_id = cmdid;
 645
 646         set_current_state(TASK_KILLABLE);
 647         nvme_submit_cmd(nvmeq, cmd);
 648         schedule();
 649
 650         if (cmdinfo.status == -EINTR) {
 651                 nvme_abort_command(nvmeq, cmdid);
 652                 return -EINTR;
 653         }
 654
 655         if (result)
 656                 *result = cmdinfo.result;
 657
 658         return cmdinfo.status;
 659 }
 660
 661 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 662                                                                 u32 *result)
 663 {
 664         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 665 }
 666
 667 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 668 {
 669         int status;
 670         struct nvme_command c;
 671
 672         memset(&c, 0, sizeof(c));
 673         c.delete_queue.opcode = opcode;
 674         c.delete_queue.qid = cpu_to_le16(id);
 675
 676         status = nvme_submit_admin_cmd(dev, &c, NULL);
 677         if (status)
 678                 return -EIO;
 679         return 0;
 680 }
 681
 682 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 683                                                 struct nvme_queue *nvmeq)
 684 {
 685         int status;
 686         struct nvme_command c;
 687         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 688
 689         memset(&c, 0, sizeof(c));
 690         c.create_cq.opcode = nvme_admin_create_cq;
 691         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 692         c.create_cq.cqid = cpu_to_le16(qid);
 693         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 694         c.create_cq.cq_flags = cpu_to_le16(flags);
 695         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 696
 697         status = nvme_submit_admin_cmd(dev, &c, NULL);
 698         if (status)
 699                 return -EIO;
 700         return 0;
 701 }
 702
 703 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 704                                                 struct nvme_queue *nvmeq)
 705 {
 706         int status;
 707         struct nvme_command c;
 708         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 709
 710         memset(&c, 0, sizeof(c));
 711         c.create_sq.opcode = nvme_admin_create_sq;
 712         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 713         c.create_sq.sqid = cpu_to_le16(qid);
 714         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 715         c.create_sq.sq_flags = cpu_to_le16(flags);
 716         c.create_sq.cqid = cpu_to_le16(qid);
 717
 718         status = nvme_submit_admin_cmd(dev, &c, NULL);
 719         if (status)
 720                 return -EIO;
 721         return 0;
 722 }
 723
 724 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 725 {
 726         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 727 }
 728
 729 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 730 {
 731         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 732 }
 733
 734 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 735 {
 736         struct nvme_queue *nvmeq = dev->queues[qid];
 737
 738         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 739
 740         /* Don't tell the adapter to delete the admin queue */
 741         if (qid) {
 742                 adapter_delete_sq(dev, qid);
 743                 adapter_delete_cq(dev, qid);
 744         }
 745
 746         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 747                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 748         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 749                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 750         kfree(nvmeq);
 751 }
 752
 753 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 754                                                         int depth, int vector)
 755 {
 756         struct device *dmadev = &dev->pci_dev->dev;
 757         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 758         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 759         if (!nvmeq)
 760                 return NULL;
 761
 762         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 763                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 764         if (!nvmeq->cqes)
 765                 goto free_nvmeq;
 766         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 767
 768         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 769                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 770         if (!nvmeq->sq_cmds)
 771                 goto free_cqdma;
 772
 773         nvmeq->q_dmadev = dmadev;
 774         nvmeq->dev = dev;
 775         spin_lock_init(&nvmeq->q_lock);
 776         nvmeq->cq_head = 0;
 777         nvmeq->cq_phase = 1;
 778         init_waitqueue_head(&nvmeq->sq_full);
 779         bio_list_init(&nvmeq->sq_cong);
 780         nvmeq->q_db = &dev->dbs[qid * 2];
 781         nvmeq->q_depth = depth;
 782         nvmeq->cq_vector = vector;
 783
 784         return nvmeq;
 785
 786  free_cqdma:
 787         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 788                                                         nvmeq->cq_dma_addr);
 789  free_nvmeq:
 790         kfree(nvmeq);
 791         return NULL;
 792 }
 793
 794 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 795                                                         const char *name)
 796 {
 797         if (use_threaded_interrupts)
 798                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 799                                         nvme_irq_check, nvme_irq,
 800                                         IRQF_DISABLED | IRQF_SHARED,
 801                                         name, nvmeq);
 802         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 803                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 804 }
 805
 806 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 807                                         int qid, int cq_size, int vector)
 808 {
 809         int result;
 810         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 811
 812         if (!nvmeq)
 813                 return NULL;
 814
 815         result = adapter_alloc_cq(dev, qid, nvmeq);
 816         if (result < 0)
 817                 goto free_nvmeq;
 818
 819         result = adapter_alloc_sq(dev, qid, nvmeq);
 820         if (result < 0)
 821                 goto release_cq;
 822
 823         result = queue_request_irq(dev, nvmeq, "nvme");
 824         if (result < 0)
 825                 goto release_sq;
 826
 827         return nvmeq;
 828
 829  release_sq:
 830         adapter_delete_sq(dev, qid);
 831  release_cq:
 832         adapter_delete_cq(dev, qid);
 833  free_nvmeq:
 834         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 835                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 836         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 837                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 838         kfree(nvmeq);
 839         return NULL;
 840 }
 841
 842 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 843 {
 844         int result;
 845         u32 aqa;
 846         struct nvme_queue *nvmeq;
 847
 848         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 849
 850         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 851         if (!nvmeq)
 852                 return -ENOMEM;
 853
 854         aqa = nvmeq->q_depth - 1;
 855         aqa |= aqa << 16;
 856
 857         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 858         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 859         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 860
 861         writel(0, &dev->bar->cc);
 862         writel(aqa, &dev->bar->aqa);
 863         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 864         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 865         writel(dev->ctrl_config, &dev->bar->cc);
 866
 867         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 868                 msleep(100);
 869                 if (fatal_signal_pending(current))
 870                         return -EINTR;
 871         }
 872
 873         result = queue_request_irq(dev, nvmeq, "nvme admin");
 874         dev->queues[0] = nvmeq;
 875         return result;
 876 }
 877
 878 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 879                                 unsigned long addr, unsigned length,
 880                                 struct scatterlist **sgp)
 881 {
 882         int i, err, count, nents, offset;
 883         struct scatterlist *sg;
 884         struct page **pages;
 885
 886         if (addr & 3)
 887                 return -EINVAL;
 888         if (!length)
 889                 return -EINVAL;
 890
 891         offset = offset_in_page(addr);
 892         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 893         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 894
 895         err = get_user_pages_fast(addr, count, 1, pages);
 896         if (err < count) {
 897                 count = err;
 898                 err = -EFAULT;
 899                 goto put_pages;
 900         }
 901
 902         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 903         sg_init_table(sg, count);
 904         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 905         length -= (PAGE_SIZE - offset);
 906         for (i = 1; i < count; i++) {
 907                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 908                 length -= PAGE_SIZE;
 909         }
 910
 911         err = -ENOMEM;
 912         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 913                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 914         if (!nents)
 915                 goto put_pages;
 916
 917         kfree(pages);
 918         *sgp = sg;
 919         return nents;
 920
 921  put_pages:
 922         for (i = 0; i < count; i++)
 923                 put_page(pages[i]);
 924         kfree(pages);
 925         return err;
 926 }
 927
 928 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 929                                 unsigned long addr, int length,
 930                                 struct scatterlist *sg, int nents)
 931 {
 932         int i, count;
 933
 934         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 935         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 936
 937         for (i = 0; i < count; i++)
 938                 put_page(sg_page(&sg[i]));
 939 }
 940
 941 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 942                                         unsigned long addr, unsigned length,
 943                                         struct nvme_command *cmd)
 944 {
 945         int err, nents;
 946         struct scatterlist *sg;
 947         struct nvme_prps *prps;
 948
 949         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 950         if (nents < 0)
 951                 return nents;
 952         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
 953         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 954         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 955         nvme_free_prps(dev, prps);
 956         return err ? -EIO : 0;
 957 }
 958
 959 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 960 {
 961         struct nvme_command c;
 962
 963         memset(&c, 0, sizeof(c));
 964         c.identify.opcode = nvme_admin_identify;
 965         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 966         c.identify.cns = cpu_to_le32(cns);
 967
 968         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 969 }
 970
 971 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 972 {
 973         struct nvme_command c;
 974
 975         memset(&c, 0, sizeof(c));
 976         c.features.opcode = nvme_admin_get_features;
 977         c.features.nsid = cpu_to_le32(ns->ns_id);
 978         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 979
 980         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 981 }
 982
 983 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 984 {
 985         struct nvme_dev *dev = ns->dev;
 986         struct nvme_queue *nvmeq;
 987         struct nvme_user_io io;
 988         struct nvme_command c;
 989         unsigned length;
 990         u32 result;
 991         int nents, status;
 992         struct scatterlist *sg;
 993         struct nvme_prps *prps;
 994
 995         if (copy_from_user(&io, uio, sizeof(io)))
 996                 return -EFAULT;
 997         length = io.nblocks << io.block_shift;
 998         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 999         if (nents < 0)
1000                 return nents;
1001
1002         memset(&c, 0, sizeof(c));
1003         c.rw.opcode = io.opcode;
1004         c.rw.flags = io.flags;
1005         c.rw.nsid = cpu_to_le32(io.nsid);
1006         c.rw.slba = cpu_to_le64(io.slba);
1007         c.rw.length = cpu_to_le16(io.nblocks - 1);
1008         c.rw.control = cpu_to_le16(io.control);
1009         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1010         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1011         c.rw.apptag = cpu_to_le16(io.apptag);
1012         c.rw.appmask = cpu_to_le16(io.appmask);
1013         /* XXX: metadata */
1014         prps = nvme_setup_prps(dev, &c.common, sg, length);
1015
1016         nvmeq = get_nvmeq(ns);
1017         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1018          * disabled.  We may be preempted at any point, and be rescheduled
1019          * to a different CPU.  That will cause cacheline bouncing, but no
1020          * additional races since q_lock already protects against other CPUs.
1021          */
1022         put_nvmeq(nvmeq);
1023         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1024
1025         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1026         nvme_free_prps(dev, prps);
1027         put_user(result, &uio->result);
1028         return status;
1029 }
1030
1031 static int nvme_download_firmware(struct nvme_ns *ns,
1032                                                 struct nvme_dlfw __user *udlfw)
1033 {
1034         struct nvme_dev *dev = ns->dev;
1035         struct nvme_dlfw dlfw;
1036         struct nvme_command c;
1037         int nents, status;
1038         struct scatterlist *sg;
1039         struct nvme_prps *prps;
1040
1041         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1042                 return -EFAULT;
1043         if (dlfw.length >= (1 << 30))
1044                 return -EINVAL;
1045
1046         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1047         if (nents < 0)
1048                 return nents;
1049
1050         memset(&c, 0, sizeof(c));
1051         c.dlfw.opcode = nvme_admin_download_fw;
1052         c.dlfw.numd = cpu_to_le32(dlfw.length);
1053         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1054         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1055
1056         status = nvme_submit_admin_cmd(dev, &c, NULL);
1057         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1058         nvme_free_prps(dev, prps);
1059         return status;
1060 }
1061
1062 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1063 {
1064         struct nvme_dev *dev = ns->dev;
1065         struct nvme_command c;
1066
1067         memset(&c, 0, sizeof(c));
1068         c.common.opcode = nvme_admin_activate_fw;
1069         c.common.rsvd10[0] = cpu_to_le32(arg);
1070
1071         return nvme_submit_admin_cmd(dev, &c, NULL);
1072 }
1073
1074 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1075                                                         unsigned long arg)
1076 {
1077         struct nvme_ns *ns = bdev->bd_disk->private_data;
1078
1079         switch (cmd) {
1080         case NVME_IOCTL_IDENTIFY_NS:
1081                 return nvme_identify(ns, arg, 0);
1082         case NVME_IOCTL_IDENTIFY_CTRL:
1083                 return nvme_identify(ns, arg, 1);
1084         case NVME_IOCTL_GET_RANGE_TYPE:
1085                 return nvme_get_range_type(ns, arg);
1086         case NVME_IOCTL_SUBMIT_IO:
1087                 return nvme_submit_io(ns, (void __user *)arg);
1088         case NVME_IOCTL_DOWNLOAD_FW:
1089                 return nvme_download_firmware(ns, (void __user *)arg);
1090         case NVME_IOCTL_ACTIVATE_FW:
1091                 return nvme_activate_firmware(ns, arg);
1092         default:
1093                 return -ENOTTY;
1094         }
1095 }
1096
1097 static const struct block_device_operations nvme_fops = {
1098         .owner          = THIS_MODULE,
1099         .ioctl          = nvme_ioctl,
1100 };
1101
1102 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1103                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1104 {
1105         struct nvme_ns *ns;
1106         struct gendisk *disk;
1107         int lbaf;
1108
1109         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1110                 return NULL;
1111
1112         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1113         if (!ns)
1114                 return NULL;
1115         ns->queue = blk_alloc_queue(GFP_KERNEL);
1116         if (!ns->queue)
1117                 goto out_free_ns;
1118         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1119                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1120         blk_queue_make_request(ns->queue, nvme_make_request);
1121         ns->dev = dev;
1122         ns->queue->queuedata = ns;
1123
1124         disk = alloc_disk(NVME_MINORS);
1125         if (!disk)
1126                 goto out_free_queue;
1127         ns->ns_id = index;
1128         ns->disk = disk;
1129         lbaf = id->flbas & 0xf;
1130         ns->lba_shift = id->lbaf[lbaf].ds;
1131
1132         disk->major = nvme_major;
1133         disk->minors = NVME_MINORS;
1134         disk->first_minor = NVME_MINORS * index;
1135         disk->fops = &nvme_fops;
1136         disk->private_data = ns;
1137         disk->queue = ns->queue;
1138         disk->driverfs_dev = &dev->pci_dev->dev;
1139         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1140         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1141
1142         return ns;
1143
1144  out_free_queue:
1145         blk_cleanup_queue(ns->queue);
1146  out_free_ns:
1147         kfree(ns);
1148         return NULL;
1149 }
1150
1151 static void nvme_ns_free(struct nvme_ns *ns)
1152 {
1153         put_disk(ns->disk);
1154         blk_cleanup_queue(ns->queue);
1155         kfree(ns);
1156 }
1157
1158 static int set_queue_count(struct nvme_dev *dev, int count)
1159 {
1160         int status;
1161         u32 result;
1162         struct nvme_command c;
1163         u32 q_count = (count - 1) | ((count - 1) << 16);
1164
1165         memset(&c, 0, sizeof(c));
1166         c.features.opcode = nvme_admin_get_features;
1167         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1168         c.features.dword11 = cpu_to_le32(q_count);
1169
1170         status = nvme_submit_admin_cmd(dev, &c, &result);
1171         if (status)
1172                 return -EIO;
1173         return min(result & 0xffff, result >> 16) + 1;
1174 }
1175
1176 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1177 {
1178         int result, cpu, i, nr_queues;
1179
1180         nr_queues = num_online_cpus();
1181         result = set_queue_count(dev, nr_queues);
1182         if (result < 0)
1183                 return result;
1184         if (result < nr_queues)
1185                 nr_queues = result;
1186
1187         /* Deregister the admin queue's interrupt */
1188         free_irq(dev->entry[0].vector, dev->queues[0]);
1189
1190         for (i = 0; i < nr_queues; i++)
1191                 dev->entry[i].entry = i;
1192         for (;;) {
1193                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1194                 if (result == 0) {
1195                         break;
1196                 } else if (result > 0) {
1197                         nr_queues = result;
1198                         continue;
1199                 } else {
1200                         nr_queues = 1;
1201                         break;
1202                 }
1203         }
1204
1205         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1206         /* XXX: handle failure here */
1207
1208         cpu = cpumask_first(cpu_online_mask);
1209         for (i = 0; i < nr_queues; i++) {
1210                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1211                 cpu = cpumask_next(cpu, cpu_online_mask);
1212         }
1213
1214         for (i = 0; i < nr_queues; i++) {
1215                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1216                                                         NVME_Q_DEPTH, i);
1217                 if (!dev->queues[i + 1])
1218                         return -ENOMEM;
1219                 dev->queue_count++;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static void nvme_free_queues(struct nvme_dev *dev)
1226 {
1227         int i;
1228
1229         for (i = dev->queue_count - 1; i >= 0; i--)
1230                 nvme_free_queue(dev, i);
1231 }
1232
1233 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1234 {
1235         int res, nn, i;
1236         struct nvme_ns *ns, *next;
1237         struct nvme_id_ctrl *ctrl;
1238         void *id;
1239         dma_addr_t dma_addr;
1240         struct nvme_command cid, crt;
1241
1242         res = nvme_setup_io_queues(dev);
1243         if (res)
1244                 return res;
1245
1246         /* XXX: Switch to a SG list once prp2 works */
1247         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1248                                                                 GFP_KERNEL);
1249
1250         memset(&cid, 0, sizeof(cid));
1251         cid.identify.opcode = nvme_admin_identify;
1252         cid.identify.nsid = 0;
1253         cid.identify.prp1 = cpu_to_le64(dma_addr);
1254         cid.identify.cns = cpu_to_le32(1);
1255
1256         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1257         if (res) {
1258                 res = -EIO;
1259                 goto out_free;
1260         }
1261
1262         ctrl = id;
1263         nn = le32_to_cpup(&ctrl->nn);
1264         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1265         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1266         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1267
1268         cid.identify.cns = 0;
1269         memset(&crt, 0, sizeof(crt));
1270         crt.features.opcode = nvme_admin_get_features;
1271         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1272         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1273
1274         for (i = 0; i < nn; i++) {
1275                 cid.identify.nsid = cpu_to_le32(i);
1276                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1277                 if (res)
1278                         continue;
1279
1280                 if (((struct nvme_id_ns *)id)->ncap == 0)
1281                         continue;
1282
1283                 crt.features.nsid = cpu_to_le32(i);
1284                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1285                 if (res)
1286                         continue;
1287
1288                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1289                 if (ns)
1290                         list_add_tail(&ns->list, &dev->namespaces);
1291         }
1292         list_for_each_entry(ns, &dev->namespaces, list)
1293                 add_disk(ns->disk);
1294
1295         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1296         return 0;
1297
1298  out_free:
1299         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1300                 list_del(&ns->list);
1301                 nvme_ns_free(ns);
1302         }
1303
1304         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1305         return res;
1306 }
1307
1308 static int nvme_dev_remove(struct nvme_dev *dev)
1309 {
1310         struct nvme_ns *ns, *next;
1311
1312         /* TODO: wait all I/O finished or cancel them */
1313
1314         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1315                 list_del(&ns->list);
1316                 del_gendisk(ns->disk);
1317                 nvme_ns_free(ns);
1318         }
1319
1320         nvme_free_queues(dev);
1321
1322         return 0;
1323 }
1324
1325 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1326 {
1327         struct device *dmadev = &dev->pci_dev->dev;
1328         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1329                                                 PAGE_SIZE, PAGE_SIZE, 0);
1330         if (!dev->prp_page_pool)
1331                 return -ENOMEM;
1332
1333         /* Optimisation for I/Os between 4k and 128k */
1334         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1335                                                 256, 256, 0);
1336         if (!dev->prp_small_pool) {
1337                 dma_pool_destroy(dev->prp_page_pool);
1338                 return -ENOMEM;
1339         }
1340         return 0;
1341 }
1342
1343 static void nvme_release_prp_pools(struct nvme_dev *dev)
1344 {
1345         dma_pool_destroy(dev->prp_page_pool);
1346         dma_pool_destroy(dev->prp_small_pool);
1347 }
1348
1349 /* XXX: Use an ida or something to let remove / add work correctly */
1350 static void nvme_set_instance(struct nvme_dev *dev)
1351 {
1352         static int instance;
1353         dev->instance = instance++;
1354 }
1355
1356 static void nvme_release_instance(struct nvme_dev *dev)
1357 {
1358 }
1359
1360 static int __devinit nvme_probe(struct pci_dev *pdev,
1361                                                 const struct pci_device_id *id)
1362 {
1363         int bars, result = -ENOMEM;
1364         struct nvme_dev *dev;
1365
1366         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1367         if (!dev)
1368                 return -ENOMEM;
1369         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1370                                                                 GFP_KERNEL);
1371         if (!dev->entry)
1372                 goto free;
1373         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1374                                                                 GFP_KERNEL);
1375         if (!dev->queues)
1376                 goto free;
1377
1378         if (pci_enable_device_mem(pdev))
1379                 goto free;
1380         pci_set_master(pdev);
1381         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1382         if (pci_request_selected_regions(pdev, bars, "nvme"))
1383                 goto disable;
1384
1385         INIT_LIST_HEAD(&dev->namespaces);
1386         dev->pci_dev = pdev;
1387         pci_set_drvdata(pdev, dev);
1388         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1389         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1390         nvme_set_instance(dev);
1391         dev->entry[0].vector = pdev->irq;
1392
1393         result = nvme_setup_prp_pools(dev);
1394         if (result)
1395                 goto disable_msix;
1396
1397         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1398         if (!dev->bar) {
1399                 result = -ENOMEM;
1400                 goto disable_msix;
1401         }
1402
1403         result = nvme_configure_admin_queue(dev);
1404         if (result)
1405                 goto unmap;
1406         dev->queue_count++;
1407
1408         result = nvme_dev_add(dev);
1409         if (result)
1410                 goto delete;
1411         return 0;
1412
1413  delete:
1414         nvme_free_queues(dev);
1415  unmap:
1416         iounmap(dev->bar);
1417  disable_msix:
1418         pci_disable_msix(pdev);
1419         nvme_release_instance(dev);
1420         nvme_release_prp_pools(dev);
1421  disable:
1422         pci_disable_device(pdev);
1423         pci_release_regions(pdev);
1424  free:
1425         kfree(dev->queues);
1426         kfree(dev->entry);
1427         kfree(dev);
1428         return result;
1429 }
1430
1431 static void __devexit nvme_remove(struct pci_dev *pdev)
1432 {
1433         struct nvme_dev *dev = pci_get_drvdata(pdev);
1434         nvme_dev_remove(dev);
1435         pci_disable_msix(pdev);
1436         iounmap(dev->bar);
1437         nvme_release_instance(dev);
1438         nvme_release_prp_pools(dev);
1439         pci_disable_device(pdev);
1440         pci_release_regions(pdev);
1441         kfree(dev->queues);
1442         kfree(dev->entry);
1443         kfree(dev);
1444 }
1445
1446 /* These functions are yet to be implemented */
1447 #define nvme_error_detected NULL
1448 #define nvme_dump_registers NULL
1449 #define nvme_link_reset NULL
1450 #define nvme_slot_reset NULL
1451 #define nvme_error_resume NULL
1452 #define nvme_suspend NULL
1453 #define nvme_resume NULL
1454
1455 static struct pci_error_handlers nvme_err_handler = {
1456         .error_detected = nvme_error_detected,
1457         .mmio_enabled   = nvme_dump_registers,
1458         .link_reset     = nvme_link_reset,
1459         .slot_reset     = nvme_slot_reset,
1460         .resume         = nvme_error_resume,
1461 };
1462
1463 /* Move to pci_ids.h later */
1464 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1465
1466 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1467         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1468         { 0, }
1469 };
1470 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1471
1472 static struct pci_driver nvme_driver = {
1473         .name           = "nvme",
1474         .id_table       = nvme_id_table,
1475         .probe          = nvme_probe,
1476         .remove         = __devexit_p(nvme_remove),
1477         .suspend        = nvme_suspend,
1478         .resume         = nvme_resume,
1479         .err_handler    = &nvme_err_handler,
1480 };
1481
1482 static int __init nvme_init(void)
1483 {
1484         int result;
1485
1486         nvme_major = register_blkdev(nvme_major, "nvme");
1487         if (nvme_major <= 0)
1488                 return -EBUSY;
1489
1490         result = pci_register_driver(&nvme_driver);
1491         if (!result)
1492                 return 0;
1493
1494         unregister_blkdev(nvme_major, "nvme");
1495         return result;
1496 }
1497
1498 static void __exit nvme_exit(void)
1499 {
1500         pci_unregister_driver(&nvme_driver);
1501         unregister_blkdev(nvme_major, "nvme");
1502 }
1503
1504 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1505 MODULE_LICENSE("GPL");
1506 MODULE_VERSION("0.2");
1507 module_init(nvme_init);
1508 module_exit(nvme_exit);