drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44
  45 static int nvme_major;
  46 module_param(nvme_major, int, 0);
  47
  48 static int use_threaded_interrupts;
  49 module_param(use_threaded_interrupts, int, 0);
  50
  51 /*
  52  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  53  */
  54 struct nvme_dev {
  55         struct nvme_queue **queues;
  56         u32 __iomem *dbs;
  57         struct pci_dev *pci_dev;
  58         int instance;
  59         int queue_count;
  60         u32 ctrl_config;
  61         struct msix_entry *entry;
  62         struct nvme_bar __iomem *bar;
  63         struct list_head namespaces;
  64         char serial[20];
  65         char model[40];
  66         char firmware_rev[8];
  67 };
  68
  69 /*
  70  * An NVM Express namespace is equivalent to a SCSI LUN
  71  */
  72 struct nvme_ns {
  73         struct list_head list;
  74
  75         struct nvme_dev *dev;
  76         struct request_queue *queue;
  77         struct gendisk *disk;
  78
  79         int ns_id;
  80         int lba_shift;
  81 };
  82
  83 /*
  84  * An NVM Express queue.  Each device has at least two (one for admin
  85  * commands and one for I/O commands).
  86  */
  87 struct nvme_queue {
  88         struct device *q_dmadev;
  89         spinlock_t q_lock;
  90         struct nvme_command *sq_cmds;
  91         volatile struct nvme_completion *cqes;
  92         dma_addr_t sq_dma_addr;
  93         dma_addr_t cq_dma_addr;
  94         wait_queue_head_t sq_full;
  95         struct bio_list sq_cong;
  96         u32 __iomem *q_db;
  97         u16 q_depth;
  98         u16 cq_vector;
  99         u16 sq_head;
 100         u16 sq_tail;
 101         u16 cq_head;
 102         u16 cq_phase;
 103         unsigned long cmdid_data[];
 104 };
 105
 106 /*
 107  * Check we didin't inadvertently grow the command struct
 108  */
 109 static inline void _nvme_check_size(void)
 110 {
 111         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 112         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 113         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 114         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 115         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 116         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 117         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 118         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 119         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 120 }
 121
 122 /**
 123  * alloc_cmdid - Allocate a Command ID
 124  * @param nvmeq The queue that will be used for this command
 125  * @param ctx A pointer that will be passed to the handler
 126  * @param handler The ID of the handler to call
 127  *
 128  * Allocate a Command ID for a queue.  The data passed in will
 129  * be passed to the completion handler.  This is implemented by using
 130  * the bottom two bits of the ctx pointer to store the handler ID.
 131  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 132  * We can change this if it becomes a problem.
 133  */
 134 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
 135 {
 136         int depth = nvmeq->q_depth;
 137         unsigned long data = (unsigned long)ctx | handler;
 138         int cmdid;
 139
 140         BUG_ON((unsigned long)ctx & 3);
 141
 142         do {
 143                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 144                 if (cmdid >= depth)
 145                         return -EBUSY;
 146         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 147
 148         nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
 149         return cmdid;
 150 }
 151
 152 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 153                                                                 int handler)
 154 {
 155         int cmdid;
 156         wait_event_killable(nvmeq->sq_full,
 157                         (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
 158         return (cmdid < 0) ? -EINTR : cmdid;
 159 }
 160
 161 /* If you need more than four handlers, you'll need to change how
 162  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 163  * CMD_CTX value instead, if that works for your situation.
 164  */
 165 enum {
 166         sync_completion_id = 0,
 167         bio_completion_id,
 168 };
 169
 170 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 171 #define CMD_CTX_CANCELLED       (0x2008 + CMD_CTX_BASE)
 172 #define CMD_CTX_COMPLETED       (0x2010 + CMD_CTX_BASE)
 173
 174 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 175 {
 176         unsigned long data;
 177         unsigned offset = cmdid + BITS_TO_LONGS(nvmeq->q_depth);
 178
 179         data = nvmeq->cmdid_data[offset];
 180         nvmeq->cmdid_data[offset] = CMD_CTX_COMPLETED;
 181         clear_bit(cmdid, nvmeq->cmdid_data);
 182         wake_up(&nvmeq->sq_full);
 183         return data;
 184 }
 185
 186 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 187 {
 188         unsigned offset = cmdid + BITS_TO_LONGS(nvmeq->q_depth);
 189         nvmeq->cmdid_data[offset] = CMD_CTX_CANCELLED;
 190 }
 191
 192 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 193 {
 194         int qid, cpu = get_cpu();
 195         if (cpu < ns->dev->queue_count)
 196                 qid = cpu + 1;
 197         else
 198                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 199         return ns->dev->queues[qid];
 200 }
 201
 202 static void put_nvmeq(struct nvme_queue *nvmeq)
 203 {
 204         put_cpu();
 205 }
 206
 207 /**
 208  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 209  * @nvmeq: The queue to use
 210  * @cmd: The command to send
 211  *
 212  * Safe to use from interrupt context
 213  */
 214 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 215 {
 216         unsigned long flags;
 217         u16 tail;
 218         /* XXX: Need to check tail isn't going to overrun head */
 219         spin_lock_irqsave(&nvmeq->q_lock, flags);
 220         tail = nvmeq->sq_tail;
 221         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 222         writel(tail, nvmeq->q_db);
 223         if (++tail == nvmeq->q_depth)
 224                 tail = 0;
 225         nvmeq->sq_tail = tail;
 226         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 struct nvme_req_info {
 232         struct bio *bio;
 233         int nents;
 234         struct scatterlist sg[0];
 235 };
 236
 237 /* XXX: use a mempool */
 238 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 239 {
 240         return kmalloc(sizeof(struct nvme_req_info) +
 241                         sizeof(struct scatterlist) * nseg, gfp);
 242 }
 243
 244 static void free_info(struct nvme_req_info *info)
 245 {
 246         kfree(info);
 247 }
 248
 249 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 250                                                 struct nvme_completion *cqe)
 251 {
 252         struct nvme_req_info *info = ctx;
 253         struct bio *bio = info->bio;
 254         u16 status = le16_to_cpup(&cqe->status) >> 1;
 255
 256         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 257                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 258         free_info(info);
 259         bio_endio(bio, status ? -EIO : 0);
 260 }
 261
 262 /* length is in bytes */
 263 static void nvme_setup_prps(struct nvme_common_command *cmd,
 264                                         struct scatterlist *sg, int length)
 265 {
 266         int dma_len = sg_dma_len(sg);
 267         u64 dma_addr = sg_dma_address(sg);
 268         int offset = offset_in_page(dma_addr);
 269
 270         cmd->prp1 = cpu_to_le64(dma_addr);
 271         length -= (PAGE_SIZE - offset);
 272         if (length <= 0)
 273                 return;
 274
 275         dma_len -= (PAGE_SIZE - offset);
 276         if (dma_len) {
 277                 dma_addr += (PAGE_SIZE - offset);
 278         } else {
 279                 sg = sg_next(sg);
 280                 dma_addr = sg_dma_address(sg);
 281                 dma_len = sg_dma_len(sg);
 282         }
 283
 284         if (length <= PAGE_SIZE) {
 285                 cmd->prp2 = cpu_to_le64(dma_addr);
 286                 return;
 287         }
 288
 289         /* XXX: support PRP lists */
 290 }
 291
 292 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 293                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 294 {
 295         struct bio_vec *bvec;
 296         struct scatterlist *sg = info->sg;
 297         int i, nsegs;
 298
 299         sg_init_table(sg, psegs);
 300         bio_for_each_segment(bvec, bio, i) {
 301                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 302                 /* XXX: handle non-mergable here */
 303                 nsegs++;
 304         }
 305         info->nents = nsegs;
 306
 307         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 308 }
 309
 310 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 311                                                                 struct bio *bio)
 312 {
 313         struct nvme_command *cmnd;
 314         struct nvme_req_info *info;
 315         enum dma_data_direction dma_dir;
 316         int cmdid;
 317         u16 control;
 318         u32 dsmgmt;
 319         unsigned long flags;
 320         int psegs = bio_phys_segments(ns->queue, bio);
 321
 322         info = alloc_info(psegs, GFP_NOIO);
 323         if (!info)
 324                 goto congestion;
 325         info->bio = bio;
 326
 327         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
 328         if (unlikely(cmdid < 0))
 329                 goto free_info;
 330
 331         control = 0;
 332         if (bio->bi_rw & REQ_FUA)
 333                 control |= NVME_RW_FUA;
 334         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 335                 control |= NVME_RW_LR;
 336
 337         dsmgmt = 0;
 338         if (bio->bi_rw & REQ_RAHEAD)
 339                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 340
 341         spin_lock_irqsave(&nvmeq->q_lock, flags);
 342         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 343
 344         memset(cmnd, 0, sizeof(*cmnd));
 345         if (bio_data_dir(bio)) {
 346                 cmnd->rw.opcode = nvme_cmd_write;
 347                 dma_dir = DMA_TO_DEVICE;
 348         } else {
 349                 cmnd->rw.opcode = nvme_cmd_read;
 350                 dma_dir = DMA_FROM_DEVICE;
 351         }
 352
 353         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 354
 355         cmnd->rw.flags = 1;
 356         cmnd->rw.command_id = cmdid;
 357         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 358         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 359         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 360         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 361         cmnd->rw.control = cpu_to_le16(control);
 362         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 363
 364         writel(nvmeq->sq_tail, nvmeq->q_db);
 365         if (++nvmeq->sq_tail == nvmeq->q_depth)
 366                 nvmeq->sq_tail = 0;
 367
 368         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 369
 370         return 0;
 371
 372  free_info:
 373         free_info(info);
 374  congestion:
 375         return -EBUSY;
 376 }
 377
 378 /*
 379  * NB: return value of non-zero would mean that we were a stacking driver.
 380  * make_request must always succeed.
 381  */
 382 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 383 {
 384         struct nvme_ns *ns = q->queuedata;
 385         struct nvme_queue *nvmeq = get_nvmeq(ns);
 386
 387         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 388                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 389                 bio_list_add(&nvmeq->sq_cong, bio);
 390         }
 391         put_nvmeq(nvmeq);
 392
 393         return 0;
 394 }
 395
 396 struct sync_cmd_info {
 397         struct task_struct *task;
 398         u32 result;
 399         int status;
 400 };
 401
 402 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 403                                                 struct nvme_completion *cqe)
 404 {
 405         struct sync_cmd_info *cmdinfo = ctx;
 406         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 407                 return;
 408         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 409                 dev_warn(nvmeq->q_dmadev,
 410                                 "completed id %d twice on queue %d\n",
 411                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 412                 return;
 413         }
 414         cmdinfo->result = le32_to_cpup(&cqe->result);
 415         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 416         wake_up_process(cmdinfo->task);
 417 }
 418
 419 typedef void (*completion_fn)(struct nvme_queue *, void *,
 420                                                 struct nvme_completion *);
 421
 422 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 423 {
 424         u16 head, phase;
 425
 426         static const completion_fn completions[4] = {
 427                 [sync_completion_id] = sync_completion,
 428                 [bio_completion_id]  = bio_completion,
 429         };
 430
 431         head = nvmeq->cq_head;
 432         phase = nvmeq->cq_phase;
 433
 434         for (;;) {
 435                 unsigned long data;
 436                 void *ptr;
 437                 unsigned char handler;
 438                 struct nvme_completion cqe = nvmeq->cqes[head];
 439                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 440                         break;
 441                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 442                 if (++head == nvmeq->q_depth) {
 443                         head = 0;
 444                         phase = !phase;
 445                 }
 446
 447                 data = free_cmdid(nvmeq, cqe.command_id);
 448                 handler = data & 3;
 449                 ptr = (void *)(data & ~3UL);
 450                 completions[handler](nvmeq, ptr, &cqe);
 451         }
 452
 453         /* If the controller ignores the cq head doorbell and continuously
 454          * writes to the queue, it is theoretically possible to wrap around
 455          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 456          * requires that 0.1% of your interrupts are handled, so this isn't
 457          * a big problem.
 458          */
 459         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 460                 return IRQ_NONE;
 461
 462         writel(head, nvmeq->q_db + 1);
 463         nvmeq->cq_head = head;
 464         nvmeq->cq_phase = phase;
 465
 466         return IRQ_HANDLED;
 467 }
 468
 469 static irqreturn_t nvme_irq(int irq, void *data)
 470 {
 471         return nvme_process_cq(data);
 472 }
 473
 474 static irqreturn_t nvme_irq_thread(int irq, void *data)
 475 {
 476         irqreturn_t result;
 477         struct nvme_queue *nvmeq = data;
 478         spin_lock(&nvmeq->q_lock);
 479         result = nvme_process_cq(nvmeq);
 480         spin_unlock(&nvmeq->q_lock);
 481         return result;
 482 }
 483
 484 static irqreturn_t nvme_irq_check(int irq, void *data)
 485 {
 486         struct nvme_queue *nvmeq = data;
 487         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 488         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 489                 return IRQ_NONE;
 490         return IRQ_WAKE_THREAD;
 491 }
 492
 493 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 494 {
 495         spin_lock_irq(&nvmeq->q_lock);
 496         cancel_cmdid_data(nvmeq, cmdid);
 497         spin_unlock_irq(&nvmeq->q_lock);
 498 }
 499
 500 /*
 501  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 502  * if the result is positive, it's an NVM Express status code
 503  */
 504 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 505                                         struct nvme_command *cmd, u32 *result)
 506 {
 507         int cmdid;
 508         struct sync_cmd_info cmdinfo;
 509
 510         cmdinfo.task = current;
 511         cmdinfo.status = -EINTR;
 512
 513         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id);
 514         if (cmdid < 0)
 515                 return cmdid;
 516         cmd->common.command_id = cmdid;
 517
 518         set_current_state(TASK_KILLABLE);
 519         nvme_submit_cmd(nvmeq, cmd);
 520         schedule();
 521
 522         if (cmdinfo.status == -EINTR) {
 523                 nvme_abort_command(nvmeq, cmdid);
 524                 return -EINTR;
 525         }
 526
 527         if (result)
 528                 *result = cmdinfo.result;
 529
 530         return cmdinfo.status;
 531 }
 532
 533 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 534                                                                 u32 *result)
 535 {
 536         return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
 537 }
 538
 539 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 540 {
 541         int status;
 542         struct nvme_command c;
 543
 544         memset(&c, 0, sizeof(c));
 545         c.delete_queue.opcode = opcode;
 546         c.delete_queue.qid = cpu_to_le16(id);
 547
 548         status = nvme_submit_admin_cmd(dev, &c, NULL);
 549         if (status)
 550                 return -EIO;
 551         return 0;
 552 }
 553
 554 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 555                                                 struct nvme_queue *nvmeq)
 556 {
 557         int status;
 558         struct nvme_command c;
 559         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 560
 561         memset(&c, 0, sizeof(c));
 562         c.create_cq.opcode = nvme_admin_create_cq;
 563         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 564         c.create_cq.cqid = cpu_to_le16(qid);
 565         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 566         c.create_cq.cq_flags = cpu_to_le16(flags);
 567         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 568
 569         status = nvme_submit_admin_cmd(dev, &c, NULL);
 570         if (status)
 571                 return -EIO;
 572         return 0;
 573 }
 574
 575 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 576                                                 struct nvme_queue *nvmeq)
 577 {
 578         int status;
 579         struct nvme_command c;
 580         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 581
 582         memset(&c, 0, sizeof(c));
 583         c.create_sq.opcode = nvme_admin_create_sq;
 584         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 585         c.create_sq.sqid = cpu_to_le16(qid);
 586         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 587         c.create_sq.sq_flags = cpu_to_le16(flags);
 588         c.create_sq.cqid = cpu_to_le16(qid);
 589
 590         status = nvme_submit_admin_cmd(dev, &c, NULL);
 591         if (status)
 592                 return -EIO;
 593         return 0;
 594 }
 595
 596 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 597 {
 598         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 599 }
 600
 601 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 602 {
 603         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 604 }
 605
 606 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 607 {
 608         struct nvme_queue *nvmeq = dev->queues[qid];
 609
 610         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 611
 612         /* Don't tell the adapter to delete the admin queue */
 613         if (qid) {
 614                 adapter_delete_sq(dev, qid);
 615                 adapter_delete_cq(dev, qid);
 616         }
 617
 618         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 619                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 620         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 621                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 622         kfree(nvmeq);
 623 }
 624
 625 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 626                                                         int depth, int vector)
 627 {
 628         struct device *dmadev = &dev->pci_dev->dev;
 629         unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
 630         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 631         if (!nvmeq)
 632                 return NULL;
 633
 634         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 635                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 636         if (!nvmeq->cqes)
 637                 goto free_nvmeq;
 638         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 639
 640         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 641                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 642         if (!nvmeq->sq_cmds)
 643                 goto free_cqdma;
 644
 645         nvmeq->q_dmadev = dmadev;
 646         spin_lock_init(&nvmeq->q_lock);
 647         nvmeq->cq_head = 0;
 648         nvmeq->cq_phase = 1;
 649         init_waitqueue_head(&nvmeq->sq_full);
 650         bio_list_init(&nvmeq->sq_cong);
 651         nvmeq->q_db = &dev->dbs[qid * 2];
 652         nvmeq->q_depth = depth;
 653         nvmeq->cq_vector = vector;
 654
 655         return nvmeq;
 656
 657  free_cqdma:
 658         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 659                                                         nvmeq->cq_dma_addr);
 660  free_nvmeq:
 661         kfree(nvmeq);
 662         return NULL;
 663 }
 664
 665 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 666                                                         const char *name)
 667 {
 668         if (use_threaded_interrupts)
 669                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 670                                         nvme_irq_check, nvme_irq_thread,
 671                                         IRQF_DISABLED | IRQF_SHARED,
 672                                         name, nvmeq);
 673         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 674                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 675 }
 676
 677 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 678                                         int qid, int cq_size, int vector)
 679 {
 680         int result;
 681         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 682
 683         if (!nvmeq)
 684                 return NULL;
 685
 686         result = adapter_alloc_cq(dev, qid, nvmeq);
 687         if (result < 0)
 688                 goto free_nvmeq;
 689
 690         result = adapter_alloc_sq(dev, qid, nvmeq);
 691         if (result < 0)
 692                 goto release_cq;
 693
 694         result = queue_request_irq(dev, nvmeq, "nvme");
 695         if (result < 0)
 696                 goto release_sq;
 697
 698         return nvmeq;
 699
 700  release_sq:
 701         adapter_delete_sq(dev, qid);
 702  release_cq:
 703         adapter_delete_cq(dev, qid);
 704  free_nvmeq:
 705         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 706                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 707         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 708                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 709         kfree(nvmeq);
 710         return NULL;
 711 }
 712
 713 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 714 {
 715         int result;
 716         u32 aqa;
 717         struct nvme_queue *nvmeq;
 718
 719         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 720
 721         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 722         if (!nvmeq)
 723                 return -ENOMEM;
 724
 725         aqa = nvmeq->q_depth - 1;
 726         aqa |= aqa << 16;
 727
 728         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 729         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 730         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 731
 732         writel(0, &dev->bar->cc);
 733         writel(aqa, &dev->bar->aqa);
 734         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 735         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 736         writel(dev->ctrl_config, &dev->bar->cc);
 737
 738         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 739                 msleep(100);
 740                 if (fatal_signal_pending(current))
 741                         return -EINTR;
 742         }
 743
 744         result = queue_request_irq(dev, nvmeq, "nvme admin");
 745         dev->queues[0] = nvmeq;
 746         return result;
 747 }
 748
 749 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 750                                 unsigned long addr, unsigned length,
 751                                 struct scatterlist **sgp)
 752 {
 753         int i, err, count, nents, offset;
 754         struct scatterlist *sg;
 755         struct page **pages;
 756
 757         if (addr & 3)
 758                 return -EINVAL;
 759         if (!length)
 760                 return -EINVAL;
 761
 762         offset = offset_in_page(addr);
 763         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 764         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 765
 766         err = get_user_pages_fast(addr, count, 1, pages);
 767         if (err < count) {
 768                 count = err;
 769                 err = -EFAULT;
 770                 goto put_pages;
 771         }
 772
 773         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 774         sg_init_table(sg, count);
 775         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 776         length -= (PAGE_SIZE - offset);
 777         for (i = 1; i < count; i++) {
 778                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 779                 length -= PAGE_SIZE;
 780         }
 781
 782         err = -ENOMEM;
 783         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 784                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 785         if (!nents)
 786                 goto put_pages;
 787
 788         kfree(pages);
 789         *sgp = sg;
 790         return nents;
 791
 792  put_pages:
 793         for (i = 0; i < count; i++)
 794                 put_page(pages[i]);
 795         kfree(pages);
 796         return err;
 797 }
 798
 799 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 800                                 unsigned long addr, int length,
 801                                 struct scatterlist *sg, int nents)
 802 {
 803         int i, count;
 804
 805         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 806         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 807
 808         for (i = 0; i < count; i++)
 809                 put_page(sg_page(&sg[i]));
 810 }
 811
 812 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 813                                         unsigned long addr, unsigned length,
 814                                         struct nvme_command *cmd)
 815 {
 816         int err, nents;
 817         struct scatterlist *sg;
 818
 819         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 820         if (nents < 0)
 821                 return nents;
 822         nvme_setup_prps(&cmd->common, sg, length);
 823         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 824         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 825         return err ? -EIO : 0;
 826 }
 827
 828 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 829 {
 830         struct nvme_command c;
 831
 832         memset(&c, 0, sizeof(c));
 833         c.identify.opcode = nvme_admin_identify;
 834         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 835         c.identify.cns = cpu_to_le32(cns);
 836
 837         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 838 }
 839
 840 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 841 {
 842         struct nvme_command c;
 843
 844         memset(&c, 0, sizeof(c));
 845         c.features.opcode = nvme_admin_get_features;
 846         c.features.nsid = cpu_to_le32(ns->ns_id);
 847         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 848
 849         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 850 }
 851
 852 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 853 {
 854         struct nvme_dev *dev = ns->dev;
 855         struct nvme_queue *nvmeq;
 856         struct nvme_user_io io;
 857         struct nvme_command c;
 858         unsigned length;
 859         u32 result;
 860         int nents, status;
 861         struct scatterlist *sg;
 862
 863         if (copy_from_user(&io, uio, sizeof(io)))
 864                 return -EFAULT;
 865         length = io.nblocks << io.block_shift;
 866         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 867         if (nents < 0)
 868                 return nents;
 869
 870         memset(&c, 0, sizeof(c));
 871         c.rw.opcode = io.opcode;
 872         c.rw.flags = io.flags;
 873         c.rw.nsid = cpu_to_le32(io.nsid);
 874         c.rw.slba = cpu_to_le64(io.slba);
 875         c.rw.length = cpu_to_le16(io.nblocks - 1);
 876         c.rw.control = cpu_to_le16(io.control);
 877         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 878         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 879         c.rw.apptag = cpu_to_le16(io.apptag);
 880         c.rw.appmask = cpu_to_le16(io.appmask);
 881         /* XXX: metadata */
 882         nvme_setup_prps(&c.common, sg, length);
 883
 884         nvmeq = get_nvmeq(ns);
 885         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
 886          * disabled.  We may be preempted at any point, and be rescheduled
 887          * to a different CPU.  That will cause cacheline bouncing, but no
 888          * additional races since q_lock already protects against other CPUs.
 889          */
 890         put_nvmeq(nvmeq);
 891         status = nvme_submit_sync_cmd(nvmeq, &c, &result);
 892
 893         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
 894         put_user(result, &uio->result);
 895         return status;
 896 }
 897
 898 static int nvme_download_firmware(struct nvme_ns *ns,
 899                                                 struct nvme_dlfw __user *udlfw)
 900 {
 901         struct nvme_dev *dev = ns->dev;
 902         struct nvme_dlfw dlfw;
 903         struct nvme_command c;
 904         int nents, status;
 905         struct scatterlist *sg;
 906
 907         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
 908                 return -EFAULT;
 909         if (dlfw.length >= (1 << 30))
 910                 return -EINVAL;
 911
 912         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
 913         if (nents < 0)
 914                 return nents;
 915
 916         memset(&c, 0, sizeof(c));
 917         c.dlfw.opcode = nvme_admin_download_fw;
 918         c.dlfw.numd = cpu_to_le32(dlfw.length);
 919         c.dlfw.offset = cpu_to_le32(dlfw.offset);
 920         nvme_setup_prps(&c.common, sg, dlfw.length * 4);
 921
 922         status = nvme_submit_admin_cmd(dev, &c, NULL);
 923         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
 924         return status;
 925 }
 926
 927 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
 928 {
 929         struct nvme_dev *dev = ns->dev;
 930         struct nvme_command c;
 931
 932         memset(&c, 0, sizeof(c));
 933         c.common.opcode = nvme_admin_activate_fw;
 934         c.common.rsvd10[0] = cpu_to_le32(arg);
 935
 936         return nvme_submit_admin_cmd(dev, &c, NULL);
 937 }
 938
 939 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 940                                                         unsigned long arg)
 941 {
 942         struct nvme_ns *ns = bdev->bd_disk->private_data;
 943
 944         switch (cmd) {
 945         case NVME_IOCTL_IDENTIFY_NS:
 946                 return nvme_identify(ns, arg, 0);
 947         case NVME_IOCTL_IDENTIFY_CTRL:
 948                 return nvme_identify(ns, arg, 1);
 949         case NVME_IOCTL_GET_RANGE_TYPE:
 950                 return nvme_get_range_type(ns, arg);
 951         case NVME_IOCTL_SUBMIT_IO:
 952                 return nvme_submit_io(ns, (void __user *)arg);
 953         case NVME_IOCTL_DOWNLOAD_FW:
 954                 return nvme_download_firmware(ns, (void __user *)arg);
 955         case NVME_IOCTL_ACTIVATE_FW:
 956                 return nvme_activate_firmware(ns, arg);
 957         default:
 958                 return -ENOTTY;
 959         }
 960 }
 961
 962 static const struct block_device_operations nvme_fops = {
 963         .owner          = THIS_MODULE,
 964         .ioctl          = nvme_ioctl,
 965 };
 966
 967 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
 968                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
 969 {
 970         struct nvme_ns *ns;
 971         struct gendisk *disk;
 972         int lbaf;
 973
 974         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
 975                 return NULL;
 976
 977         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
 978         if (!ns)
 979                 return NULL;
 980         ns->queue = blk_alloc_queue(GFP_KERNEL);
 981         if (!ns->queue)
 982                 goto out_free_ns;
 983         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
 984                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
 985         blk_queue_make_request(ns->queue, nvme_make_request);
 986         ns->dev = dev;
 987         ns->queue->queuedata = ns;
 988
 989         disk = alloc_disk(NVME_MINORS);
 990         if (!disk)
 991                 goto out_free_queue;
 992         ns->ns_id = index;
 993         ns->disk = disk;
 994         lbaf = id->flbas & 0xf;
 995         ns->lba_shift = id->lbaf[lbaf].ds;
 996
 997         disk->major = nvme_major;
 998         disk->minors = NVME_MINORS;
 999         disk->first_minor = NVME_MINORS * index;
1000         disk->fops = &nvme_fops;
1001         disk->private_data = ns;
1002         disk->queue = ns->queue;
1003         disk->driverfs_dev = &dev->pci_dev->dev;
1004         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1005         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1006
1007         return ns;
1008
1009  out_free_queue:
1010         blk_cleanup_queue(ns->queue);
1011  out_free_ns:
1012         kfree(ns);
1013         return NULL;
1014 }
1015
1016 static void nvme_ns_free(struct nvme_ns *ns)
1017 {
1018         put_disk(ns->disk);
1019         blk_cleanup_queue(ns->queue);
1020         kfree(ns);
1021 }
1022
1023 static int set_queue_count(struct nvme_dev *dev, int count)
1024 {
1025         int status;
1026         u32 result;
1027         struct nvme_command c;
1028         u32 q_count = (count - 1) | ((count - 1) << 16);
1029
1030         memset(&c, 0, sizeof(c));
1031         c.features.opcode = nvme_admin_get_features;
1032         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1033         c.features.dword11 = cpu_to_le32(q_count);
1034
1035         status = nvme_submit_admin_cmd(dev, &c, &result);
1036         if (status)
1037                 return -EIO;
1038         return min(result & 0xffff, result >> 16) + 1;
1039 }
1040
1041 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1042 {
1043         int result, cpu, i, nr_queues;
1044
1045         nr_queues = num_online_cpus();
1046         result = set_queue_count(dev, nr_queues);
1047         if (result < 0)
1048                 return result;
1049         if (result < nr_queues)
1050                 nr_queues = result;
1051
1052         /* Deregister the admin queue's interrupt */
1053         free_irq(dev->entry[0].vector, dev->queues[0]);
1054
1055         for (i = 0; i < nr_queues; i++)
1056                 dev->entry[i].entry = i;
1057         for (;;) {
1058                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1059                 if (result == 0) {
1060                         break;
1061                 } else if (result > 0) {
1062                         nr_queues = result;
1063                         continue;
1064                 } else {
1065                         nr_queues = 1;
1066                         break;
1067                 }
1068         }
1069
1070         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1071         /* XXX: handle failure here */
1072
1073         cpu = cpumask_first(cpu_online_mask);
1074         for (i = 0; i < nr_queues; i++) {
1075                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1076                 cpu = cpumask_next(cpu, cpu_online_mask);
1077         }
1078
1079         for (i = 0; i < nr_queues; i++) {
1080                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1081                                                         NVME_Q_DEPTH, i);
1082                 if (!dev->queues[i + 1])
1083                         return -ENOMEM;
1084                 dev->queue_count++;
1085         }
1086
1087         return 0;
1088 }
1089
1090 static void nvme_free_queues(struct nvme_dev *dev)
1091 {
1092         int i;
1093
1094         for (i = dev->queue_count - 1; i >= 0; i--)
1095                 nvme_free_queue(dev, i);
1096 }
1097
1098 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1099 {
1100         int res, nn, i;
1101         struct nvme_ns *ns, *next;
1102         struct nvme_id_ctrl *ctrl;
1103         void *id;
1104         dma_addr_t dma_addr;
1105         struct nvme_command cid, crt;
1106
1107         res = nvme_setup_io_queues(dev);
1108         if (res)
1109                 return res;
1110
1111         /* XXX: Switch to a SG list once prp2 works */
1112         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1113                                                                 GFP_KERNEL);
1114
1115         memset(&cid, 0, sizeof(cid));
1116         cid.identify.opcode = nvme_admin_identify;
1117         cid.identify.nsid = 0;
1118         cid.identify.prp1 = cpu_to_le64(dma_addr);
1119         cid.identify.cns = cpu_to_le32(1);
1120
1121         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1122         if (res) {
1123                 res = -EIO;
1124                 goto out_free;
1125         }
1126
1127         ctrl = id;
1128         nn = le32_to_cpup(&ctrl->nn);
1129         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1130         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1131         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1132
1133         cid.identify.cns = 0;
1134         memset(&crt, 0, sizeof(crt));
1135         crt.features.opcode = nvme_admin_get_features;
1136         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1137         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1138
1139         for (i = 0; i < nn; i++) {
1140                 cid.identify.nsid = cpu_to_le32(i);
1141                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1142                 if (res)
1143                         continue;
1144
1145                 if (((struct nvme_id_ns *)id)->ncap == 0)
1146                         continue;
1147
1148                 crt.features.nsid = cpu_to_le32(i);
1149                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1150                 if (res)
1151                         continue;
1152
1153                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1154                 if (ns)
1155                         list_add_tail(&ns->list, &dev->namespaces);
1156         }
1157         list_for_each_entry(ns, &dev->namespaces, list)
1158                 add_disk(ns->disk);
1159
1160         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1161         return 0;
1162
1163  out_free:
1164         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1165                 list_del(&ns->list);
1166                 nvme_ns_free(ns);
1167         }
1168
1169         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1170         return res;
1171 }
1172
1173 static int nvme_dev_remove(struct nvme_dev *dev)
1174 {
1175         struct nvme_ns *ns, *next;
1176
1177         /* TODO: wait all I/O finished or cancel them */
1178
1179         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1180                 list_del(&ns->list);
1181                 del_gendisk(ns->disk);
1182                 nvme_ns_free(ns);
1183         }
1184
1185         nvme_free_queues(dev);
1186
1187         return 0;
1188 }
1189
1190 /* XXX: Use an ida or something to let remove / add work correctly */
1191 static void nvme_set_instance(struct nvme_dev *dev)
1192 {
1193         static int instance;
1194         dev->instance = instance++;
1195 }
1196
1197 static void nvme_release_instance(struct nvme_dev *dev)
1198 {
1199 }
1200
1201 static int __devinit nvme_probe(struct pci_dev *pdev,
1202                                                 const struct pci_device_id *id)
1203 {
1204         int bars, result = -ENOMEM;
1205         struct nvme_dev *dev;
1206
1207         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1208         if (!dev)
1209                 return -ENOMEM;
1210         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1211                                                                 GFP_KERNEL);
1212         if (!dev->entry)
1213                 goto free;
1214         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1215                                                                 GFP_KERNEL);
1216         if (!dev->queues)
1217                 goto free;
1218
1219         if (pci_enable_device_mem(pdev))
1220                 goto free;
1221         pci_set_master(pdev);
1222         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1223         if (pci_request_selected_regions(pdev, bars, "nvme"))
1224                 goto disable;
1225
1226         INIT_LIST_HEAD(&dev->namespaces);
1227         dev->pci_dev = pdev;
1228         pci_set_drvdata(pdev, dev);
1229         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1230         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1231         nvme_set_instance(dev);
1232         dev->entry[0].vector = pdev->irq;
1233
1234         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1235         if (!dev->bar) {
1236                 result = -ENOMEM;
1237                 goto disable_msix;
1238         }
1239
1240         result = nvme_configure_admin_queue(dev);
1241         if (result)
1242                 goto unmap;
1243         dev->queue_count++;
1244
1245         result = nvme_dev_add(dev);
1246         if (result)
1247                 goto delete;
1248         return 0;
1249
1250  delete:
1251         nvme_free_queues(dev);
1252  unmap:
1253         iounmap(dev->bar);
1254  disable_msix:
1255         pci_disable_msix(pdev);
1256         nvme_release_instance(dev);
1257  disable:
1258         pci_disable_device(pdev);
1259         pci_release_regions(pdev);
1260  free:
1261         kfree(dev->queues);
1262         kfree(dev->entry);
1263         kfree(dev);
1264         return result;
1265 }
1266
1267 static void __devexit nvme_remove(struct pci_dev *pdev)
1268 {
1269         struct nvme_dev *dev = pci_get_drvdata(pdev);
1270         nvme_dev_remove(dev);
1271         pci_disable_msix(pdev);
1272         iounmap(dev->bar);
1273         nvme_release_instance(dev);
1274         pci_disable_device(pdev);
1275         pci_release_regions(pdev);
1276         kfree(dev->queues);
1277         kfree(dev->entry);
1278         kfree(dev);
1279 }
1280
1281 /* These functions are yet to be implemented */
1282 #define nvme_error_detected NULL
1283 #define nvme_dump_registers NULL
1284 #define nvme_link_reset NULL
1285 #define nvme_slot_reset NULL
1286 #define nvme_error_resume NULL
1287 #define nvme_suspend NULL
1288 #define nvme_resume NULL
1289
1290 static struct pci_error_handlers nvme_err_handler = {
1291         .error_detected = nvme_error_detected,
1292         .mmio_enabled   = nvme_dump_registers,
1293         .link_reset     = nvme_link_reset,
1294         .slot_reset     = nvme_slot_reset,
1295         .resume         = nvme_error_resume,
1296 };
1297
1298 /* Move to pci_ids.h later */
1299 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1300
1301 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1302         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1303         { 0, }
1304 };
1305 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1306
1307 static struct pci_driver nvme_driver = {
1308         .name           = "nvme",
1309         .id_table       = nvme_id_table,
1310         .probe          = nvme_probe,
1311         .remove         = __devexit_p(nvme_remove),
1312         .suspend        = nvme_suspend,
1313         .resume         = nvme_resume,
1314         .err_handler    = &nvme_err_handler,
1315 };
1316
1317 static int __init nvme_init(void)
1318 {
1319         int result;
1320
1321         nvme_major = register_blkdev(nvme_major, "nvme");
1322         if (nvme_major <= 0)
1323                 return -EBUSY;
1324
1325         result = pci_register_driver(&nvme_driver);
1326         if (!result)
1327                 return 0;
1328
1329         unregister_blkdev(nvme_major, "nvme");
1330         return result;
1331 }
1332
1333 static void __exit nvme_exit(void)
1334 {
1335         pci_unregister_driver(&nvme_driver);
1336         unregister_blkdev(nvme_major, "nvme");
1337 }
1338
1339 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1340 MODULE_LICENSE("GPL");
1341 MODULE_VERSION("0.2");
1342 module_init(nvme_init);
1343 module_exit(nvme_exit);