2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/pci.h>
34 #include <linux/poison.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/types.h>
38 #include <linux/version.h>
40 #define NVME_Q_DEPTH 1024
41 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
42 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 #define NVME_MINORS 64
44 #define IO_TIMEOUT (5 * HZ)
45 #define ADMIN_TIMEOUT (60 * HZ)
47 static int nvme_major;
48 module_param(nvme_major, int, 0);
50 static int use_threaded_interrupts;
51 module_param(use_threaded_interrupts, int, 0);
54 * Represents an NVM Express device. Each nvme_dev is a PCI function.
57 struct nvme_queue **queues;
59 struct pci_dev *pci_dev;
63 struct msix_entry *entry;
64 struct nvme_bar __iomem *bar;
65 struct list_head namespaces;
72 * An NVM Express namespace is equivalent to a SCSI LUN
75 struct list_head list;
78 struct request_queue *queue;
86 * An NVM Express queue. Each device has at least two (one for admin
87 * commands and one for I/O commands).
90 struct device *q_dmadev;
92 struct nvme_command *sq_cmds;
93 volatile struct nvme_completion *cqes;
94 dma_addr_t sq_dma_addr;
95 dma_addr_t cq_dma_addr;
96 wait_queue_head_t sq_full;
97 struct bio_list sq_cong;
105 unsigned long cmdid_data[];
109 * Check we didin't inadvertently grow the command struct
111 static inline void _nvme_check_size(void)
113 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
114 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
115 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
116 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
117 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
120 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
121 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
124 struct nvme_cmd_info {
126 unsigned long timeout;
129 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
131 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
135 * alloc_cmdid - Allocate a Command ID
136 * @param nvmeq The queue that will be used for this command
137 * @param ctx A pointer that will be passed to the handler
138 * @param handler The ID of the handler to call
140 * Allocate a Command ID for a queue. The data passed in will
141 * be passed to the completion handler. This is implemented by using
142 * the bottom two bits of the ctx pointer to store the handler ID.
143 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
144 * We can change this if it becomes a problem.
146 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
149 int depth = nvmeq->q_depth;
150 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
153 BUG_ON((unsigned long)ctx & 3);
156 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
159 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
161 info[cmdid].ctx = (unsigned long)ctx | handler;
162 info[cmdid].timeout = jiffies + timeout;
166 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
167 int handler, unsigned timeout)
170 wait_event_killable(nvmeq->sq_full,
171 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
172 return (cmdid < 0) ? -EINTR : cmdid;
175 /* If you need more than four handlers, you'll need to change how
176 * alloc_cmdid and nvme_process_cq work. Consider using a special
177 * CMD_CTX value instead, if that works for your situation.
180 sync_completion_id = 0,
184 #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id)
185 #define CMD_CTX_CANCELLED (0x2008 + CMD_CTX_BASE)
186 #define CMD_CTX_COMPLETED (0x2010 + CMD_CTX_BASE)
187 #define CMD_CTX_INVALID (0x2014 + CMD_CTX_BASE)
189 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
192 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
194 if (cmdid >= nvmeq->q_depth)
195 return CMD_CTX_INVALID;
196 data = info[cmdid].ctx;
197 info[cmdid].ctx = CMD_CTX_COMPLETED;
198 clear_bit(cmdid, nvmeq->cmdid_data);
199 wake_up(&nvmeq->sq_full);
203 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
205 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
206 info[cmdid].ctx = CMD_CTX_CANCELLED;
209 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
211 int qid, cpu = get_cpu();
212 if (cpu < ns->dev->queue_count)
215 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
216 return ns->dev->queues[qid];
219 static void put_nvmeq(struct nvme_queue *nvmeq)
225 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
226 * @nvmeq: The queue to use
227 * @cmd: The command to send
229 * Safe to use from interrupt context
231 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
235 /* XXX: Need to check tail isn't going to overrun head */
236 spin_lock_irqsave(&nvmeq->q_lock, flags);
237 tail = nvmeq->sq_tail;
238 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
239 writel(tail, nvmeq->q_db);
240 if (++tail == nvmeq->q_depth)
242 nvmeq->sq_tail = tail;
243 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
248 struct nvme_req_info {
251 struct scatterlist sg[0];
254 /* XXX: use a mempool */
255 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
257 return kmalloc(sizeof(struct nvme_req_info) +
258 sizeof(struct scatterlist) * nseg, gfp);
261 static void free_info(struct nvme_req_info *info)
266 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
267 struct nvme_completion *cqe)
269 struct nvme_req_info *info = ctx;
270 struct bio *bio = info->bio;
271 u16 status = le16_to_cpup(&cqe->status) >> 1;
273 dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
274 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
276 bio_endio(bio, status ? -EIO : 0);
279 /* length is in bytes */
280 static void nvme_setup_prps(struct nvme_common_command *cmd,
281 struct scatterlist *sg, int length)
283 int dma_len = sg_dma_len(sg);
284 u64 dma_addr = sg_dma_address(sg);
285 int offset = offset_in_page(dma_addr);
287 cmd->prp1 = cpu_to_le64(dma_addr);
288 length -= (PAGE_SIZE - offset);
292 dma_len -= (PAGE_SIZE - offset);
294 dma_addr += (PAGE_SIZE - offset);
297 dma_addr = sg_dma_address(sg);
298 dma_len = sg_dma_len(sg);
301 if (length <= PAGE_SIZE) {
302 cmd->prp2 = cpu_to_le64(dma_addr);
306 /* XXX: support PRP lists */
309 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
310 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
312 struct bio_vec *bvec;
313 struct scatterlist *sg = info->sg;
316 sg_init_table(sg, psegs);
317 bio_for_each_segment(bvec, bio, i) {
318 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
319 /* XXX: handle non-mergable here */
324 return dma_map_sg(dev, info->sg, info->nents, dma_dir);
327 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
330 struct nvme_command *cmnd;
331 struct nvme_req_info *info;
332 enum dma_data_direction dma_dir;
337 int psegs = bio_phys_segments(ns->queue, bio);
339 info = alloc_info(psegs, GFP_NOIO);
344 cmdid = alloc_cmdid(nvmeq, info, bio_completion_id, IO_TIMEOUT);
345 if (unlikely(cmdid < 0))
349 if (bio->bi_rw & REQ_FUA)
350 control |= NVME_RW_FUA;
351 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
352 control |= NVME_RW_LR;
355 if (bio->bi_rw & REQ_RAHEAD)
356 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
358 spin_lock_irqsave(&nvmeq->q_lock, flags);
359 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
361 memset(cmnd, 0, sizeof(*cmnd));
362 if (bio_data_dir(bio)) {
363 cmnd->rw.opcode = nvme_cmd_write;
364 dma_dir = DMA_TO_DEVICE;
366 cmnd->rw.opcode = nvme_cmd_read;
367 dma_dir = DMA_FROM_DEVICE;
370 nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
373 cmnd->rw.command_id = cmdid;
374 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
375 nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
376 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
377 cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
378 cmnd->rw.control = cpu_to_le16(control);
379 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
381 writel(nvmeq->sq_tail, nvmeq->q_db);
382 if (++nvmeq->sq_tail == nvmeq->q_depth)
385 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
396 * NB: return value of non-zero would mean that we were a stacking driver.
397 * make_request must always succeed.
399 static int nvme_make_request(struct request_queue *q, struct bio *bio)
401 struct nvme_ns *ns = q->queuedata;
402 struct nvme_queue *nvmeq = get_nvmeq(ns);
404 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
405 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
406 bio_list_add(&nvmeq->sq_cong, bio);
413 struct sync_cmd_info {
414 struct task_struct *task;
419 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
420 struct nvme_completion *cqe)
422 struct sync_cmd_info *cmdinfo = ctx;
423 if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
425 if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
426 dev_warn(nvmeq->q_dmadev,
427 "completed id %d twice on queue %d\n",
428 cqe->command_id, le16_to_cpup(&cqe->sq_id));
431 if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
432 dev_warn(nvmeq->q_dmadev,
433 "invalid id %d completed on queue %d\n",
434 cqe->command_id, le16_to_cpup(&cqe->sq_id));
437 cmdinfo->result = le32_to_cpup(&cqe->result);
438 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
439 wake_up_process(cmdinfo->task);
442 typedef void (*completion_fn)(struct nvme_queue *, void *,
443 struct nvme_completion *);
445 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
449 static const completion_fn completions[4] = {
450 [sync_completion_id] = sync_completion,
451 [bio_completion_id] = bio_completion,
454 head = nvmeq->cq_head;
455 phase = nvmeq->cq_phase;
460 unsigned char handler;
461 struct nvme_completion cqe = nvmeq->cqes[head];
462 if ((le16_to_cpu(cqe.status) & 1) != phase)
464 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
465 if (++head == nvmeq->q_depth) {
470 data = free_cmdid(nvmeq, cqe.command_id);
472 ptr = (void *)(data & ~3UL);
473 completions[handler](nvmeq, ptr, &cqe);
476 /* If the controller ignores the cq head doorbell and continuously
477 * writes to the queue, it is theoretically possible to wrap around
478 * the queue twice and mistakenly return IRQ_NONE. Linux only
479 * requires that 0.1% of your interrupts are handled, so this isn't
482 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
485 writel(head, nvmeq->q_db + 1);
486 nvmeq->cq_head = head;
487 nvmeq->cq_phase = phase;
492 static irqreturn_t nvme_irq(int irq, void *data)
495 struct nvme_queue *nvmeq = data;
496 spin_lock(&nvmeq->q_lock);
497 result = nvme_process_cq(nvmeq);
498 spin_unlock(&nvmeq->q_lock);
502 static irqreturn_t nvme_irq_check(int irq, void *data)
504 struct nvme_queue *nvmeq = data;
505 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
506 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
508 return IRQ_WAKE_THREAD;
511 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
513 spin_lock_irq(&nvmeq->q_lock);
514 cancel_cmdid_data(nvmeq, cmdid);
515 spin_unlock_irq(&nvmeq->q_lock);
519 * Returns 0 on success. If the result is negative, it's a Linux error code;
520 * if the result is positive, it's an NVM Express status code
522 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
523 struct nvme_command *cmd, u32 *result, unsigned timeout)
526 struct sync_cmd_info cmdinfo;
528 cmdinfo.task = current;
529 cmdinfo.status = -EINTR;
531 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
535 cmd->common.command_id = cmdid;
537 set_current_state(TASK_KILLABLE);
538 nvme_submit_cmd(nvmeq, cmd);
541 if (cmdinfo.status == -EINTR) {
542 nvme_abort_command(nvmeq, cmdid);
547 *result = cmdinfo.result;
549 return cmdinfo.status;
552 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
555 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
558 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
561 struct nvme_command c;
563 memset(&c, 0, sizeof(c));
564 c.delete_queue.opcode = opcode;
565 c.delete_queue.qid = cpu_to_le16(id);
567 status = nvme_submit_admin_cmd(dev, &c, NULL);
573 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
574 struct nvme_queue *nvmeq)
577 struct nvme_command c;
578 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
580 memset(&c, 0, sizeof(c));
581 c.create_cq.opcode = nvme_admin_create_cq;
582 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
583 c.create_cq.cqid = cpu_to_le16(qid);
584 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
585 c.create_cq.cq_flags = cpu_to_le16(flags);
586 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
588 status = nvme_submit_admin_cmd(dev, &c, NULL);
594 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
595 struct nvme_queue *nvmeq)
598 struct nvme_command c;
599 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
601 memset(&c, 0, sizeof(c));
602 c.create_sq.opcode = nvme_admin_create_sq;
603 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
604 c.create_sq.sqid = cpu_to_le16(qid);
605 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
606 c.create_sq.sq_flags = cpu_to_le16(flags);
607 c.create_sq.cqid = cpu_to_le16(qid);
609 status = nvme_submit_admin_cmd(dev, &c, NULL);
615 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
617 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
620 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
622 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
625 static void nvme_free_queue(struct nvme_dev *dev, int qid)
627 struct nvme_queue *nvmeq = dev->queues[qid];
629 free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
631 /* Don't tell the adapter to delete the admin queue */
633 adapter_delete_sq(dev, qid);
634 adapter_delete_cq(dev, qid);
637 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
638 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
639 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
640 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
644 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
645 int depth, int vector)
647 struct device *dmadev = &dev->pci_dev->dev;
648 unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
649 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
653 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
654 &nvmeq->cq_dma_addr, GFP_KERNEL);
657 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
659 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
660 &nvmeq->sq_dma_addr, GFP_KERNEL);
664 nvmeq->q_dmadev = dmadev;
665 spin_lock_init(&nvmeq->q_lock);
668 init_waitqueue_head(&nvmeq->sq_full);
669 bio_list_init(&nvmeq->sq_cong);
670 nvmeq->q_db = &dev->dbs[qid * 2];
671 nvmeq->q_depth = depth;
672 nvmeq->cq_vector = vector;
677 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
684 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
687 if (use_threaded_interrupts)
688 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
689 nvme_irq_check, nvme_irq,
690 IRQF_DISABLED | IRQF_SHARED,
692 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
693 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
696 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
697 int qid, int cq_size, int vector)
700 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
705 result = adapter_alloc_cq(dev, qid, nvmeq);
709 result = adapter_alloc_sq(dev, qid, nvmeq);
713 result = queue_request_irq(dev, nvmeq, "nvme");
720 adapter_delete_sq(dev, qid);
722 adapter_delete_cq(dev, qid);
724 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
725 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
726 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
727 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
732 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
736 struct nvme_queue *nvmeq;
738 dev->dbs = ((void __iomem *)dev->bar) + 4096;
740 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
744 aqa = nvmeq->q_depth - 1;
747 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
748 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
749 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
751 writel(0, &dev->bar->cc);
752 writel(aqa, &dev->bar->aqa);
753 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
754 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
755 writel(dev->ctrl_config, &dev->bar->cc);
757 while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
759 if (fatal_signal_pending(current))
763 result = queue_request_irq(dev, nvmeq, "nvme admin");
764 dev->queues[0] = nvmeq;
768 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
769 unsigned long addr, unsigned length,
770 struct scatterlist **sgp)
772 int i, err, count, nents, offset;
773 struct scatterlist *sg;
781 offset = offset_in_page(addr);
782 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
783 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
785 err = get_user_pages_fast(addr, count, 1, pages);
792 sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
793 sg_init_table(sg, count);
794 sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
795 length -= (PAGE_SIZE - offset);
796 for (i = 1; i < count; i++) {
797 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
802 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
803 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
812 for (i = 0; i < count; i++)
818 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
819 unsigned long addr, int length,
820 struct scatterlist *sg, int nents)
824 count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
825 dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
827 for (i = 0; i < count; i++)
828 put_page(sg_page(&sg[i]));
831 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
832 unsigned long addr, unsigned length,
833 struct nvme_command *cmd)
836 struct scatterlist *sg;
838 nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
841 nvme_setup_prps(&cmd->common, sg, length);
842 err = nvme_submit_admin_cmd(dev, cmd, NULL);
843 nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
844 return err ? -EIO : 0;
847 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
849 struct nvme_command c;
851 memset(&c, 0, sizeof(c));
852 c.identify.opcode = nvme_admin_identify;
853 c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
854 c.identify.cns = cpu_to_le32(cns);
856 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
859 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
861 struct nvme_command c;
863 memset(&c, 0, sizeof(c));
864 c.features.opcode = nvme_admin_get_features;
865 c.features.nsid = cpu_to_le32(ns->ns_id);
866 c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
868 return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
871 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
873 struct nvme_dev *dev = ns->dev;
874 struct nvme_queue *nvmeq;
875 struct nvme_user_io io;
876 struct nvme_command c;
880 struct scatterlist *sg;
882 if (copy_from_user(&io, uio, sizeof(io)))
884 length = io.nblocks << io.block_shift;
885 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
889 memset(&c, 0, sizeof(c));
890 c.rw.opcode = io.opcode;
891 c.rw.flags = io.flags;
892 c.rw.nsid = cpu_to_le32(io.nsid);
893 c.rw.slba = cpu_to_le64(io.slba);
894 c.rw.length = cpu_to_le16(io.nblocks - 1);
895 c.rw.control = cpu_to_le16(io.control);
896 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
897 c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */
898 c.rw.apptag = cpu_to_le16(io.apptag);
899 c.rw.appmask = cpu_to_le16(io.appmask);
901 nvme_setup_prps(&c.common, sg, length);
903 nvmeq = get_nvmeq(ns);
904 /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
905 * disabled. We may be preempted at any point, and be rescheduled
906 * to a different CPU. That will cause cacheline bouncing, but no
907 * additional races since q_lock already protects against other CPUs.
910 status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
912 nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
913 put_user(result, &uio->result);
917 static int nvme_download_firmware(struct nvme_ns *ns,
918 struct nvme_dlfw __user *udlfw)
920 struct nvme_dev *dev = ns->dev;
921 struct nvme_dlfw dlfw;
922 struct nvme_command c;
924 struct scatterlist *sg;
926 if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
928 if (dlfw.length >= (1 << 30))
931 nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
935 memset(&c, 0, sizeof(c));
936 c.dlfw.opcode = nvme_admin_download_fw;
937 c.dlfw.numd = cpu_to_le32(dlfw.length);
938 c.dlfw.offset = cpu_to_le32(dlfw.offset);
939 nvme_setup_prps(&c.common, sg, dlfw.length * 4);
941 status = nvme_submit_admin_cmd(dev, &c, NULL);
942 nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
946 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
948 struct nvme_dev *dev = ns->dev;
949 struct nvme_command c;
951 memset(&c, 0, sizeof(c));
952 c.common.opcode = nvme_admin_activate_fw;
953 c.common.rsvd10[0] = cpu_to_le32(arg);
955 return nvme_submit_admin_cmd(dev, &c, NULL);
958 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
961 struct nvme_ns *ns = bdev->bd_disk->private_data;
964 case NVME_IOCTL_IDENTIFY_NS:
965 return nvme_identify(ns, arg, 0);
966 case NVME_IOCTL_IDENTIFY_CTRL:
967 return nvme_identify(ns, arg, 1);
968 case NVME_IOCTL_GET_RANGE_TYPE:
969 return nvme_get_range_type(ns, arg);
970 case NVME_IOCTL_SUBMIT_IO:
971 return nvme_submit_io(ns, (void __user *)arg);
972 case NVME_IOCTL_DOWNLOAD_FW:
973 return nvme_download_firmware(ns, (void __user *)arg);
974 case NVME_IOCTL_ACTIVATE_FW:
975 return nvme_activate_firmware(ns, arg);
981 static const struct block_device_operations nvme_fops = {
982 .owner = THIS_MODULE,
986 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
987 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
990 struct gendisk *disk;
993 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
996 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
999 ns->queue = blk_alloc_queue(GFP_KERNEL);
1002 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1003 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1004 blk_queue_make_request(ns->queue, nvme_make_request);
1006 ns->queue->queuedata = ns;
1008 disk = alloc_disk(NVME_MINORS);
1010 goto out_free_queue;
1013 lbaf = id->flbas & 0xf;
1014 ns->lba_shift = id->lbaf[lbaf].ds;
1016 disk->major = nvme_major;
1017 disk->minors = NVME_MINORS;
1018 disk->first_minor = NVME_MINORS * index;
1019 disk->fops = &nvme_fops;
1020 disk->private_data = ns;
1021 disk->queue = ns->queue;
1022 disk->driverfs_dev = &dev->pci_dev->dev;
1023 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1024 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1029 blk_cleanup_queue(ns->queue);
1035 static void nvme_ns_free(struct nvme_ns *ns)
1038 blk_cleanup_queue(ns->queue);
1042 static int set_queue_count(struct nvme_dev *dev, int count)
1046 struct nvme_command c;
1047 u32 q_count = (count - 1) | ((count - 1) << 16);
1049 memset(&c, 0, sizeof(c));
1050 c.features.opcode = nvme_admin_get_features;
1051 c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1052 c.features.dword11 = cpu_to_le32(q_count);
1054 status = nvme_submit_admin_cmd(dev, &c, &result);
1057 return min(result & 0xffff, result >> 16) + 1;
1060 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1062 int result, cpu, i, nr_queues;
1064 nr_queues = num_online_cpus();
1065 result = set_queue_count(dev, nr_queues);
1068 if (result < nr_queues)
1071 /* Deregister the admin queue's interrupt */
1072 free_irq(dev->entry[0].vector, dev->queues[0]);
1074 for (i = 0; i < nr_queues; i++)
1075 dev->entry[i].entry = i;
1077 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1080 } else if (result > 0) {
1089 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1090 /* XXX: handle failure here */
1092 cpu = cpumask_first(cpu_online_mask);
1093 for (i = 0; i < nr_queues; i++) {
1094 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1095 cpu = cpumask_next(cpu, cpu_online_mask);
1098 for (i = 0; i < nr_queues; i++) {
1099 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1101 if (!dev->queues[i + 1])
1109 static void nvme_free_queues(struct nvme_dev *dev)
1113 for (i = dev->queue_count - 1; i >= 0; i--)
1114 nvme_free_queue(dev, i);
1117 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1120 struct nvme_ns *ns, *next;
1121 struct nvme_id_ctrl *ctrl;
1123 dma_addr_t dma_addr;
1124 struct nvme_command cid, crt;
1126 res = nvme_setup_io_queues(dev);
1130 /* XXX: Switch to a SG list once prp2 works */
1131 id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1134 memset(&cid, 0, sizeof(cid));
1135 cid.identify.opcode = nvme_admin_identify;
1136 cid.identify.nsid = 0;
1137 cid.identify.prp1 = cpu_to_le64(dma_addr);
1138 cid.identify.cns = cpu_to_le32(1);
1140 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1147 nn = le32_to_cpup(&ctrl->nn);
1148 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1149 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1150 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1152 cid.identify.cns = 0;
1153 memset(&crt, 0, sizeof(crt));
1154 crt.features.opcode = nvme_admin_get_features;
1155 crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1156 crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1158 for (i = 0; i < nn; i++) {
1159 cid.identify.nsid = cpu_to_le32(i);
1160 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1164 if (((struct nvme_id_ns *)id)->ncap == 0)
1167 crt.features.nsid = cpu_to_le32(i);
1168 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1172 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1174 list_add_tail(&ns->list, &dev->namespaces);
1176 list_for_each_entry(ns, &dev->namespaces, list)
1179 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1183 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1184 list_del(&ns->list);
1188 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1192 static int nvme_dev_remove(struct nvme_dev *dev)
1194 struct nvme_ns *ns, *next;
1196 /* TODO: wait all I/O finished or cancel them */
1198 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1199 list_del(&ns->list);
1200 del_gendisk(ns->disk);
1204 nvme_free_queues(dev);
1209 /* XXX: Use an ida or something to let remove / add work correctly */
1210 static void nvme_set_instance(struct nvme_dev *dev)
1212 static int instance;
1213 dev->instance = instance++;
1216 static void nvme_release_instance(struct nvme_dev *dev)
1220 static int __devinit nvme_probe(struct pci_dev *pdev,
1221 const struct pci_device_id *id)
1223 int bars, result = -ENOMEM;
1224 struct nvme_dev *dev;
1226 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1229 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1233 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1238 if (pci_enable_device_mem(pdev))
1240 pci_set_master(pdev);
1241 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1242 if (pci_request_selected_regions(pdev, bars, "nvme"))
1245 INIT_LIST_HEAD(&dev->namespaces);
1246 dev->pci_dev = pdev;
1247 pci_set_drvdata(pdev, dev);
1248 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1249 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1250 nvme_set_instance(dev);
1251 dev->entry[0].vector = pdev->irq;
1253 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1259 result = nvme_configure_admin_queue(dev);
1264 result = nvme_dev_add(dev);
1270 nvme_free_queues(dev);
1274 pci_disable_msix(pdev);
1275 nvme_release_instance(dev);
1277 pci_disable_device(pdev);
1278 pci_release_regions(pdev);
1286 static void __devexit nvme_remove(struct pci_dev *pdev)
1288 struct nvme_dev *dev = pci_get_drvdata(pdev);
1289 nvme_dev_remove(dev);
1290 pci_disable_msix(pdev);
1292 nvme_release_instance(dev);
1293 pci_disable_device(pdev);
1294 pci_release_regions(pdev);
1300 /* These functions are yet to be implemented */
1301 #define nvme_error_detected NULL
1302 #define nvme_dump_registers NULL
1303 #define nvme_link_reset NULL
1304 #define nvme_slot_reset NULL
1305 #define nvme_error_resume NULL
1306 #define nvme_suspend NULL
1307 #define nvme_resume NULL
1309 static struct pci_error_handlers nvme_err_handler = {
1310 .error_detected = nvme_error_detected,
1311 .mmio_enabled = nvme_dump_registers,
1312 .link_reset = nvme_link_reset,
1313 .slot_reset = nvme_slot_reset,
1314 .resume = nvme_error_resume,
1317 /* Move to pci_ids.h later */
1318 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1320 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1321 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1324 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1326 static struct pci_driver nvme_driver = {
1328 .id_table = nvme_id_table,
1329 .probe = nvme_probe,
1330 .remove = __devexit_p(nvme_remove),
1331 .suspend = nvme_suspend,
1332 .resume = nvme_resume,
1333 .err_handler = &nvme_err_handler,
1336 static int __init nvme_init(void)
1340 nvme_major = register_blkdev(nvme_major, "nvme");
1341 if (nvme_major <= 0)
1344 result = pci_register_driver(&nvme_driver);
1348 unregister_blkdev(nvme_major, "nvme");
1352 static void __exit nvme_exit(void)
1354 pci_unregister_driver(&nvme_driver);
1355 unregister_blkdev(nvme_major, "nvme");
1358 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1359 MODULE_LICENSE("GPL");
1360 MODULE_VERSION("0.2");
1361 module_init(nvme_init);
1362 module_exit(nvme_exit);