10 config ARM_CCI400_COMMON
15 bool "ARM CCI400 PMU support"
16 depends on (ARM && CPU_V7) || ARM64
17 depends on PERF_EVENTS
18 select ARM_CCI400_COMMON
20 Support for PMU events monitoring on the ARM CCI-400 (cache coherent
21 interconnect). CCI-400 supports counting events related to the
22 connected slave/master interfaces.
24 config ARM_CCI400_PORT_CTRL
26 depends on ARM && OF && CPU_V7
27 select ARM_CCI400_COMMON
29 Low level power management driver for CCI400 cache coherent
30 interconnect for ARM platforms.
33 bool "ARM CCN driver support"
34 depends on ARM || ARM64
35 depends on PERF_EVENTS
37 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
40 config BRCMSTB_GISB_ARB
41 bool "Broadcom STB GISB bus arbiter"
42 depends on ARM || MIPS
44 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
45 arbiter. This driver provides timeout and target abort error handling
46 and internal bus master decoding.
49 bool "Freescale EIM DRIVER"
52 Driver for i.MX WEIM controller.
53 The WEIM(Wireless External Interface Module) works like a bus.
54 You can attach many different devices on it, such as NOR, onenand.
57 bool "MIPS Common Device Memory Map (CDMM) Driver"
60 Driver needed for the MIPS Common Device Memory Map bus in MIPS
61 cores. This bus is for per-CPU tightly coupled devices such as the
62 Fast Debug Channel (FDC).
64 For this to work, either your bootloader needs to enable the CDMM
65 region at an unused physical address on the boot CPU, or else your
66 platform code needs to implement mips_cdmm_phys_base() (see
73 Driver needed for the MBus configuration on Marvell EBU SoCs
74 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
76 config OMAP_INTERCONNECT
77 tristate "OMAP INTERCONNECT DRIVER"
78 depends on ARCH_OMAP2PLUS
81 Driver to enable OMAP interconnect error handling driver.
84 tristate "OMAP OCP2SCP DRIVER"
85 depends on ARCH_OMAP2PLUS
87 Driver to enable ocp2scp module which transforms ocp interface
88 protocol to scp protocol. In OMAP4, USB PHY is connected via
89 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
93 bool "Simple Power-Managed Bus Driver"
95 depends on ARCH_SHMOBILE || COMPILE_TEST
97 Driver for transparent busses that don't need a real driver, but
98 where the bus controller is part of a PM domain, or under the control
99 of a functional clock, and thus relies on runtime PM for managing
100 this PM domain and/or clock.
101 An example of such a bus controller is the Renesas Bus State
102 Controller (BSC, sometimes called "LBSC within Bus Bridge", or
103 "External Bus Interface") as found on several Renesas ARM SoCs.
105 config VEXPRESS_CONFIG
106 bool "Versatile Express configuration bus"
107 default y if ARCH_VEXPRESS
108 depends on ARM || ARM64
112 Platform configuration infrastructure for the ARM Ltd.