14 config ARM_CCI400_COMMON
19 bool "ARM CCI400 PMU support"
20 depends on (ARM && CPU_V7) || ARM64
21 depends on PERF_EVENTS
22 select ARM_CCI400_COMMON
25 Support for PMU events monitoring on the ARM CCI-400 (cache coherent
26 interconnect). CCI-400 supports counting events related to the
27 connected slave/master interfaces.
29 config ARM_CCI400_PORT_CTRL
31 depends on ARM && OF && CPU_V7
32 select ARM_CCI400_COMMON
34 Low level power management driver for CCI400 cache coherent
35 interconnect for ARM platforms.
38 bool "ARM CCN driver support"
39 depends on ARM || ARM64
40 depends on PERF_EVENTS
42 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 config BRCMSTB_GISB_ARB
46 bool "Broadcom STB GISB bus arbiter"
47 depends on ARM || MIPS
49 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
50 arbiter. This driver provides timeout and target abort error handling
51 and internal bus master decoding.
54 bool "Freescale EIM DRIVER"
57 Driver for i.MX WEIM controller.
58 The WEIM(Wireless External Interface Module) works like a bus.
59 You can attach many different devices on it, such as NOR, onenand.
62 bool "MIPS Common Device Memory Map (CDMM) Driver"
65 Driver needed for the MIPS Common Device Memory Map bus in MIPS
66 cores. This bus is for per-CPU tightly coupled devices such as the
67 Fast Debug Channel (FDC).
69 For this to work, either your bootloader needs to enable the CDMM
70 region at an unused physical address on the boot CPU, or else your
71 platform code needs to implement mips_cdmm_phys_base() (see
78 Driver needed for the MBus configuration on Marvell EBU SoCs
79 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
81 config OMAP_INTERCONNECT
82 tristate "OMAP INTERCONNECT DRIVER"
83 depends on ARCH_OMAP2PLUS
86 Driver to enable OMAP interconnect error handling driver.
89 tristate "OMAP OCP2SCP DRIVER"
90 depends on ARCH_OMAP2PLUS
92 Driver to enable ocp2scp module which transforms ocp interface
93 protocol to scp protocol. In OMAP4, USB PHY is connected via
94 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
98 bool "Simple Power-Managed Bus Driver"
100 depends on ARCH_SHMOBILE || COMPILE_TEST
102 Driver for transparent busses that don't need a real driver, but
103 where the bus controller is part of a PM domain, or under the control
104 of a functional clock, and thus relies on runtime PM for managing
105 this PM domain and/or clock.
106 An example of such a bus controller is the Renesas Bus State
107 Controller (BSC, sometimes called "LBSC within Bus Bridge", or
108 "External Bus Interface") as found on several Renesas ARM SoCs.
110 config VEXPRESS_CONFIG
111 bool "Versatile Express configuration bus"
112 default y if ARCH_VEXPRESS
113 depends on ARM || ARM64
117 Platform configuration infrastructure for the ARM Ltd.