2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window(),
39 * mvebu_mbus_add_window_remap_flags() and
40 * mvebu_mbus_del_window(). Since the (target, attribute) values
41 * differ from one SoC family to another, the API uses a 'const char
42 * *' string to identify devices, and this driver is responsible for
43 * knowing the mapping between the name of a device and its
44 * corresponding (target, attribute) in the current SoC family.
46 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
47 * see the list of CPU -> SDRAM windows and their configuration
48 * (file 'sdram') and the list of CPU -> devices windows and their
49 * configuration (file 'devices').
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 #include <linux/kernel.h>
55 #include <linux/module.h>
56 #include <linux/init.h>
57 #include <linux/mbus.h>
59 #include <linux/ioport.h>
61 #include <linux/of_address.h>
62 #include <linux/debugfs.h>
65 * DDR target is the same on all platforms.
70 * CPU Address Decode Windows registers
72 #define WIN_CTRL_OFF 0x0000
73 #define WIN_CTRL_ENABLE BIT(0)
74 #define WIN_CTRL_TGT_MASK 0xf0
75 #define WIN_CTRL_TGT_SHIFT 4
76 #define WIN_CTRL_ATTR_MASK 0xff00
77 #define WIN_CTRL_ATTR_SHIFT 8
78 #define WIN_CTRL_SIZE_MASK 0xffff0000
79 #define WIN_CTRL_SIZE_SHIFT 16
80 #define WIN_BASE_OFF 0x0004
81 #define WIN_BASE_LOW 0xffff0000
82 #define WIN_BASE_HIGH 0xf
83 #define WIN_REMAP_LO_OFF 0x0008
84 #define WIN_REMAP_LOW 0xffff0000
85 #define WIN_REMAP_HI_OFF 0x000c
87 #define ATTR_HW_COHERENCY (0x1 << 4)
89 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
90 #define DDR_BASE_CS_HIGH_MASK 0xf
91 #define DDR_BASE_CS_LOW_MASK 0xff000000
92 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
93 #define DDR_SIZE_ENABLED BIT(0)
94 #define DDR_SIZE_CS_MASK 0x1c
95 #define DDR_SIZE_CS_SHIFT 2
96 #define DDR_SIZE_MASK 0xff000000
98 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
100 struct mvebu_mbus_mapping {
108 * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
109 * allow to get the real attribute value, discarding the special bits
110 * used to select a PCI MEM region or a PCI WA region. This allows the
111 * debugfs code to reverse-match the name of a device from its
112 * target/attr values.
114 * For all devices except PCI, all bits of 'attr' must be
115 * considered. For most SoCs, only bit 3 should be ignored (it allows
116 * to select between PCI MEM and PCI I/O). On Orion5x however, there
117 * is the special bit 5 to select a PCI WA region.
119 #define MAPDEF_NOMASK 0xff
120 #define MAPDEF_PCIMASK 0xf7
121 #define MAPDEF_ORIONPCIMASK 0xd7
123 /* Macro used to define one mvebu_mbus_mapping entry */
124 #define MAPDEF(__n, __t, __a, __m) \
125 { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
127 struct mvebu_mbus_state;
129 struct mvebu_mbus_soc_data {
130 unsigned int num_wins;
131 unsigned int num_remappable_wins;
132 unsigned int (*win_cfg_offset)(const int win);
133 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
134 int (*show_cpu_target)(struct mvebu_mbus_state *s,
135 struct seq_file *seq, void *v);
136 const struct mvebu_mbus_mapping *map;
139 struct mvebu_mbus_state {
140 void __iomem *mbuswins_base;
141 void __iomem *sdramwins_base;
142 struct dentry *debugfs_root;
143 struct dentry *debugfs_sdram;
144 struct dentry *debugfs_devs;
145 struct resource pcie_mem_aperture;
146 struct resource pcie_io_aperture;
147 const struct mvebu_mbus_soc_data *soc;
151 static struct mvebu_mbus_state mbus_state;
153 static struct mbus_dram_target_info mvebu_mbus_dram_info;
154 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
156 return &mvebu_mbus_dram_info;
158 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
161 * Functions to manipulate the address decoding windows
164 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
165 int win, int *enabled, u64 *base,
166 u32 *size, u8 *target, u8 *attr,
169 void __iomem *addr = mbus->mbuswins_base +
170 mbus->soc->win_cfg_offset(win);
171 u32 basereg = readl(addr + WIN_BASE_OFF);
172 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
174 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
180 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
181 *base |= (basereg & WIN_BASE_LOW);
182 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
185 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
188 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
191 if (win < mbus->soc->num_remappable_wins) {
192 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
193 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
194 *remap = ((u64)remap_hi << 32) | remap_low;
200 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
205 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
207 writel(0, addr + WIN_BASE_OFF);
208 writel(0, addr + WIN_CTRL_OFF);
209 if (win < mbus->soc->num_remappable_wins) {
210 writel(0, addr + WIN_REMAP_LO_OFF);
211 writel(0, addr + WIN_REMAP_HI_OFF);
215 /* Checks whether the given window number is available */
216 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
219 void __iomem *addr = mbus->mbuswins_base +
220 mbus->soc->win_cfg_offset(win);
221 u32 ctrl = readl(addr + WIN_CTRL_OFF);
222 return !(ctrl & WIN_CTRL_ENABLE);
226 * Checks whether the given (base, base+size) area doesn't overlap an
229 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
230 phys_addr_t base, size_t size,
233 u64 end = (u64)base + size;
236 for (win = 0; win < mbus->soc->num_wins; win++) {
242 mvebu_mbus_read_window(mbus, win,
243 &enabled, &wbase, &wsize,
244 &wtarget, &wattr, NULL);
249 wend = wbase + wsize;
252 * Check if the current window overlaps with the
253 * proposed physical range
255 if ((u64)base < wend && end > wbase)
259 * Check if target/attribute conflicts
261 if (target == wtarget && attr == wattr)
268 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
269 phys_addr_t base, size_t size)
273 for (win = 0; win < mbus->soc->num_wins; win++) {
278 mvebu_mbus_read_window(mbus, win,
279 &enabled, &wbase, &wsize,
285 if (base == wbase && size == wsize)
292 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
293 int win, phys_addr_t base, size_t size,
294 phys_addr_t remap, u8 target,
297 void __iomem *addr = mbus->mbuswins_base +
298 mbus->soc->win_cfg_offset(win);
299 u32 ctrl, remap_addr;
301 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
302 (attr << WIN_CTRL_ATTR_SHIFT) |
303 (target << WIN_CTRL_TGT_SHIFT) |
306 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
307 writel(ctrl, addr + WIN_CTRL_OFF);
308 if (win < mbus->soc->num_remappable_wins) {
309 if (remap == MVEBU_MBUS_NO_REMAP)
313 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
314 writel(0, addr + WIN_REMAP_HI_OFF);
320 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
321 phys_addr_t base, size_t size,
322 phys_addr_t remap, u8 target,
327 if (remap == MVEBU_MBUS_NO_REMAP) {
328 for (win = mbus->soc->num_remappable_wins;
329 win < mbus->soc->num_wins; win++)
330 if (mvebu_mbus_window_is_free(mbus, win))
331 return mvebu_mbus_setup_window(mbus, win, base,
337 for (win = 0; win < mbus->soc->num_wins; win++)
338 if (mvebu_mbus_window_is_free(mbus, win))
339 return mvebu_mbus_setup_window(mbus, win, base, size,
340 remap, target, attr);
349 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
350 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
351 struct seq_file *seq, void *v)
355 for (i = 0; i < 4; i++) {
356 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
357 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
361 if (!(sizereg & DDR_SIZE_ENABLED)) {
362 seq_printf(seq, "[%d] disabled\n", i);
366 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
367 base |= basereg & DDR_BASE_CS_LOW_MASK;
368 size = (sizereg | ~DDR_SIZE_MASK);
370 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
371 i, (unsigned long long)base,
372 (unsigned long long)base + size + 1,
373 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
379 /* Special function for Dove */
380 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
381 struct seq_file *seq, void *v)
385 for (i = 0; i < 2; i++) {
386 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
391 seq_printf(seq, "[%d] disabled\n", i);
395 base = map & 0xff800000;
396 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
398 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
399 i, (unsigned long long)base,
400 (unsigned long long)base + size, i);
406 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
408 struct mvebu_mbus_state *mbus = &mbus_state;
409 return mbus->soc->show_cpu_target(mbus, seq, v);
412 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
414 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
417 static const struct file_operations mvebu_sdram_debug_fops = {
418 .open = mvebu_sdram_debug_open,
421 .release = single_release,
424 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
426 struct mvebu_mbus_state *mbus = &mbus_state;
429 for (win = 0; win < mbus->soc->num_wins; win++) {
436 mvebu_mbus_read_window(mbus, win,
437 &enabled, &wbase, &wsize,
438 &wtarget, &wattr, &wremap);
441 seq_printf(seq, "[%02d] disabled\n", win);
446 for (i = 0; mbus->soc->map[i].name; i++)
447 if (mbus->soc->map[i].target == wtarget &&
448 mbus->soc->map[i].attr ==
449 (wattr & mbus->soc->map[i].attrmask))
452 name = mbus->soc->map[i].name ?: "unknown";
454 seq_printf(seq, "[%02d] %016llx - %016llx : %s",
455 win, (unsigned long long)wbase,
456 (unsigned long long)(wbase + wsize), name);
458 if (win < mbus->soc->num_remappable_wins) {
459 seq_printf(seq, " (remap %016llx)\n",
460 (unsigned long long)wremap);
462 seq_printf(seq, "\n");
468 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
470 return single_open(file, mvebu_devs_debug_show, inode->i_private);
473 static const struct file_operations mvebu_devs_debug_fops = {
474 .open = mvebu_devs_debug_open,
477 .release = single_release,
481 * SoC-specific functions and definitions
484 static unsigned int orion_mbus_win_offset(int win)
489 static unsigned int armada_370_xp_mbus_win_offset(int win)
491 /* The register layout is a bit annoying and the below code
492 * tries to cope with it.
493 * - At offset 0x0, there are the registers for the first 8
494 * windows, with 4 registers of 32 bits per window (ctrl,
495 * base, remap low, remap high)
496 * - Then at offset 0x80, there is a hole of 0x10 bytes for
497 * the internal registers base address and internal units
498 * sync barrier register.
499 * - Then at offset 0x90, there the registers for 12
500 * windows, with only 2 registers of 32 bits per window
506 return 0x90 + ((win - 8) << 3);
509 static unsigned int mv78xx0_mbus_win_offset(int win)
514 return 0x900 + ((win - 8) << 4);
518 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
523 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
525 for (i = 0, cs = 0; i < 4; i++) {
526 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
527 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
530 * We only take care of entries for which the chip
531 * select is enabled, and that don't have high base
532 * address bits set (devices can only access the first
533 * 32 bits of the memory).
535 if ((size & DDR_SIZE_ENABLED) &&
536 !(base & DDR_BASE_CS_HIGH_MASK)) {
537 struct mbus_dram_window *w;
539 w = &mvebu_mbus_dram_info.cs[cs++];
541 w->mbus_attr = 0xf & ~(1 << i);
542 if (mbus->hw_io_coherency)
543 w->mbus_attr |= ATTR_HW_COHERENCY;
544 w->base = base & DDR_BASE_CS_LOW_MASK;
545 w->size = (size | ~DDR_SIZE_MASK) + 1;
548 mvebu_mbus_dram_info.num_cs = cs;
552 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
557 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
559 for (i = 0, cs = 0; i < 2; i++) {
560 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
563 * Chip select enabled?
566 struct mbus_dram_window *w;
568 w = &mvebu_mbus_dram_info.cs[cs++];
570 w->mbus_attr = 0; /* CS address decoding done inside */
571 /* the DDR controller, no need to */
572 /* provide attributes */
573 w->base = map & 0xff800000;
574 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
578 mvebu_mbus_dram_info.num_cs = cs;
581 static const struct mvebu_mbus_mapping armada_370_map[] = {
582 MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
583 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
584 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
585 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
586 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
587 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
588 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
589 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
593 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
595 .num_remappable_wins = 8,
596 .win_cfg_offset = armada_370_xp_mbus_win_offset,
597 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
598 .show_cpu_target = mvebu_sdram_debug_show_orion,
599 .map = armada_370_map,
602 static const struct mvebu_mbus_mapping armada_xp_map[] = {
603 MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
604 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
605 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
606 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
607 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
608 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
609 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
610 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
611 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
612 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
613 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
614 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
615 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
616 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
617 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
618 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
622 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
624 .num_remappable_wins = 8,
625 .win_cfg_offset = armada_370_xp_mbus_win_offset,
626 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
627 .show_cpu_target = mvebu_sdram_debug_show_orion,
628 .map = armada_xp_map,
631 static const struct mvebu_mbus_mapping kirkwood_map[] = {
632 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
633 MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
634 MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
635 MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
639 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
641 .num_remappable_wins = 4,
642 .win_cfg_offset = orion_mbus_win_offset,
643 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
644 .show_cpu_target = mvebu_sdram_debug_show_orion,
648 static const struct mvebu_mbus_mapping dove_map[] = {
649 MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
650 MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
651 MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
652 MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
653 MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
657 static const struct mvebu_mbus_soc_data dove_mbus_data = {
659 .num_remappable_wins = 4,
660 .win_cfg_offset = orion_mbus_win_offset,
661 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
662 .show_cpu_target = mvebu_sdram_debug_show_dove,
666 static const struct mvebu_mbus_mapping orion5x_map[] = {
667 MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
668 MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
669 MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
670 MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
671 MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
672 MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
673 MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
678 * Some variants of Orion5x have 4 remappable windows, some other have
681 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
683 .num_remappable_wins = 4,
684 .win_cfg_offset = orion_mbus_win_offset,
685 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
686 .show_cpu_target = mvebu_sdram_debug_show_orion,
690 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
692 .num_remappable_wins = 2,
693 .win_cfg_offset = orion_mbus_win_offset,
694 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
695 .show_cpu_target = mvebu_sdram_debug_show_orion,
699 static const struct mvebu_mbus_mapping mv78xx0_map[] = {
700 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
701 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
702 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
703 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
704 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
705 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
706 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
707 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
708 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
709 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
713 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
715 .num_remappable_wins = 8,
716 .win_cfg_offset = mv78xx0_mbus_win_offset,
717 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
718 .show_cpu_target = mvebu_sdram_debug_show_orion,
723 * The driver doesn't yet have a DT binding because the details of
724 * this DT binding still need to be sorted out. However, as a
725 * preparation, we already use of_device_id to match a SoC description
726 * string against the SoC specific details of this driver.
728 static const struct of_device_id of_mvebu_mbus_ids[] = {
729 { .compatible = "marvell,armada370-mbus",
730 .data = &armada_370_mbus_data, },
731 { .compatible = "marvell,armadaxp-mbus",
732 .data = &armada_xp_mbus_data, },
733 { .compatible = "marvell,kirkwood-mbus",
734 .data = &kirkwood_mbus_data, },
735 { .compatible = "marvell,dove-mbus",
736 .data = &dove_mbus_data, },
737 { .compatible = "marvell,orion5x-88f5281-mbus",
738 .data = &orion5x_4win_mbus_data, },
739 { .compatible = "marvell,orion5x-88f5182-mbus",
740 .data = &orion5x_2win_mbus_data, },
741 { .compatible = "marvell,orion5x-88f5181-mbus",
742 .data = &orion5x_2win_mbus_data, },
743 { .compatible = "marvell,orion5x-88f6183-mbus",
744 .data = &orion5x_4win_mbus_data, },
745 { .compatible = "marvell,mv78xx0-mbus",
746 .data = &mv78xx0_mbus_data, },
751 * Public API of the driver
753 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
754 unsigned int attribute,
755 phys_addr_t base, size_t size,
758 struct mvebu_mbus_state *s = &mbus_state;
760 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
761 pr_err("cannot add window '%x:%x', conflicts with another window\n",
766 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
769 int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
770 size_t size, phys_addr_t remap,
773 struct mvebu_mbus_state *s = &mbus_state;
780 for (i = 0; s->soc->map[i].name; i++)
781 if (!strcmp(s->soc->map[i].name, devname))
784 if (!s->soc->map[i].name) {
785 pr_err("unknown device '%s'\n", devname);
789 target = s->soc->map[i].target;
790 attr = s->soc->map[i].attr;
792 if (flags == MVEBU_MBUS_PCI_MEM)
794 else if (flags == MVEBU_MBUS_PCI_WA)
797 return mvebu_mbus_add_window_remap_by_id(target, attr, base,
801 int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
803 return mvebu_mbus_add_window_remap_flags(devname, base, size,
804 MVEBU_MBUS_NO_REMAP, 0);
807 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
808 phys_addr_t base, size_t size)
810 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
811 size, MVEBU_MBUS_NO_REMAP);
814 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
818 win = mvebu_mbus_find_window(&mbus_state, base, size);
822 mvebu_mbus_disable_window(&mbus_state, win);
826 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
830 *res = mbus_state.pcie_mem_aperture;
833 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
837 *res = mbus_state.pcie_io_aperture;
840 static __init int mvebu_mbus_debugfs_init(void)
842 struct mvebu_mbus_state *s = &mbus_state;
845 * If no base has been initialized, doesn't make sense to
846 * register the debugfs entries. We may be on a multiplatform
847 * kernel that isn't running a Marvell EBU SoC.
849 if (!s->mbuswins_base)
852 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
853 if (s->debugfs_root) {
854 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
855 s->debugfs_root, NULL,
856 &mvebu_sdram_debug_fops);
857 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
858 s->debugfs_root, NULL,
859 &mvebu_devs_debug_fops);
864 fs_initcall(mvebu_mbus_debugfs_init);
866 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
867 phys_addr_t mbuswins_phys_base,
868 size_t mbuswins_size,
869 phys_addr_t sdramwins_phys_base,
870 size_t sdramwins_size)
874 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
875 if (!mbus->mbuswins_base)
878 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
879 if (!mbus->sdramwins_base) {
880 iounmap(mbus_state.mbuswins_base);
884 if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
885 mbus->hw_io_coherency = 1;
887 for (win = 0; win < mbus->soc->num_wins; win++)
888 mvebu_mbus_disable_window(mbus, win);
890 mbus->soc->setup_cpu_target(mbus);
895 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
896 size_t mbuswins_size,
897 phys_addr_t sdramwins_phys_base,
898 size_t sdramwins_size)
900 const struct of_device_id *of_id;
902 for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
903 if (!strcmp(of_id->compatible, soc))
906 if (!of_id->compatible) {
907 pr_err("could not find a matching SoC family\n");
911 mbus_state.soc = of_id->data;
913 return mvebu_mbus_common_init(&mbus_state,
922 * The window IDs in the ranges DT property have the following format:
923 * - bits 28 to 31: MBus custom field
924 * - bits 24 to 27: window target ID
925 * - bits 16 to 23: window attribute ID
926 * - bits 0 to 15: unused
928 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
929 #define TARGET(id) (((id) & 0x0F000000) >> 24)
930 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
932 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
936 const struct mvebu_mbus_mapping *map = mbus->soc->map;
940 /* Search for a suitable window in the existing mappings */
941 for (i = 0; map[i].name; i++)
942 if (map[i].target == target &&
943 map[i].attr == (attr & map[i].attrmask))
948 pr_err("window 0x%x:0x%x is unknown, skipping\n",
953 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
954 pr_err("cannot add window '%s', conflicts with another window\n",
959 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
961 pr_err("cannot add window '%s', too many windows\n",
969 mbus_parse_ranges(struct device_node *node,
970 int *addr_cells, int *c_addr_cells, int *c_size_cells,
971 int *cell_count, const __be32 **ranges_start,
972 const __be32 **ranges_end)
975 int ranges_len, tuple_len;
977 /* Allow a node with no 'ranges' property */
978 *ranges_start = of_get_property(node, "ranges", &ranges_len);
979 if (*ranges_start == NULL) {
980 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
981 *ranges_start = *ranges_end = NULL;
984 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
986 *addr_cells = of_n_addr_cells(node);
988 prop = of_get_property(node, "#address-cells", NULL);
989 *c_addr_cells = be32_to_cpup(prop);
991 prop = of_get_property(node, "#size-cells", NULL);
992 *c_size_cells = be32_to_cpup(prop);
994 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
995 tuple_len = (*cell_count) * sizeof(__be32);
997 if (ranges_len % tuple_len) {
998 pr_warn("malformed ranges entry '%s'\n", node->name);
1004 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1005 struct device_node *np)
1007 int addr_cells, c_addr_cells, c_size_cells;
1008 int i, ret, cell_count;
1009 const __be32 *r, *ranges_start, *ranges_end;
1011 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1012 &c_size_cells, &cell_count,
1013 &ranges_start, &ranges_end);
1017 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1018 u32 windowid, base, size;
1022 * An entry with a non-zero custom field do not
1023 * correspond to a static window, so skip it.
1025 windowid = of_read_number(r, 1);
1026 if (CUSTOM(windowid))
1029 target = TARGET(windowid);
1030 attr = ATTR(windowid);
1032 base = of_read_number(r + c_addr_cells, addr_cells);
1033 size = of_read_number(r + c_addr_cells + addr_cells,
1035 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1042 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1043 struct resource *mem,
1044 struct resource *io)
1050 * These are optional, so we clear them and they'll
1051 * be zero if they are missing from the DT.
1053 memset(mem, 0, sizeof(struct resource));
1054 memset(io, 0, sizeof(struct resource));
1056 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1058 mem->start = reg[0];
1059 mem->end = mem->start + reg[1];
1060 mem->flags = IORESOURCE_MEM;
1063 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1066 io->end = io->start + reg[1];
1067 io->flags = IORESOURCE_IO;
1071 int __init mvebu_mbus_dt_init(void)
1073 struct resource mbuswins_res, sdramwins_res;
1074 struct device_node *np, *controller;
1075 const struct of_device_id *of_id;
1079 np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
1081 pr_err("could not find a matching SoC family\n");
1085 of_id = of_match_node(of_mvebu_mbus_ids, np);
1086 mbus_state.soc = of_id->data;
1088 prop = of_get_property(np, "controller", NULL);
1090 pr_err("required 'controller' property missing\n");
1094 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1096 pr_err("could not find an 'mbus-controller' node\n");
1100 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1101 pr_err("cannot get MBUS register address\n");
1105 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1106 pr_err("cannot get SDRAM register address\n");
1110 /* Get optional pcie-{mem,io}-aperture properties */
1111 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1112 &mbus_state.pcie_io_aperture);
1114 ret = mvebu_mbus_common_init(&mbus_state,
1116 resource_size(&mbuswins_res),
1117 sdramwins_res.start,
1118 resource_size(&sdramwins_res));
1122 /* Setup statically declared windows in the DT */
1123 return mbus_dt_setup(&mbus_state, np);