2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/mbus.h>
55 #include <linux/ioport.h>
57 #include <linux/of_address.h>
58 #include <linux/debugfs.h>
59 #include <linux/log2.h>
60 #include <linux/syscore_ops.h>
63 * DDR target is the same on all platforms.
68 * CPU Address Decode Windows registers
70 #define WIN_CTRL_OFF 0x0000
71 #define WIN_CTRL_ENABLE BIT(0)
72 #define WIN_CTRL_TGT_MASK 0xf0
73 #define WIN_CTRL_TGT_SHIFT 4
74 #define WIN_CTRL_ATTR_MASK 0xff00
75 #define WIN_CTRL_ATTR_SHIFT 8
76 #define WIN_CTRL_SIZE_MASK 0xffff0000
77 #define WIN_CTRL_SIZE_SHIFT 16
78 #define WIN_BASE_OFF 0x0004
79 #define WIN_BASE_LOW 0xffff0000
80 #define WIN_BASE_HIGH 0xf
81 #define WIN_REMAP_LO_OFF 0x0008
82 #define WIN_REMAP_LOW 0xffff0000
83 #define WIN_REMAP_HI_OFF 0x000c
85 #define ATTR_HW_COHERENCY (0x1 << 4)
87 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
88 #define DDR_BASE_CS_HIGH_MASK 0xf
89 #define DDR_BASE_CS_LOW_MASK 0xff000000
90 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
91 #define DDR_SIZE_ENABLED BIT(0)
92 #define DDR_SIZE_CS_MASK 0x1c
93 #define DDR_SIZE_CS_SHIFT 2
94 #define DDR_SIZE_MASK 0xff000000
96 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
98 /* Relative to mbusbridge_base */
99 #define MBUS_BRIDGE_CTRL_OFF 0x0
100 #define MBUS_BRIDGE_BASE_OFF 0x4
102 /* Maximum number of windows, for all known platforms */
103 #define MBUS_WINS_MAX 20
105 struct mvebu_mbus_state;
107 struct mvebu_mbus_soc_data {
108 unsigned int num_wins;
109 unsigned int num_remappable_wins;
110 bool has_mbus_bridge;
111 unsigned int (*win_cfg_offset)(const int win);
112 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
113 int (*show_cpu_target)(struct mvebu_mbus_state *s,
114 struct seq_file *seq, void *v);
118 * Used to store the state of one MBus window accross suspend/resume.
120 struct mvebu_mbus_win_data {
127 struct mvebu_mbus_state {
128 void __iomem *mbuswins_base;
129 void __iomem *sdramwins_base;
130 void __iomem *mbusbridge_base;
131 struct dentry *debugfs_root;
132 struct dentry *debugfs_sdram;
133 struct dentry *debugfs_devs;
134 struct resource pcie_mem_aperture;
135 struct resource pcie_io_aperture;
136 const struct mvebu_mbus_soc_data *soc;
139 /* Used during suspend/resume */
140 u32 mbus_bridge_ctrl;
141 u32 mbus_bridge_base;
142 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
145 static struct mvebu_mbus_state mbus_state;
147 static struct mbus_dram_target_info mvebu_mbus_dram_info;
148 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
150 return &mvebu_mbus_dram_info;
152 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
155 * Functions to manipulate the address decoding windows
158 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
159 int win, int *enabled, u64 *base,
160 u32 *size, u8 *target, u8 *attr,
163 void __iomem *addr = mbus->mbuswins_base +
164 mbus->soc->win_cfg_offset(win);
165 u32 basereg = readl(addr + WIN_BASE_OFF);
166 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
168 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
174 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
175 *base |= (basereg & WIN_BASE_LOW);
176 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
179 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
182 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
185 if (win < mbus->soc->num_remappable_wins) {
186 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
187 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
188 *remap = ((u64)remap_hi << 32) | remap_low;
194 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
199 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
201 writel(0, addr + WIN_BASE_OFF);
202 writel(0, addr + WIN_CTRL_OFF);
203 if (win < mbus->soc->num_remappable_wins) {
204 writel(0, addr + WIN_REMAP_LO_OFF);
205 writel(0, addr + WIN_REMAP_HI_OFF);
209 /* Checks whether the given window number is available */
210 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
213 void __iomem *addr = mbus->mbuswins_base +
214 mbus->soc->win_cfg_offset(win);
215 u32 ctrl = readl(addr + WIN_CTRL_OFF);
216 return !(ctrl & WIN_CTRL_ENABLE);
220 * Checks whether the given (base, base+size) area doesn't overlap an
223 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
224 phys_addr_t base, size_t size,
227 u64 end = (u64)base + size;
230 for (win = 0; win < mbus->soc->num_wins; win++) {
236 mvebu_mbus_read_window(mbus, win,
237 &enabled, &wbase, &wsize,
238 &wtarget, &wattr, NULL);
243 wend = wbase + wsize;
246 * Check if the current window overlaps with the
247 * proposed physical range
249 if ((u64)base < wend && end > wbase)
256 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
257 phys_addr_t base, size_t size)
261 for (win = 0; win < mbus->soc->num_wins; win++) {
266 mvebu_mbus_read_window(mbus, win,
267 &enabled, &wbase, &wsize,
273 if (base == wbase && size == wsize)
280 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
281 int win, phys_addr_t base, size_t size,
282 phys_addr_t remap, u8 target,
285 void __iomem *addr = mbus->mbuswins_base +
286 mbus->soc->win_cfg_offset(win);
287 u32 ctrl, remap_addr;
289 if (!is_power_of_2(size)) {
290 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
294 if ((base & (phys_addr_t)(size - 1)) != 0) {
295 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
300 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
301 (attr << WIN_CTRL_ATTR_SHIFT) |
302 (target << WIN_CTRL_TGT_SHIFT) |
305 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
306 writel(ctrl, addr + WIN_CTRL_OFF);
307 if (win < mbus->soc->num_remappable_wins) {
308 if (remap == MVEBU_MBUS_NO_REMAP)
312 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
313 writel(0, addr + WIN_REMAP_HI_OFF);
319 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
320 phys_addr_t base, size_t size,
321 phys_addr_t remap, u8 target,
326 if (remap == MVEBU_MBUS_NO_REMAP) {
327 for (win = mbus->soc->num_remappable_wins;
328 win < mbus->soc->num_wins; win++)
329 if (mvebu_mbus_window_is_free(mbus, win))
330 return mvebu_mbus_setup_window(mbus, win, base,
336 for (win = 0; win < mbus->soc->num_wins; win++)
337 if (mvebu_mbus_window_is_free(mbus, win))
338 return mvebu_mbus_setup_window(mbus, win, base, size,
339 remap, target, attr);
348 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
349 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
350 struct seq_file *seq, void *v)
354 for (i = 0; i < 4; i++) {
355 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
356 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
360 if (!(sizereg & DDR_SIZE_ENABLED)) {
361 seq_printf(seq, "[%d] disabled\n", i);
365 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
366 base |= basereg & DDR_BASE_CS_LOW_MASK;
367 size = (sizereg | ~DDR_SIZE_MASK);
369 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
370 i, (unsigned long long)base,
371 (unsigned long long)base + size + 1,
372 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
378 /* Special function for Dove */
379 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
380 struct seq_file *seq, void *v)
384 for (i = 0; i < 2; i++) {
385 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
390 seq_printf(seq, "[%d] disabled\n", i);
394 base = map & 0xff800000;
395 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
397 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
398 i, (unsigned long long)base,
399 (unsigned long long)base + size, i);
405 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
407 struct mvebu_mbus_state *mbus = &mbus_state;
408 return mbus->soc->show_cpu_target(mbus, seq, v);
411 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
413 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
416 static const struct file_operations mvebu_sdram_debug_fops = {
417 .open = mvebu_sdram_debug_open,
420 .release = single_release,
423 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
425 struct mvebu_mbus_state *mbus = &mbus_state;
428 for (win = 0; win < mbus->soc->num_wins; win++) {
434 mvebu_mbus_read_window(mbus, win,
435 &enabled, &wbase, &wsize,
436 &wtarget, &wattr, &wremap);
439 seq_printf(seq, "[%02d] disabled\n", win);
443 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
444 win, (unsigned long long)wbase,
445 (unsigned long long)(wbase + wsize), wtarget, wattr);
447 if (!is_power_of_2(wsize) ||
448 ((wbase & (u64)(wsize - 1)) != 0))
449 seq_puts(seq, " (Invalid base/size!!)");
451 if (win < mbus->soc->num_remappable_wins) {
452 seq_printf(seq, " (remap %016llx)\n",
453 (unsigned long long)wremap);
455 seq_printf(seq, "\n");
461 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
463 return single_open(file, mvebu_devs_debug_show, inode->i_private);
466 static const struct file_operations mvebu_devs_debug_fops = {
467 .open = mvebu_devs_debug_open,
470 .release = single_release,
474 * SoC-specific functions and definitions
477 static unsigned int orion_mbus_win_offset(int win)
482 static unsigned int armada_370_xp_mbus_win_offset(int win)
484 /* The register layout is a bit annoying and the below code
485 * tries to cope with it.
486 * - At offset 0x0, there are the registers for the first 8
487 * windows, with 4 registers of 32 bits per window (ctrl,
488 * base, remap low, remap high)
489 * - Then at offset 0x80, there is a hole of 0x10 bytes for
490 * the internal registers base address and internal units
491 * sync barrier register.
492 * - Then at offset 0x90, there the registers for 12
493 * windows, with only 2 registers of 32 bits per window
499 return 0x90 + ((win - 8) << 3);
502 static unsigned int mv78xx0_mbus_win_offset(int win)
507 return 0x900 + ((win - 8) << 4);
511 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
516 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
518 for (i = 0, cs = 0; i < 4; i++) {
519 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
520 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
523 * We only take care of entries for which the chip
524 * select is enabled, and that don't have high base
525 * address bits set (devices can only access the first
526 * 32 bits of the memory).
528 if ((size & DDR_SIZE_ENABLED) &&
529 !(base & DDR_BASE_CS_HIGH_MASK)) {
530 struct mbus_dram_window *w;
532 w = &mvebu_mbus_dram_info.cs[cs++];
534 w->mbus_attr = 0xf & ~(1 << i);
535 if (mbus->hw_io_coherency)
536 w->mbus_attr |= ATTR_HW_COHERENCY;
537 w->base = base & DDR_BASE_CS_LOW_MASK;
538 w->size = (size | ~DDR_SIZE_MASK) + 1;
541 mvebu_mbus_dram_info.num_cs = cs;
545 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
550 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
552 for (i = 0, cs = 0; i < 2; i++) {
553 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
556 * Chip select enabled?
559 struct mbus_dram_window *w;
561 w = &mvebu_mbus_dram_info.cs[cs++];
563 w->mbus_attr = 0; /* CS address decoding done inside */
564 /* the DDR controller, no need to */
565 /* provide attributes */
566 w->base = map & 0xff800000;
567 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
571 mvebu_mbus_dram_info.num_cs = cs;
574 static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
576 .num_remappable_wins = 8,
577 .has_mbus_bridge = true,
578 .win_cfg_offset = armada_370_xp_mbus_win_offset,
579 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
580 .show_cpu_target = mvebu_sdram_debug_show_orion,
583 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
585 .num_remappable_wins = 4,
586 .win_cfg_offset = orion_mbus_win_offset,
587 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
588 .show_cpu_target = mvebu_sdram_debug_show_orion,
591 static const struct mvebu_mbus_soc_data dove_mbus_data = {
593 .num_remappable_wins = 4,
594 .win_cfg_offset = orion_mbus_win_offset,
595 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
596 .show_cpu_target = mvebu_sdram_debug_show_dove,
600 * Some variants of Orion5x have 4 remappable windows, some other have
603 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
605 .num_remappable_wins = 4,
606 .win_cfg_offset = orion_mbus_win_offset,
607 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
608 .show_cpu_target = mvebu_sdram_debug_show_orion,
611 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
613 .num_remappable_wins = 2,
614 .win_cfg_offset = orion_mbus_win_offset,
615 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
616 .show_cpu_target = mvebu_sdram_debug_show_orion,
619 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
621 .num_remappable_wins = 8,
622 .win_cfg_offset = mv78xx0_mbus_win_offset,
623 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
624 .show_cpu_target = mvebu_sdram_debug_show_orion,
627 static const struct of_device_id of_mvebu_mbus_ids[] = {
628 { .compatible = "marvell,armada370-mbus",
629 .data = &armada_370_xp_mbus_data, },
630 { .compatible = "marvell,armadaxp-mbus",
631 .data = &armada_370_xp_mbus_data, },
632 { .compatible = "marvell,kirkwood-mbus",
633 .data = &kirkwood_mbus_data, },
634 { .compatible = "marvell,dove-mbus",
635 .data = &dove_mbus_data, },
636 { .compatible = "marvell,orion5x-88f5281-mbus",
637 .data = &orion5x_4win_mbus_data, },
638 { .compatible = "marvell,orion5x-88f5182-mbus",
639 .data = &orion5x_2win_mbus_data, },
640 { .compatible = "marvell,orion5x-88f5181-mbus",
641 .data = &orion5x_2win_mbus_data, },
642 { .compatible = "marvell,orion5x-88f6183-mbus",
643 .data = &orion5x_4win_mbus_data, },
644 { .compatible = "marvell,mv78xx0-mbus",
645 .data = &mv78xx0_mbus_data, },
650 * Public API of the driver
652 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
653 unsigned int attribute,
654 phys_addr_t base, size_t size,
657 struct mvebu_mbus_state *s = &mbus_state;
659 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
660 pr_err("cannot add window '%x:%x', conflicts with another window\n",
665 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
668 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
669 phys_addr_t base, size_t size)
671 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
672 size, MVEBU_MBUS_NO_REMAP);
675 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
679 win = mvebu_mbus_find_window(&mbus_state, base, size);
683 mvebu_mbus_disable_window(&mbus_state, win);
687 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
691 *res = mbus_state.pcie_mem_aperture;
694 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
698 *res = mbus_state.pcie_io_aperture;
701 static __init int mvebu_mbus_debugfs_init(void)
703 struct mvebu_mbus_state *s = &mbus_state;
706 * If no base has been initialized, doesn't make sense to
707 * register the debugfs entries. We may be on a multiplatform
708 * kernel that isn't running a Marvell EBU SoC.
710 if (!s->mbuswins_base)
713 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
714 if (s->debugfs_root) {
715 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
716 s->debugfs_root, NULL,
717 &mvebu_sdram_debug_fops);
718 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
719 s->debugfs_root, NULL,
720 &mvebu_devs_debug_fops);
725 fs_initcall(mvebu_mbus_debugfs_init);
727 static int mvebu_mbus_suspend(void)
729 struct mvebu_mbus_state *s = &mbus_state;
732 if (!s->mbusbridge_base)
735 for (win = 0; win < s->soc->num_wins; win++) {
736 void __iomem *addr = s->mbuswins_base +
737 s->soc->win_cfg_offset(win);
739 s->wins[win].base = readl(addr + WIN_BASE_OFF);
740 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
742 if (win >= s->soc->num_remappable_wins)
745 s->wins[win].remap_lo = readl(addr + WIN_REMAP_LO_OFF);
746 s->wins[win].remap_hi = readl(addr + WIN_REMAP_HI_OFF);
749 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
750 MBUS_BRIDGE_CTRL_OFF);
751 s->mbus_bridge_base = readl(s->mbusbridge_base +
752 MBUS_BRIDGE_BASE_OFF);
757 static void mvebu_mbus_resume(void)
759 struct mvebu_mbus_state *s = &mbus_state;
762 writel(s->mbus_bridge_ctrl,
763 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
764 writel(s->mbus_bridge_base,
765 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
767 for (win = 0; win < s->soc->num_wins; win++) {
768 void __iomem *addr = s->mbuswins_base +
769 s->soc->win_cfg_offset(win);
771 writel(s->wins[win].base, addr + WIN_BASE_OFF);
772 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
774 if (win >= s->soc->num_remappable_wins)
777 writel(s->wins[win].remap_lo, addr + WIN_REMAP_LO_OFF);
778 writel(s->wins[win].remap_hi, addr + WIN_REMAP_HI_OFF);
782 struct syscore_ops mvebu_mbus_syscore_ops = {
783 .suspend = mvebu_mbus_suspend,
784 .resume = mvebu_mbus_resume,
787 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
788 phys_addr_t mbuswins_phys_base,
789 size_t mbuswins_size,
790 phys_addr_t sdramwins_phys_base,
791 size_t sdramwins_size,
792 phys_addr_t mbusbridge_phys_base,
793 size_t mbusbridge_size)
797 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
798 if (!mbus->mbuswins_base)
801 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
802 if (!mbus->sdramwins_base) {
803 iounmap(mbus_state.mbuswins_base);
807 if (mbusbridge_phys_base) {
808 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
810 if (!mbus->mbusbridge_base) {
811 iounmap(mbus->sdramwins_base);
812 iounmap(mbus->mbuswins_base);
816 mbus->mbusbridge_base = NULL;
818 for (win = 0; win < mbus->soc->num_wins; win++)
819 mvebu_mbus_disable_window(mbus, win);
821 mbus->soc->setup_cpu_target(mbus);
823 register_syscore_ops(&mvebu_mbus_syscore_ops);
828 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
829 size_t mbuswins_size,
830 phys_addr_t sdramwins_phys_base,
831 size_t sdramwins_size)
833 const struct of_device_id *of_id;
835 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
836 if (!strcmp(of_id->compatible, soc))
839 if (!of_id->compatible[0]) {
840 pr_err("could not find a matching SoC family\n");
844 mbus_state.soc = of_id->data;
846 return mvebu_mbus_common_init(&mbus_state,
850 sdramwins_size, 0, 0);
855 * The window IDs in the ranges DT property have the following format:
856 * - bits 28 to 31: MBus custom field
857 * - bits 24 to 27: window target ID
858 * - bits 16 to 23: window attribute ID
859 * - bits 0 to 15: unused
861 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
862 #define TARGET(id) (((id) & 0x0F000000) >> 24)
863 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
865 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
869 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
870 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
875 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
877 pr_err("cannot add window '%04x:%04x', too many windows\n",
885 mbus_parse_ranges(struct device_node *node,
886 int *addr_cells, int *c_addr_cells, int *c_size_cells,
887 int *cell_count, const __be32 **ranges_start,
888 const __be32 **ranges_end)
891 int ranges_len, tuple_len;
893 /* Allow a node with no 'ranges' property */
894 *ranges_start = of_get_property(node, "ranges", &ranges_len);
895 if (*ranges_start == NULL) {
896 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
897 *ranges_start = *ranges_end = NULL;
900 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
902 *addr_cells = of_n_addr_cells(node);
904 prop = of_get_property(node, "#address-cells", NULL);
905 *c_addr_cells = be32_to_cpup(prop);
907 prop = of_get_property(node, "#size-cells", NULL);
908 *c_size_cells = be32_to_cpup(prop);
910 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
911 tuple_len = (*cell_count) * sizeof(__be32);
913 if (ranges_len % tuple_len) {
914 pr_warn("malformed ranges entry '%s'\n", node->name);
920 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
921 struct device_node *np)
923 int addr_cells, c_addr_cells, c_size_cells;
924 int i, ret, cell_count;
925 const __be32 *r, *ranges_start, *ranges_end;
927 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
928 &c_size_cells, &cell_count,
929 &ranges_start, &ranges_end);
933 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
934 u32 windowid, base, size;
938 * An entry with a non-zero custom field do not
939 * correspond to a static window, so skip it.
941 windowid = of_read_number(r, 1);
942 if (CUSTOM(windowid))
945 target = TARGET(windowid);
946 attr = ATTR(windowid);
948 base = of_read_number(r + c_addr_cells, addr_cells);
949 size = of_read_number(r + c_addr_cells + addr_cells,
951 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
958 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
959 struct resource *mem,
966 * These are optional, so we make sure that resource_size(x) will
969 memset(mem, 0, sizeof(struct resource));
971 memset(io, 0, sizeof(struct resource));
974 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
977 mem->end = mem->start + reg[1] - 1;
978 mem->flags = IORESOURCE_MEM;
981 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
984 io->end = io->start + reg[1] - 1;
985 io->flags = IORESOURCE_IO;
989 int __init mvebu_mbus_dt_init(bool is_coherent)
991 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
992 struct device_node *np, *controller;
993 const struct of_device_id *of_id;
997 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
999 pr_err("could not find a matching SoC family\n");
1003 mbus_state.soc = of_id->data;
1005 prop = of_get_property(np, "controller", NULL);
1007 pr_err("required 'controller' property missing\n");
1011 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1013 pr_err("could not find an 'mbus-controller' node\n");
1017 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1018 pr_err("cannot get MBUS register address\n");
1022 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1023 pr_err("cannot get SDRAM register address\n");
1028 * Set the resource to 0 so that it can be left unmapped by
1029 * mvebu_mbus_common_init() if the DT doesn't carry the
1030 * necessary information. This is needed to preserve backward
1033 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1035 if (mbus_state.soc->has_mbus_bridge) {
1036 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1037 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1040 mbus_state.hw_io_coherency = is_coherent;
1042 /* Get optional pcie-{mem,io}-aperture properties */
1043 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1044 &mbus_state.pcie_io_aperture);
1046 ret = mvebu_mbus_common_init(&mbus_state,
1048 resource_size(&mbuswins_res),
1049 sdramwins_res.start,
1050 resource_size(&sdramwins_res),
1051 mbusbridge_res.start,
1052 resource_size(&mbusbridge_res));
1056 /* Setup statically declared windows in the DT */
1057 return mbus_dt_setup(&mbus_state, np);