2 * OMAP L3 Interconnect error handling driver
4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/slab.h>
25 #include "omap_l3_noc.h"
28 * Interrupt Handler for L3 error detection.
29 * 1) Identify the L3 clockdomain partition to which the error belongs to.
30 * 2) Identify the slave where the error information is logged
31 * 3) Print the logged information.
32 * 4) Add dump stack to provide kernel trace.
34 * Two Types of errors :
35 * 1) Custom errors in L3 :
36 * Target like DMM/FW/EMIF generates SRESP=ERR error
37 * 2) Standard L3 error:
39 * L3 tries to access target while it is idle
41 * - Address hole error:
42 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
43 * do not have connectivity, the error is logged in
44 * their default target which is DMM2.
46 * On High Secure devices, firewall errors are possible and those
47 * can be trapped as well. But the trapping is implemented as part
48 * secure software and hence need not be implemented here.
50 static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
53 struct omap_l3 *l3 = _l3;
56 u32 std_err_main, err_reg, clear, masterid;
57 void __iomem *base, *l3_targ_base;
58 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
59 char *target_name, *master_name = "UN IDENTIFIED";
60 struct l3_target_data *l3_targ_inst;
62 /* Get the Type of interrupt */
63 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
65 for (i = 0; i < L3_MODULES; i++) {
67 * Read the regerr register of the clock domain
68 * to determine the source
70 base = l3->l3_base[i];
71 err_reg = readl_relaxed(base + l3_flagmux[i] +
72 L3_FLAGMUX_REGERR0 + (inttype << 3));
74 /* Get the corresponding error and analyse */
76 /* Identify the source from control status register */
77 err_src = __ffs(err_reg);
78 l3_targ_inst = &l3_targ[i][err_src];
79 target_name = l3_targ_inst->name;
80 l3_targ_base = base + l3_targ_inst->offset;
82 /* Read the stderrlog_main_source from clk domain */
83 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
84 l3_targ_slvofslsb = l3_targ_base +
85 L3_TARG_STDERRLOG_SLVOFSLSB;
86 l3_targ_mstaddr = l3_targ_base +
87 L3_TARG_STDERRLOG_MSTADDR;
89 std_err_main = readl_relaxed(l3_targ_stderr);
90 masterid = readl_relaxed(l3_targ_mstaddr);
92 switch (std_err_main & CUSTOM_ERROR) {
94 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
96 readl_relaxed(l3_targ_slvofslsb));
97 /* clear the std error log*/
98 clear = std_err_main | CLEAR_STDERR_LOG;
99 writel_relaxed(clear, l3_targ_stderr);
103 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
104 if (masterid == l3_masters[k].id)
108 WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
109 master_name, target_name);
110 /* clear the std error log*/
111 clear = std_err_main | CLEAR_STDERR_LOG;
112 writel_relaxed(clear, l3_targ_stderr);
116 /* Nothing to be handled here as of now */
119 /* Error found so break the for loop */
126 static int omap_l3_probe(struct platform_device *pdev)
128 static struct omap_l3 *l3;
131 l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
135 l3->dev = &pdev->dev;
136 platform_set_drvdata(pdev, l3);
138 /* Get mem resources */
139 for (i = 0; i < L3_MODULES; i++) {
140 struct resource *res = platform_get_resource(pdev,
143 l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
144 if (IS_ERR(l3->l3_base[i])) {
145 dev_err(l3->dev, "ioremap %d failed\n", i);
146 return PTR_ERR(l3->l3_base[i]);
151 * Setup interrupt Handlers
153 l3->debug_irq = platform_get_irq(pdev, 0);
154 ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
155 IRQF_DISABLED, "l3-dbg-irq", l3);
157 dev_err(l3->dev, "request_irq failed for %d\n",
162 l3->app_irq = platform_get_irq(pdev, 1);
163 ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
164 IRQF_DISABLED, "l3-app-irq", l3);
166 dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
171 #if defined(CONFIG_OF)
172 static const struct of_device_id l3_noc_match[] = {
173 {.compatible = "ti,omap4-l3-noc", },
176 MODULE_DEVICE_TABLE(of, l3_noc_match);
178 #define l3_noc_match NULL
181 static struct platform_driver omap_l3_driver = {
182 .probe = omap_l3_probe,
184 .name = "omap_l3_noc",
185 .owner = THIS_MODULE,
186 .of_match_table = l3_noc_match,
190 static int __init omap_l3_init(void)
192 return platform_driver_register(&omap_l3_driver);
194 postcore_initcall_sync(omap_l3_init);
196 static void __exit omap_l3_exit(void)
198 platform_driver_unregister(&omap_l3_driver);
200 module_exit(omap_l3_exit);