drivers/bus/omap_l3_noc.c

   1 /*
   2  * OMAP L3 Interconnect error handling driver
   3  *
   4  * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *      Sricharan <r.sricharan@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26
  27 #include "omap_l3_noc.h"
  28
  29 /*
  30  * Interrupt Handler for L3 error detection.
  31  *      1) Identify the L3 clockdomain partition to which the error belongs to.
  32  *      2) Identify the slave where the error information is logged
  33  *      3) Print the logged information.
  34  *      4) Add dump stack to provide kernel trace.
  35  *
  36  * Two Types of errors :
  37  *      1) Custom errors in L3 :
  38  *              Target like DMM/FW/EMIF generates SRESP=ERR error
  39  *      2) Standard L3 error:
  40  *              - Unsupported CMD.
  41  *                      L3 tries to access target while it is idle
  42  *              - OCP disconnect.
  43  *              - Address hole error:
  44  *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
  45  *                      do not have connectivity, the error is logged in
  46  *                      their default target which is DMM2.
  47  *
  48  *      On High Secure devices, firewall errors are possible and those
  49  *      can be trapped as well. But the trapping is implemented as part
  50  *      secure software and hence need not be implemented here.
  51  */
  52 static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
  53 {
  54
  55         struct omap_l3 *l3 = _l3;
  56         int inttype, i, k;
  57         int err_src = 0;
  58         u32 std_err_main, err_reg, clear, masterid;
  59         void __iomem *base, *l3_targ_base;
  60         void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
  61         char *target_name, *master_name = "UN IDENTIFIED";
  62         struct l3_target_data *l3_targ_inst;
  63         struct l3_flagmux_data *flag_mux;
  64         struct l3_masters_data *master;
  65         char *err_description;
  66         char err_string[30] = { 0 };
  67
  68         /* Get the Type of interrupt */
  69         inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
  70
  71         for (i = 0; i < l3->num_modules; i++) {
  72                 /*
  73                  * Read the regerr register of the clock domain
  74                  * to determine the source
  75                  */
  76                 base = l3->l3_base[i];
  77                 flag_mux = l3->l3_flagmux[i];
  78                 err_reg = readl_relaxed(base + flag_mux->offset +
  79                                         L3_FLAGMUX_REGERR0 + (inttype << 3));
  80
  81                 /* Get the corresponding error and analyse */
  82                 if (err_reg) {
  83                         bool std_err = true;
  84
  85                         /* Identify the source from control status register */
  86                         err_src = __ffs(err_reg);
  87
  88                         /* We DONOT expect err_src to go out of bounds */
  89                         BUG_ON(err_src > MAX_CLKDM_TARGETS);
  90
  91                         if (err_src < flag_mux->num_targ_data) {
  92                                 l3_targ_inst = &flag_mux->l3_targ[err_src];
  93                                 target_name = l3_targ_inst->name;
  94                                 l3_targ_base = base + l3_targ_inst->offset;
  95                         } else {
  96                                 target_name = L3_TARGET_NOT_SUPPORTED;
  97                         }
  98
  99                         /*
 100                          * If we do not know of a register offset to decode
 101                          * and clear, then mask.
 102                          */
 103                         if (target_name == L3_TARGET_NOT_SUPPORTED) {
 104                                 u32 mask_val;
 105                                 void __iomem *mask_reg;
 106
 107                                 /*
 108                                  * Certain plaforms may have "undocumented"
 109                                  * status pending on boot.. So dont generate
 110                                  * a severe warning here.
 111                                  */
 112                                 dev_err(l3->dev,
 113                                         "L3 %s error: target %d mod:%d %s\n",
 114                                         inttype ? "debug" : "application",
 115                                         err_src, i, "(unclearable)");
 116
 117                                 mask_reg = base + flag_mux->offset +
 118                                            L3_FLAGMUX_MASK0 + (inttype << 3);
 119                                 mask_val = readl_relaxed(mask_reg);
 120                                 mask_val &= ~(1 << err_src);
 121                                 writel_relaxed(mask_val, mask_reg);
 122
 123                                 break;
 124                         }
 125
 126                         /* Read the stderrlog_main_source from clk domain */
 127                         l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
 128                         l3_targ_slvofslsb = l3_targ_base +
 129                                             L3_TARG_STDERRLOG_SLVOFSLSB;
 130
 131                         std_err_main = readl_relaxed(l3_targ_stderr);
 132
 133                         switch (std_err_main & CUSTOM_ERROR) {
 134                         case STANDARD_ERROR:
 135                                 err_description = "Standard";
 136                                 snprintf(err_string, sizeof(err_string),
 137                                          ": At Address: 0x%08X ",
 138                                          readl_relaxed(l3_targ_slvofslsb));
 139
 140                                 l3_targ_mstaddr = l3_targ_base +
 141                                                 L3_TARG_STDERRLOG_MSTADDR;
 142                                 break;
 143
 144                         case CUSTOM_ERROR:
 145                                 err_description = "Custom";
 146
 147                                 l3_targ_mstaddr = l3_targ_base +
 148                                                 L3_TARG_STDERRLOG_CINFO_MSTADDR;
 149                                 break;
 150
 151                         default:
 152                                 std_err = false;
 153                                 /* Nothing to be handled here as of now */
 154                                 break;
 155                         }
 156
 157                         if (!std_err)
 158                                 break;
 159
 160                         /* STDERRLOG_MSTADDR Stores the NTTP master address. */
 161                         masterid = (readl_relaxed(l3_targ_mstaddr) &
 162                                     l3->mst_addr_mask) >>
 163                                         __ffs(l3->mst_addr_mask);
 164
 165                         for (k = 0, master = l3->l3_masters;
 166                              k < l3->num_masters; k++, master++) {
 167                                 if (masterid == master->id) {
 168                                         master_name = master->name;
 169                                         break;
 170                                 }
 171                         }
 172
 173                         WARN(true,
 174                              "%s:L3 %s Error: MASTER %s TARGET %s%s\n",
 175                              dev_name(l3->dev),
 176                              err_description,
 177                              master_name, target_name,
 178                              err_string);
 179                         /* clear the std error log*/
 180                         clear = std_err_main | CLEAR_STDERR_LOG;
 181                         writel_relaxed(clear, l3_targ_stderr);
 182
 183                         /* Error found so break the for loop */
 184                         break;
 185                 }
 186         }
 187         return IRQ_HANDLED;
 188 }
 189
 190 static const struct of_device_id l3_noc_match[] = {
 191         {.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
 192         {},
 193 };
 194 MODULE_DEVICE_TABLE(of, l3_noc_match);
 195
 196 static int omap_l3_probe(struct platform_device *pdev)
 197 {
 198         const struct of_device_id *of_id;
 199         static struct omap_l3 *l3;
 200         int ret, i;
 201
 202         of_id = of_match_device(l3_noc_match, &pdev->dev);
 203         if (!of_id) {
 204                 dev_err(&pdev->dev, "OF data missing\n");
 205                 return -EINVAL;
 206         }
 207
 208         l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
 209         if (!l3)
 210                 return -ENOMEM;
 211
 212         memcpy(l3, of_id->data, sizeof(*l3));
 213         l3->dev = &pdev->dev;
 214         platform_set_drvdata(pdev, l3);
 215
 216         /* Get mem resources */
 217         for (i = 0; i < l3->num_modules; i++) {
 218                 struct resource *res = platform_get_resource(pdev,
 219                                                              IORESOURCE_MEM, i);
 220
 221                 l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
 222                 if (IS_ERR(l3->l3_base[i])) {
 223                         dev_err(l3->dev, "ioremap %d failed\n", i);
 224                         return PTR_ERR(l3->l3_base[i]);
 225                 }
 226         }
 227
 228         /*
 229          * Setup interrupt Handlers
 230          */
 231         l3->debug_irq = platform_get_irq(pdev, 0);
 232         ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
 233                                IRQF_DISABLED, "l3-dbg-irq", l3);
 234         if (ret) {
 235                 dev_err(l3->dev, "request_irq failed for %d\n",
 236                         l3->debug_irq);
 237                 return ret;
 238         }
 239
 240         l3->app_irq = platform_get_irq(pdev, 1);
 241         ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
 242                                IRQF_DISABLED, "l3-app-irq", l3);
 243         if (ret)
 244                 dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
 245
 246         return ret;
 247 }
 248
 249 static struct platform_driver omap_l3_driver = {
 250         .probe          = omap_l3_probe,
 251         .driver         = {
 252                 .name           = "omap_l3_noc",
 253                 .owner          = THIS_MODULE,
 254                 .of_match_table = of_match_ptr(l3_noc_match),
 255         },
 256 };
 257
 258 static int __init omap_l3_init(void)
 259 {
 260         return platform_driver_register(&omap_l3_driver);
 261 }
 262 postcore_initcall_sync(omap_l3_init);
 263
 264 static void __exit omap_l3_exit(void)
 265 {
 266         platform_driver_unregister(&omap_l3_driver);
 267 }
 268 module_exit(omap_l3_exit);