drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <linux/delay.h>
  25 #include <asm/smp.h>
  26 #include "agp.h"
  27 #include "intel-agp.h"
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_INTEL_IOMMU
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 struct intel_gtt_driver {
  43         unsigned int gen : 8;
  44         unsigned int is_g33 : 1;
  45         unsigned int is_pineview : 1;
  46         unsigned int is_ironlake : 1;
  47         unsigned int has_pgtbl_enable : 1;
  48         unsigned int dma_mask_size : 8;
  49         /* Chipset specific GTT setup */
  50         int (*setup)(void);
  51         /* This should undo anything done in ->setup() save the unmapping
  52          * of the mmio register file, that's done in the generic code. */
  53         void (*cleanup)(void);
  54         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  55         /* Flags is a more or less chipset specific opaque value.
  56          * For chipsets that need to support old ums (non-gem) code, this
  57          * needs to be identical to the various supported agp memory types! */
  58         bool (*check_flags)(unsigned int flags);
  59         void (*chipset_flush)(void);
  60 };
  61
  62 static struct _intel_private {
  63         const struct intel_gtt_driver *driver;
  64         struct pci_dev *pcidev; /* device one */
  65         struct pci_dev *bridge_dev;
  66         u8 __iomem *registers;
  67         phys_addr_t gtt_phys_addr;
  68         u32 PGETBL_save;
  69         u32 __iomem *gtt;               /* I915G */
  70         bool clear_fake_agp; /* on first access via agp, fill with scratch */
  71         int num_dcache_entries;
  72         void __iomem *i9xx_flush_page;
  73         char *i81x_gtt_table;
  74         struct resource ifp_resource;
  75         int resource_valid;
  76         struct page *scratch_page;
  77         phys_addr_t scratch_page_dma;
  78         int refcount;
  79         /* Whether i915 needs to use the dmar apis or not. */
  80         unsigned int needs_dmar : 1;
  81         phys_addr_t gma_bus_addr;
  82         /*  Size of memory reserved for graphics by the BIOS */
  83         unsigned int stolen_size;
  84         /* Total number of gtt entries. */
  85         unsigned int gtt_total_entries;
  86         /* Part of the gtt that is mappable by the cpu, for those chips where
  87          * this is not the full gtt. */
  88         unsigned int gtt_mappable_entries;
  89 } intel_private;
  90
  91 #define INTEL_GTT_GEN   intel_private.driver->gen
  92 #define IS_G33          intel_private.driver->is_g33
  93 #define IS_PINEVIEW     intel_private.driver->is_pineview
  94 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  95 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  96
  97 static int intel_gtt_map_memory(struct page **pages,
  98                                 unsigned int num_entries,
  99                                 struct sg_table *st)
 100 {
 101         struct scatterlist *sg;
 102         int i;
 103
 104         DBG("try mapping %lu pages\n", (unsigned long)num_entries);
 105
 106         if (sg_alloc_table(st, num_entries, GFP_KERNEL))
 107                 goto err;
 108
 109         for_each_sg(st->sgl, sg, num_entries, i)
 110                 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
 111
 112         if (!pci_map_sg(intel_private.pcidev,
 113                         st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
 114                 goto err;
 115
 116         return 0;
 117
 118 err:
 119         sg_free_table(st);
 120         return -ENOMEM;
 121 }
 122
 123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
 124 {
 125         struct sg_table st;
 126         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 127
 128         pci_unmap_sg(intel_private.pcidev, sg_list,
 129                      num_sg, PCI_DMA_BIDIRECTIONAL);
 130
 131         st.sgl = sg_list;
 132         st.orig_nents = st.nents = num_sg;
 133
 134         sg_free_table(&st);
 135 }
 136
 137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 138 {
 139         return;
 140 }
 141
 142 /* Exists to support ARGB cursors */
 143 static struct page *i8xx_alloc_pages(void)
 144 {
 145         struct page *page;
 146
 147         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 148         if (page == NULL)
 149                 return NULL;
 150
 151         if (set_pages_uc(page, 4) < 0) {
 152                 set_pages_wb(page, 4);
 153                 __free_pages(page, 2);
 154                 return NULL;
 155         }
 156         get_page(page);
 157         atomic_inc(&agp_bridge->current_memory_agp);
 158         return page;
 159 }
 160
 161 static void i8xx_destroy_pages(struct page *page)
 162 {
 163         if (page == NULL)
 164                 return;
 165
 166         set_pages_wb(page, 4);
 167         put_page(page);
 168         __free_pages(page, 2);
 169         atomic_dec(&agp_bridge->current_memory_agp);
 170 }
 171
 172 #define I810_GTT_ORDER 4
 173 static int i810_setup(void)
 174 {
 175         phys_addr_t reg_addr;
 176         char *gtt_table;
 177
 178         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 179         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 180         if (gtt_table == NULL)
 181                 return -ENOMEM;
 182         intel_private.i81x_gtt_table = gtt_table;
 183
 184         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 185
 186         intel_private.registers = ioremap(reg_addr, KB(64));
 187         if (!intel_private.registers)
 188                 return -ENOMEM;
 189
 190         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 191                intel_private.registers+I810_PGETBL_CTL);
 192
 193         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 194
 195         if ((readl(intel_private.registers+I810_DRAM_CTL)
 196                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 197                 dev_info(&intel_private.pcidev->dev,
 198                          "detected 4MB dedicated video ram\n");
 199                 intel_private.num_dcache_entries = 1024;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static void i810_cleanup(void)
 206 {
 207         writel(0, intel_private.registers+I810_PGETBL_CTL);
 208         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 209 }
 210
 211 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 212                                       int type)
 213 {
 214         int i;
 215
 216         if ((pg_start + mem->page_count)
 217                         > intel_private.num_dcache_entries)
 218                 return -EINVAL;
 219
 220         if (!mem->is_flushed)
 221                 global_cache_flush();
 222
 223         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 224                 dma_addr_t addr = i << PAGE_SHIFT;
 225                 intel_private.driver->write_entry(addr,
 226                                                   i, type);
 227         }
 228         readl(intel_private.gtt+i-1);
 229
 230         return 0;
 231 }
 232
 233 /*
 234  * The i810/i830 requires a physical address to program its mouse
 235  * pointer into hardware.
 236  * However the Xserver still writes to it through the agp aperture.
 237  */
 238 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 239 {
 240         struct agp_memory *new;
 241         struct page *page;
 242
 243         switch (pg_count) {
 244         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 245                 break;
 246         case 4:
 247                 /* kludge to get 4 physical pages for ARGB cursor */
 248                 page = i8xx_alloc_pages();
 249                 break;
 250         default:
 251                 return NULL;
 252         }
 253
 254         if (page == NULL)
 255                 return NULL;
 256
 257         new = agp_create_memory(pg_count);
 258         if (new == NULL)
 259                 return NULL;
 260
 261         new->pages[0] = page;
 262         if (pg_count == 4) {
 263                 /* kludge to get 4 physical pages for ARGB cursor */
 264                 new->pages[1] = new->pages[0] + 1;
 265                 new->pages[2] = new->pages[1] + 1;
 266                 new->pages[3] = new->pages[2] + 1;
 267         }
 268         new->page_count = pg_count;
 269         new->num_scratch_pages = pg_count;
 270         new->type = AGP_PHYS_MEMORY;
 271         new->physical = page_to_phys(new->pages[0]);
 272         return new;
 273 }
 274
 275 static void intel_i810_free_by_type(struct agp_memory *curr)
 276 {
 277         agp_free_key(curr->key);
 278         if (curr->type == AGP_PHYS_MEMORY) {
 279                 if (curr->page_count == 4)
 280                         i8xx_destroy_pages(curr->pages[0]);
 281                 else {
 282                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 283                                                              AGP_PAGE_DESTROY_UNMAP);
 284                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 285                                                              AGP_PAGE_DESTROY_FREE);
 286                 }
 287                 agp_free_page_array(curr);
 288         }
 289         kfree(curr);
 290 }
 291
 292 static int intel_gtt_setup_scratch_page(void)
 293 {
 294         struct page *page;
 295         dma_addr_t dma_addr;
 296
 297         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 298         if (page == NULL)
 299                 return -ENOMEM;
 300         get_page(page);
 301         set_pages_uc(page, 1);
 302
 303         if (intel_private.needs_dmar) {
 304                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 305                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 306                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 307                         return -EINVAL;
 308
 309                 intel_private.scratch_page_dma = dma_addr;
 310         } else
 311                 intel_private.scratch_page_dma = page_to_phys(page);
 312
 313         intel_private.scratch_page = page;
 314
 315         return 0;
 316 }
 317
 318 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 319                              unsigned int flags)
 320 {
 321         u32 pte_flags = I810_PTE_VALID;
 322
 323         switch (flags) {
 324         case AGP_DCACHE_MEMORY:
 325                 pte_flags |= I810_PTE_LOCAL;
 326                 break;
 327         case AGP_USER_CACHED_MEMORY:
 328                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 329                 break;
 330         }
 331
 332         writel(addr | pte_flags, intel_private.gtt + entry);
 333 }
 334
 335 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
 336         {32, 8192, 3},
 337         {64, 16384, 4},
 338         {128, 32768, 5},
 339         {256, 65536, 6},
 340         {512, 131072, 7},
 341 };
 342
 343 static unsigned int intel_gtt_stolen_size(void)
 344 {
 345         u16 gmch_ctrl;
 346         u8 rdct;
 347         int local = 0;
 348         static const int ddt[4] = { 0, 16, 32, 64 };
 349         unsigned int stolen_size = 0;
 350
 351         if (INTEL_GTT_GEN == 1)
 352                 return 0; /* no stolen mem on i81x */
 353
 354         pci_read_config_word(intel_private.bridge_dev,
 355                              I830_GMCH_CTRL, &gmch_ctrl);
 356
 357         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 358             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 359                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 360                 case I830_GMCH_GMS_STOLEN_512:
 361                         stolen_size = KB(512);
 362                         break;
 363                 case I830_GMCH_GMS_STOLEN_1024:
 364                         stolen_size = MB(1);
 365                         break;
 366                 case I830_GMCH_GMS_STOLEN_8192:
 367                         stolen_size = MB(8);
 368                         break;
 369                 case I830_GMCH_GMS_LOCAL:
 370                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 371                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 372                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 373                         local = 1;
 374                         break;
 375                 default:
 376                         stolen_size = 0;
 377                         break;
 378                 }
 379         } else {
 380                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 381                 case I855_GMCH_GMS_STOLEN_1M:
 382                         stolen_size = MB(1);
 383                         break;
 384                 case I855_GMCH_GMS_STOLEN_4M:
 385                         stolen_size = MB(4);
 386                         break;
 387                 case I855_GMCH_GMS_STOLEN_8M:
 388                         stolen_size = MB(8);
 389                         break;
 390                 case I855_GMCH_GMS_STOLEN_16M:
 391                         stolen_size = MB(16);
 392                         break;
 393                 case I855_GMCH_GMS_STOLEN_32M:
 394                         stolen_size = MB(32);
 395                         break;
 396                 case I915_GMCH_GMS_STOLEN_48M:
 397                         stolen_size = MB(48);
 398                         break;
 399                 case I915_GMCH_GMS_STOLEN_64M:
 400                         stolen_size = MB(64);
 401                         break;
 402                 case G33_GMCH_GMS_STOLEN_128M:
 403                         stolen_size = MB(128);
 404                         break;
 405                 case G33_GMCH_GMS_STOLEN_256M:
 406                         stolen_size = MB(256);
 407                         break;
 408                 case INTEL_GMCH_GMS_STOLEN_96M:
 409                         stolen_size = MB(96);
 410                         break;
 411                 case INTEL_GMCH_GMS_STOLEN_160M:
 412                         stolen_size = MB(160);
 413                         break;
 414                 case INTEL_GMCH_GMS_STOLEN_224M:
 415                         stolen_size = MB(224);
 416                         break;
 417                 case INTEL_GMCH_GMS_STOLEN_352M:
 418                         stolen_size = MB(352);
 419                         break;
 420                 default:
 421                         stolen_size = 0;
 422                         break;
 423                 }
 424         }
 425
 426         if (stolen_size > 0) {
 427                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 428                        stolen_size / KB(1), local ? "local" : "stolen");
 429         } else {
 430                 dev_info(&intel_private.bridge_dev->dev,
 431                        "no pre-allocated video memory detected\n");
 432                 stolen_size = 0;
 433         }
 434
 435         return stolen_size;
 436 }
 437
 438 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 439 {
 440         u32 pgetbl_ctl, pgetbl_ctl2;
 441
 442         /* ensure that ppgtt is disabled */
 443         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 444         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 445         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 446
 447         /* write the new ggtt size */
 448         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 449         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 450         pgetbl_ctl |= size_flag;
 451         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 452 }
 453
 454 static unsigned int i965_gtt_total_entries(void)
 455 {
 456         int size;
 457         u32 pgetbl_ctl;
 458         u16 gmch_ctl;
 459
 460         pci_read_config_word(intel_private.bridge_dev,
 461                              I830_GMCH_CTRL, &gmch_ctl);
 462
 463         if (INTEL_GTT_GEN == 5) {
 464                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 465                 case G4x_GMCH_SIZE_1M:
 466                 case G4x_GMCH_SIZE_VT_1M:
 467                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 468                         break;
 469                 case G4x_GMCH_SIZE_VT_1_5M:
 470                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 471                         break;
 472                 case G4x_GMCH_SIZE_2M:
 473                 case G4x_GMCH_SIZE_VT_2M:
 474                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 475                         break;
 476                 }
 477         }
 478
 479         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 480
 481         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 482         case I965_PGETBL_SIZE_128KB:
 483                 size = KB(128);
 484                 break;
 485         case I965_PGETBL_SIZE_256KB:
 486                 size = KB(256);
 487                 break;
 488         case I965_PGETBL_SIZE_512KB:
 489                 size = KB(512);
 490                 break;
 491         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 492         case I965_PGETBL_SIZE_1MB:
 493                 size = KB(1024);
 494                 break;
 495         case I965_PGETBL_SIZE_2MB:
 496                 size = KB(2048);
 497                 break;
 498         case I965_PGETBL_SIZE_1_5MB:
 499                 size = KB(1024 + 512);
 500                 break;
 501         default:
 502                 dev_info(&intel_private.pcidev->dev,
 503                          "unknown page table size, assuming 512KB\n");
 504                 size = KB(512);
 505         }
 506
 507         return size/4;
 508 }
 509
 510 static unsigned int intel_gtt_total_entries(void)
 511 {
 512         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 513                 return i965_gtt_total_entries();
 514         else {
 515                 /* On previous hardware, the GTT size was just what was
 516                  * required to map the aperture.
 517                  */
 518                 return intel_private.gtt_mappable_entries;
 519         }
 520 }
 521
 522 static unsigned int intel_gtt_mappable_entries(void)
 523 {
 524         unsigned int aperture_size;
 525
 526         if (INTEL_GTT_GEN == 1) {
 527                 u32 smram_miscc;
 528
 529                 pci_read_config_dword(intel_private.bridge_dev,
 530                                       I810_SMRAM_MISCC, &smram_miscc);
 531
 532                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 533                                 == I810_GFX_MEM_WIN_32M)
 534                         aperture_size = MB(32);
 535                 else
 536                         aperture_size = MB(64);
 537         } else if (INTEL_GTT_GEN == 2) {
 538                 u16 gmch_ctrl;
 539
 540                 pci_read_config_word(intel_private.bridge_dev,
 541                                      I830_GMCH_CTRL, &gmch_ctrl);
 542
 543                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 544                         aperture_size = MB(64);
 545                 else
 546                         aperture_size = MB(128);
 547         } else {
 548                 /* 9xx supports large sizes, just look at the length */
 549                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 550         }
 551
 552         return aperture_size >> PAGE_SHIFT;
 553 }
 554
 555 static void intel_gtt_teardown_scratch_page(void)
 556 {
 557         set_pages_wb(intel_private.scratch_page, 1);
 558         pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
 559                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 560         put_page(intel_private.scratch_page);
 561         __free_page(intel_private.scratch_page);
 562 }
 563
 564 static void intel_gtt_cleanup(void)
 565 {
 566         intel_private.driver->cleanup();
 567
 568         iounmap(intel_private.gtt);
 569         iounmap(intel_private.registers);
 570
 571         intel_gtt_teardown_scratch_page();
 572 }
 573
 574 /* Certain Gen5 chipsets require require idling the GPU before
 575  * unmapping anything from the GTT when VT-d is enabled.
 576  */
 577 static inline int needs_ilk_vtd_wa(void)
 578 {
 579 #ifdef CONFIG_INTEL_IOMMU
 580         const unsigned short gpu_devid = intel_private.pcidev->device;
 581
 582         /* Query intel_iommu to see if we need the workaround. Presumably that
 583          * was loaded first.
 584          */
 585         if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
 586              gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
 587              intel_iommu_gfx_mapped)
 588                 return 1;
 589 #endif
 590         return 0;
 591 }
 592
 593 static bool intel_gtt_can_wc(void)
 594 {
 595         if (INTEL_GTT_GEN <= 2)
 596                 return false;
 597
 598         if (INTEL_GTT_GEN >= 6)
 599                 return false;
 600
 601         /* Reports of major corruption with ILK vt'd enabled */
 602         if (needs_ilk_vtd_wa())
 603                 return false;
 604
 605         return true;
 606 }
 607
 608 static int intel_gtt_init(void)
 609 {
 610         u32 gtt_map_size;
 611         int ret, bar;
 612
 613         ret = intel_private.driver->setup();
 614         if (ret != 0)
 615                 return ret;
 616
 617         intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
 618         intel_private.gtt_total_entries = intel_gtt_total_entries();
 619
 620         /* save the PGETBL reg for resume */
 621         intel_private.PGETBL_save =
 622                 readl(intel_private.registers+I810_PGETBL_CTL)
 623                         & ~I810_PGETBL_ENABLED;
 624         /* we only ever restore the register when enabling the PGTBL... */
 625         if (HAS_PGTBL_EN)
 626                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 627
 628         dev_info(&intel_private.bridge_dev->dev,
 629                         "detected gtt size: %dK total, %dK mappable\n",
 630                         intel_private.gtt_total_entries * 4,
 631                         intel_private.gtt_mappable_entries * 4);
 632
 633         gtt_map_size = intel_private.gtt_total_entries * 4;
 634
 635         intel_private.gtt = NULL;
 636         if (intel_gtt_can_wc())
 637                 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
 638                                                gtt_map_size);
 639         if (intel_private.gtt == NULL)
 640                 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
 641                                             gtt_map_size);
 642         if (intel_private.gtt == NULL) {
 643                 intel_private.driver->cleanup();
 644                 iounmap(intel_private.registers);
 645                 return -ENOMEM;
 646         }
 647
 648         global_cache_flush();   /* FIXME: ? */
 649
 650         intel_private.stolen_size = intel_gtt_stolen_size();
 651
 652         intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
 653
 654         ret = intel_gtt_setup_scratch_page();
 655         if (ret != 0) {
 656                 intel_gtt_cleanup();
 657                 return ret;
 658         }
 659
 660         if (INTEL_GTT_GEN <= 2)
 661                 bar = I810_GMADR_BAR;
 662         else
 663                 bar = I915_GMADR_BAR;
 664
 665         intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
 666         return 0;
 667 }
 668
 669 static int intel_fake_agp_fetch_size(void)
 670 {
 671         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 672         unsigned int aper_size;
 673         int i;
 674
 675         aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
 676
 677         for (i = 0; i < num_sizes; i++) {
 678                 if (aper_size == intel_fake_agp_sizes[i].size) {
 679                         agp_bridge->current_size =
 680                                 (void *) (intel_fake_agp_sizes + i);
 681                         return aper_size;
 682                 }
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void i830_cleanup(void)
 689 {
 690 }
 691
 692 /* The chipset_flush interface needs to get data that has already been
 693  * flushed out of the CPU all the way out to main memory, because the GPU
 694  * doesn't snoop those buffers.
 695  *
 696  * The 8xx series doesn't have the same lovely interface for flushing the
 697  * chipset write buffers that the later chips do. According to the 865
 698  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 699  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 700  * that it'll push whatever was in there out.  It appears to work.
 701  */
 702 static void i830_chipset_flush(void)
 703 {
 704         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 705
 706         /* Forcibly evict everything from the CPU write buffers.
 707          * clflush appears to be insufficient.
 708          */
 709         wbinvd_on_all_cpus();
 710
 711         /* Now we've only seen documents for this magic bit on 855GM,
 712          * we hope it exists for the other gen2 chipsets...
 713          *
 714          * Also works as advertised on my 845G.
 715          */
 716         writel(readl(intel_private.registers+I830_HIC) | (1<<31),
 717                intel_private.registers+I830_HIC);
 718
 719         while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
 720                 if (time_after(jiffies, timeout))
 721                         break;
 722
 723                 udelay(50);
 724         }
 725 }
 726
 727 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 728                              unsigned int flags)
 729 {
 730         u32 pte_flags = I810_PTE_VALID;
 731
 732         if (flags ==  AGP_USER_CACHED_MEMORY)
 733                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 734
 735         writel(addr | pte_flags, intel_private.gtt + entry);
 736 }
 737
 738 bool intel_enable_gtt(void)
 739 {
 740         u8 __iomem *reg;
 741
 742         if (INTEL_GTT_GEN == 2) {
 743                 u16 gmch_ctrl;
 744
 745                 pci_read_config_word(intel_private.bridge_dev,
 746                                      I830_GMCH_CTRL, &gmch_ctrl);
 747                 gmch_ctrl |= I830_GMCH_ENABLED;
 748                 pci_write_config_word(intel_private.bridge_dev,
 749                                       I830_GMCH_CTRL, gmch_ctrl);
 750
 751                 pci_read_config_word(intel_private.bridge_dev,
 752                                      I830_GMCH_CTRL, &gmch_ctrl);
 753                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 754                         dev_err(&intel_private.pcidev->dev,
 755                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 756                                 gmch_ctrl);
 757                         return false;
 758                 }
 759         }
 760
 761         /* On the resume path we may be adjusting the PGTBL value, so
 762          * be paranoid and flush all chipset write buffers...
 763          */
 764         if (INTEL_GTT_GEN >= 3)
 765                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 766
 767         reg = intel_private.registers+I810_PGETBL_CTL;
 768         writel(intel_private.PGETBL_save, reg);
 769         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 770                 dev_err(&intel_private.pcidev->dev,
 771                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 772                         readl(reg), intel_private.PGETBL_save);
 773                 return false;
 774         }
 775
 776         if (INTEL_GTT_GEN >= 3)
 777                 writel(0, intel_private.registers+GFX_FLSH_CNTL);
 778
 779         return true;
 780 }
 781 EXPORT_SYMBOL(intel_enable_gtt);
 782
 783 static int i830_setup(void)
 784 {
 785         phys_addr_t reg_addr;
 786
 787         reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 788
 789         intel_private.registers = ioremap(reg_addr, KB(64));
 790         if (!intel_private.registers)
 791                 return -ENOMEM;
 792
 793         intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 794
 795         return 0;
 796 }
 797
 798 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 799 {
 800         agp_bridge->gatt_table_real = NULL;
 801         agp_bridge->gatt_table = NULL;
 802         agp_bridge->gatt_bus_addr = 0;
 803
 804         return 0;
 805 }
 806
 807 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 808 {
 809         return 0;
 810 }
 811
 812 static int intel_fake_agp_configure(void)
 813 {
 814         if (!intel_enable_gtt())
 815             return -EIO;
 816
 817         intel_private.clear_fake_agp = true;
 818         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 819
 820         return 0;
 821 }
 822
 823 static bool i830_check_flags(unsigned int flags)
 824 {
 825         switch (flags) {
 826         case 0:
 827         case AGP_PHYS_MEMORY:
 828         case AGP_USER_CACHED_MEMORY:
 829         case AGP_USER_MEMORY:
 830                 return true;
 831         }
 832
 833         return false;
 834 }
 835
 836 void intel_gtt_insert_sg_entries(struct sg_table *st,
 837                                  unsigned int pg_start,
 838                                  unsigned int flags)
 839 {
 840         struct scatterlist *sg;
 841         unsigned int len, m;
 842         int i, j;
 843
 844         j = pg_start;
 845
 846         /* sg may merge pages, but we have to separate
 847          * per-page addr for GTT */
 848         for_each_sg(st->sgl, sg, st->nents, i) {
 849                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 850                 for (m = 0; m < len; m++) {
 851                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 852                         intel_private.driver->write_entry(addr, j, flags);
 853                         j++;
 854                 }
 855         }
 856         readl(intel_private.gtt+j-1);
 857 }
 858 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 859
 860 static void intel_gtt_insert_pages(unsigned int first_entry,
 861                                    unsigned int num_entries,
 862                                    struct page **pages,
 863                                    unsigned int flags)
 864 {
 865         int i, j;
 866
 867         for (i = 0, j = first_entry; i < num_entries; i++, j++) {
 868                 dma_addr_t addr = page_to_phys(pages[i]);
 869                 intel_private.driver->write_entry(addr,
 870                                                   j, flags);
 871         }
 872         readl(intel_private.gtt+j-1);
 873 }
 874
 875 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 876                                          off_t pg_start, int type)
 877 {
 878         int ret = -EINVAL;
 879
 880         if (intel_private.clear_fake_agp) {
 881                 int start = intel_private.stolen_size / PAGE_SIZE;
 882                 int end = intel_private.gtt_mappable_entries;
 883                 intel_gtt_clear_range(start, end - start);
 884                 intel_private.clear_fake_agp = false;
 885         }
 886
 887         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 888                 return i810_insert_dcache_entries(mem, pg_start, type);
 889
 890         if (mem->page_count == 0)
 891                 goto out;
 892
 893         if (pg_start + mem->page_count > intel_private.gtt_total_entries)
 894                 goto out_err;
 895
 896         if (type != mem->type)
 897                 goto out_err;
 898
 899         if (!intel_private.driver->check_flags(type))
 900                 goto out_err;
 901
 902         if (!mem->is_flushed)
 903                 global_cache_flush();
 904
 905         if (intel_private.needs_dmar) {
 906                 struct sg_table st;
 907
 908                 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
 909                 if (ret != 0)
 910                         return ret;
 911
 912                 intel_gtt_insert_sg_entries(&st, pg_start, type);
 913                 mem->sg_list = st.sgl;
 914                 mem->num_sg = st.nents;
 915         } else
 916                 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
 917                                        type);
 918
 919 out:
 920         ret = 0;
 921 out_err:
 922         mem->is_flushed = true;
 923         return ret;
 924 }
 925
 926 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
 927 {
 928         unsigned int i;
 929
 930         for (i = first_entry; i < (first_entry + num_entries); i++) {
 931                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
 932                                                   i, 0);
 933         }
 934         readl(intel_private.gtt+i-1);
 935 }
 936 EXPORT_SYMBOL(intel_gtt_clear_range);
 937
 938 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 939                                          off_t pg_start, int type)
 940 {
 941         if (mem->page_count == 0)
 942                 return 0;
 943
 944         intel_gtt_clear_range(pg_start, mem->page_count);
 945
 946         if (intel_private.needs_dmar) {
 947                 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
 948                 mem->sg_list = NULL;
 949                 mem->num_sg = 0;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 956                                                        int type)
 957 {
 958         struct agp_memory *new;
 959
 960         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
 961                 if (pg_count != intel_private.num_dcache_entries)
 962                         return NULL;
 963
 964                 new = agp_create_memory(1);
 965                 if (new == NULL)
 966                         return NULL;
 967
 968                 new->type = AGP_DCACHE_MEMORY;
 969                 new->page_count = pg_count;
 970                 new->num_scratch_pages = 0;
 971                 agp_free_page_array(new);
 972                 return new;
 973         }
 974         if (type == AGP_PHYS_MEMORY)
 975                 return alloc_agpphysmem_i8xx(pg_count, type);
 976         /* always return NULL for other allocation types for now */
 977         return NULL;
 978 }
 979
 980 static int intel_alloc_chipset_flush_resource(void)
 981 {
 982         int ret;
 983         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 984                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 985                                      pcibios_align_resource, intel_private.bridge_dev);
 986
 987         return ret;
 988 }
 989
 990 static void intel_i915_setup_chipset_flush(void)
 991 {
 992         int ret;
 993         u32 temp;
 994
 995         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
 996         if (!(temp & 0x1)) {
 997                 intel_alloc_chipset_flush_resource();
 998                 intel_private.resource_valid = 1;
 999                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1000         } else {
1001                 temp &= ~1;
1002
1003                 intel_private.resource_valid = 1;
1004                 intel_private.ifp_resource.start = temp;
1005                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1006                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1007                 /* some BIOSes reserve this area in a pnp some don't */
1008                 if (ret)
1009                         intel_private.resource_valid = 0;
1010         }
1011 }
1012
1013 static void intel_i965_g33_setup_chipset_flush(void)
1014 {
1015         u32 temp_hi, temp_lo;
1016         int ret;
1017
1018         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1019         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1020
1021         if (!(temp_lo & 0x1)) {
1022
1023                 intel_alloc_chipset_flush_resource();
1024
1025                 intel_private.resource_valid = 1;
1026                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1027                         upper_32_bits(intel_private.ifp_resource.start));
1028                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1029         } else {
1030                 u64 l64;
1031
1032                 temp_lo &= ~0x1;
1033                 l64 = ((u64)temp_hi << 32) | temp_lo;
1034
1035                 intel_private.resource_valid = 1;
1036                 intel_private.ifp_resource.start = l64;
1037                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1038                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1039                 /* some BIOSes reserve this area in a pnp some don't */
1040                 if (ret)
1041                         intel_private.resource_valid = 0;
1042         }
1043 }
1044
1045 static void intel_i9xx_setup_flush(void)
1046 {
1047         /* return if already configured */
1048         if (intel_private.ifp_resource.start)
1049                 return;
1050
1051         if (INTEL_GTT_GEN == 6)
1052                 return;
1053
1054         /* setup a resource for this object */
1055         intel_private.ifp_resource.name = "Intel Flush Page";
1056         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1057
1058         /* Setup chipset flush for 915 */
1059         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1060                 intel_i965_g33_setup_chipset_flush();
1061         } else {
1062                 intel_i915_setup_chipset_flush();
1063         }
1064
1065         if (intel_private.ifp_resource.start)
1066                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1067         if (!intel_private.i9xx_flush_page)
1068                 dev_err(&intel_private.pcidev->dev,
1069                         "can't ioremap flush page - no chipset flushing\n");
1070 }
1071
1072 static void i9xx_cleanup(void)
1073 {
1074         if (intel_private.i9xx_flush_page)
1075                 iounmap(intel_private.i9xx_flush_page);
1076         if (intel_private.resource_valid)
1077                 release_resource(&intel_private.ifp_resource);
1078         intel_private.ifp_resource.start = 0;
1079         intel_private.resource_valid = 0;
1080 }
1081
1082 static void i9xx_chipset_flush(void)
1083 {
1084         if (intel_private.i9xx_flush_page)
1085                 writel(1, intel_private.i9xx_flush_page);
1086 }
1087
1088 static void i965_write_entry(dma_addr_t addr,
1089                              unsigned int entry,
1090                              unsigned int flags)
1091 {
1092         u32 pte_flags;
1093
1094         pte_flags = I810_PTE_VALID;
1095         if (flags == AGP_USER_CACHED_MEMORY)
1096                 pte_flags |= I830_PTE_SYSTEM_CACHED;
1097
1098         /* Shift high bits down */
1099         addr |= (addr >> 28) & 0xf0;
1100         writel(addr | pte_flags, intel_private.gtt + entry);
1101 }
1102
1103 static int i9xx_setup(void)
1104 {
1105         phys_addr_t reg_addr;
1106         int size = KB(512);
1107
1108         reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1109
1110         intel_private.registers = ioremap(reg_addr, size);
1111         if (!intel_private.registers)
1112                 return -ENOMEM;
1113
1114         switch (INTEL_GTT_GEN) {
1115         case 3:
1116                 intel_private.gtt_phys_addr =
1117                         pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1118                 break;
1119         case 5:
1120                 intel_private.gtt_phys_addr = reg_addr + MB(2);
1121                 break;
1122         default:
1123                 intel_private.gtt_phys_addr = reg_addr + KB(512);
1124                 break;
1125         }
1126
1127         intel_i9xx_setup_flush();
1128
1129         return 0;
1130 }
1131
1132 static const struct agp_bridge_driver intel_fake_agp_driver = {
1133         .owner                  = THIS_MODULE,
1134         .size_type              = FIXED_APER_SIZE,
1135         .aperture_sizes         = intel_fake_agp_sizes,
1136         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1137         .configure              = intel_fake_agp_configure,
1138         .fetch_size             = intel_fake_agp_fetch_size,
1139         .cleanup                = intel_gtt_cleanup,
1140         .agp_enable             = intel_fake_agp_enable,
1141         .cache_flush            = global_cache_flush,
1142         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1143         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1144         .insert_memory          = intel_fake_agp_insert_entries,
1145         .remove_memory          = intel_fake_agp_remove_entries,
1146         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1147         .free_by_type           = intel_i810_free_by_type,
1148         .agp_alloc_page         = agp_generic_alloc_page,
1149         .agp_alloc_pages        = agp_generic_alloc_pages,
1150         .agp_destroy_page       = agp_generic_destroy_page,
1151         .agp_destroy_pages      = agp_generic_destroy_pages,
1152 };
1153
1154 static const struct intel_gtt_driver i81x_gtt_driver = {
1155         .gen = 1,
1156         .has_pgtbl_enable = 1,
1157         .dma_mask_size = 32,
1158         .setup = i810_setup,
1159         .cleanup = i810_cleanup,
1160         .check_flags = i830_check_flags,
1161         .write_entry = i810_write_entry,
1162 };
1163 static const struct intel_gtt_driver i8xx_gtt_driver = {
1164         .gen = 2,
1165         .has_pgtbl_enable = 1,
1166         .setup = i830_setup,
1167         .cleanup = i830_cleanup,
1168         .write_entry = i830_write_entry,
1169         .dma_mask_size = 32,
1170         .check_flags = i830_check_flags,
1171         .chipset_flush = i830_chipset_flush,
1172 };
1173 static const struct intel_gtt_driver i915_gtt_driver = {
1174         .gen = 3,
1175         .has_pgtbl_enable = 1,
1176         .setup = i9xx_setup,
1177         .cleanup = i9xx_cleanup,
1178         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1179         .write_entry = i830_write_entry,
1180         .dma_mask_size = 32,
1181         .check_flags = i830_check_flags,
1182         .chipset_flush = i9xx_chipset_flush,
1183 };
1184 static const struct intel_gtt_driver g33_gtt_driver = {
1185         .gen = 3,
1186         .is_g33 = 1,
1187         .setup = i9xx_setup,
1188         .cleanup = i9xx_cleanup,
1189         .write_entry = i965_write_entry,
1190         .dma_mask_size = 36,
1191         .check_flags = i830_check_flags,
1192         .chipset_flush = i9xx_chipset_flush,
1193 };
1194 static const struct intel_gtt_driver pineview_gtt_driver = {
1195         .gen = 3,
1196         .is_pineview = 1, .is_g33 = 1,
1197         .setup = i9xx_setup,
1198         .cleanup = i9xx_cleanup,
1199         .write_entry = i965_write_entry,
1200         .dma_mask_size = 36,
1201         .check_flags = i830_check_flags,
1202         .chipset_flush = i9xx_chipset_flush,
1203 };
1204 static const struct intel_gtt_driver i965_gtt_driver = {
1205         .gen = 4,
1206         .has_pgtbl_enable = 1,
1207         .setup = i9xx_setup,
1208         .cleanup = i9xx_cleanup,
1209         .write_entry = i965_write_entry,
1210         .dma_mask_size = 36,
1211         .check_flags = i830_check_flags,
1212         .chipset_flush = i9xx_chipset_flush,
1213 };
1214 static const struct intel_gtt_driver g4x_gtt_driver = {
1215         .gen = 5,
1216         .setup = i9xx_setup,
1217         .cleanup = i9xx_cleanup,
1218         .write_entry = i965_write_entry,
1219         .dma_mask_size = 36,
1220         .check_flags = i830_check_flags,
1221         .chipset_flush = i9xx_chipset_flush,
1222 };
1223 static const struct intel_gtt_driver ironlake_gtt_driver = {
1224         .gen = 5,
1225         .is_ironlake = 1,
1226         .setup = i9xx_setup,
1227         .cleanup = i9xx_cleanup,
1228         .write_entry = i965_write_entry,
1229         .dma_mask_size = 36,
1230         .check_flags = i830_check_flags,
1231         .chipset_flush = i9xx_chipset_flush,
1232 };
1233
1234 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1235  * driver and gmch_driver must be non-null, and find_gmch will determine
1236  * which one should be used if a gmch_chip_id is present.
1237  */
1238 static const struct intel_gtt_driver_description {
1239         unsigned int gmch_chip_id;
1240         char *name;
1241         const struct intel_gtt_driver *gtt_driver;
1242 } intel_gtt_chipsets[] = {
1243         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1244                 &i81x_gtt_driver},
1245         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1246                 &i81x_gtt_driver},
1247         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1248                 &i81x_gtt_driver},
1249         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1250                 &i81x_gtt_driver},
1251         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1252                 &i8xx_gtt_driver},
1253         { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1254                 &i8xx_gtt_driver},
1255         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1256                 &i8xx_gtt_driver},
1257         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1258                 &i8xx_gtt_driver},
1259         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1260                 &i8xx_gtt_driver},
1261         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1262                 &i915_gtt_driver },
1263         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1264                 &i915_gtt_driver },
1265         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1266                 &i915_gtt_driver },
1267         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1268                 &i915_gtt_driver },
1269         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1270                 &i915_gtt_driver },
1271         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1272                 &i915_gtt_driver },
1273         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1274                 &i965_gtt_driver },
1275         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1276                 &i965_gtt_driver },
1277         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1278                 &i965_gtt_driver },
1279         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1280                 &i965_gtt_driver },
1281         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1282                 &i965_gtt_driver },
1283         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1284                 &i965_gtt_driver },
1285         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1286                 &g33_gtt_driver },
1287         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1288                 &g33_gtt_driver },
1289         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1290                 &g33_gtt_driver },
1291         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1292                 &pineview_gtt_driver },
1293         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1294                 &pineview_gtt_driver },
1295         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1296                 &g4x_gtt_driver },
1297         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1298                 &g4x_gtt_driver },
1299         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1300                 &g4x_gtt_driver },
1301         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1302                 &g4x_gtt_driver },
1303         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1304                 &g4x_gtt_driver },
1305         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1306                 &g4x_gtt_driver },
1307         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1308                 &g4x_gtt_driver },
1309         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1310             "HD Graphics", &ironlake_gtt_driver },
1311         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1312             "HD Graphics", &ironlake_gtt_driver },
1313         { 0, NULL, NULL }
1314 };
1315
1316 static int find_gmch(u16 device)
1317 {
1318         struct pci_dev *gmch_device;
1319
1320         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1321         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1322                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1323                                              device, gmch_device);
1324         }
1325
1326         if (!gmch_device)
1327                 return 0;
1328
1329         intel_private.pcidev = gmch_device;
1330         return 1;
1331 }
1332
1333 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1334                      struct agp_bridge_data *bridge)
1335 {
1336         int i, mask;
1337
1338         /*
1339          * Can be called from the fake agp driver but also directly from
1340          * drm/i915.ko. Hence we need to check whether everything is set up
1341          * already.
1342          */
1343         if (intel_private.driver) {
1344                 intel_private.refcount++;
1345                 return 1;
1346         }
1347
1348         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1349                 if (gpu_pdev) {
1350                         if (gpu_pdev->device ==
1351                             intel_gtt_chipsets[i].gmch_chip_id) {
1352                                 intel_private.pcidev = pci_dev_get(gpu_pdev);
1353                                 intel_private.driver =
1354                                         intel_gtt_chipsets[i].gtt_driver;
1355
1356                                 break;
1357                         }
1358                 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1359                         intel_private.driver =
1360                                 intel_gtt_chipsets[i].gtt_driver;
1361                         break;
1362                 }
1363         }
1364
1365         if (!intel_private.driver)
1366                 return 0;
1367
1368         intel_private.refcount++;
1369
1370         if (bridge) {
1371                 bridge->driver = &intel_fake_agp_driver;
1372                 bridge->dev_private_data = &intel_private;
1373                 bridge->dev = bridge_pdev;
1374         }
1375
1376         intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1377
1378         dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1379
1380         mask = intel_private.driver->dma_mask_size;
1381         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1382                 dev_err(&intel_private.pcidev->dev,
1383                         "set gfx device dma mask %d-bit failed!\n", mask);
1384         else
1385                 pci_set_consistent_dma_mask(intel_private.pcidev,
1386                                             DMA_BIT_MASK(mask));
1387
1388         if (intel_gtt_init() != 0) {
1389                 intel_gmch_remove();
1390
1391                 return 0;
1392         }
1393
1394         return 1;
1395 }
1396 EXPORT_SYMBOL(intel_gmch_probe);
1397
1398 void intel_gtt_get(size_t *gtt_total, size_t *stolen_size,
1399                    phys_addr_t *mappable_base, unsigned long *mappable_end)
1400 {
1401         *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1402         *stolen_size = intel_private.stolen_size;
1403         *mappable_base = intel_private.gma_bus_addr;
1404         *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1405 }
1406 EXPORT_SYMBOL(intel_gtt_get);
1407
1408 void intel_gtt_chipset_flush(void)
1409 {
1410         if (intel_private.driver->chipset_flush)
1411                 intel_private.driver->chipset_flush();
1412 }
1413 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1414
1415 void intel_gmch_remove(void)
1416 {
1417         if (--intel_private.refcount)
1418                 return;
1419
1420         if (intel_private.pcidev)
1421                 pci_dev_put(intel_private.pcidev);
1422         if (intel_private.bridge_dev)
1423                 pci_dev_put(intel_private.bridge_dev);
1424         intel_private.driver = NULL;
1425 }
1426 EXPORT_SYMBOL(intel_gmch_remove);
1427
1428 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1429 MODULE_LICENSE("GPL and additional rights");