4 * The state-machine driver for an IPMI SMIC driver
6 * It started as a copy of Corey Minyard's driver for the KSC interface
7 * and the kernel patch "mmcdev-patch-245" by HP
9 * modified by: Hannes Schulz <schulz@schwaar.com>
13 * Corey Minyard's driver for the KSC interface has the following
15 * Copyright 2002 MontaVista Software Inc.
17 * the kernel patch "mmcdev-patch-245" by HP has the following
19 * (c) Copyright 2001 Grant Grundler (c) Copyright
20 * 2001 Hewlett-Packard Company
23 * This program is free software; you can redistribute it and/or modify it
24 * under the terms of the GNU General Public License as published by the
25 * Free Software Foundation; either version 2 of the License, or (at your
26 * option) any later version.
29 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
34 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
35 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
37 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
38 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * You should have received a copy of the GNU General Public License along
41 * with this program; if not, write to the Free Software Foundation, Inc.,
42 * 675 Mass Ave, Cambridge, MA 02139, USA. */
44 #include <linux/kernel.h> /* For printk. */
45 #include <linux/string.h>
46 #include <linux/module.h>
47 #include <linux/moduleparam.h>
48 #include <linux/ipmi_msgdefs.h> /* for completion codes */
49 #include "ipmi_si_sm.h"
51 /* smic_debug is a bit-field
52 * SMIC_DEBUG_ENABLE - turned on for now
53 * SMIC_DEBUG_MSG - commands and their responses
54 * SMIC_DEBUG_STATES - state machine
56 #define SMIC_DEBUG_STATES 4
57 #define SMIC_DEBUG_MSG 2
58 #define SMIC_DEBUG_ENABLE 1
60 static int smic_debug = 1;
61 module_param(smic_debug, int, 0644);
62 MODULE_PARM_DESC(smic_debug, "debug bitmask, 1=enable, 2=messages, 4=states");
78 #define MAX_SMIC_READ_SIZE 80
79 #define MAX_SMIC_WRITE_SIZE 80
80 #define SMIC_MAX_ERROR_RETRIES 3
82 /* Timeouts in microseconds. */
83 #define SMIC_RETRY_TIMEOUT 2000000
85 /* SMIC Flags Register Bits */
86 #define SMIC_RX_DATA_READY 0x80
87 #define SMIC_TX_DATA_READY 0x40
89 #define SMIC_EVM_DATA_AVAIL 0x08
90 #define SMIC_SMS_DATA_AVAIL 0x04
91 #define SMIC_FLAG_BSY 0x01
93 /* SMIC Error Codes */
94 #define EC_NO_ERROR 0x00
95 #define EC_ABORTED 0x01
96 #define EC_ILLEGAL_CONTROL 0x02
97 #define EC_NO_RESPONSE 0x03
98 #define EC_ILLEGAL_COMMAND 0x04
99 #define EC_BUFFER_FULL 0x05
103 enum smic_states state;
105 unsigned char write_data[MAX_SMIC_WRITE_SIZE];
108 int orig_write_count;
109 unsigned char read_data[MAX_SMIC_READ_SIZE];
112 unsigned int error_retries;
116 static unsigned int init_smic_data (struct si_sm_data *smic,
119 smic->state = SMIC_IDLE;
122 smic->write_count = 0;
123 smic->orig_write_count = 0;
125 smic->error_retries = 0;
127 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
129 /* We use 3 bytes of I/O. */
133 static int start_smic_transaction(struct si_sm_data *smic,
134 unsigned char *data, unsigned int size)
138 if ((size < 2) || (size > MAX_SMIC_WRITE_SIZE)) {
141 if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED)) {
144 if (smic_debug & SMIC_DEBUG_MSG) {
145 printk(KERN_INFO "start_smic_transaction -");
146 for (i = 0; i < size; i ++) {
147 printk (" %02x", (unsigned char) (data [i]));
151 smic->error_retries = 0;
152 memcpy(smic->write_data, data, size);
153 smic->write_count = size;
154 smic->orig_write_count = size;
157 smic->state = SMIC_START_OP;
158 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
162 static int smic_get_result(struct si_sm_data *smic,
163 unsigned char *data, unsigned int length)
167 if (smic_debug & SMIC_DEBUG_MSG) {
168 printk (KERN_INFO "smic_get result -");
169 for (i = 0; i < smic->read_pos; i ++) {
170 printk (" %02x", (smic->read_data [i]));
174 if (length < smic->read_pos) {
175 smic->read_pos = length;
178 memcpy(data, smic->read_data, smic->read_pos);
180 if ((length >= 3) && (smic->read_pos < 3)) {
181 data[2] = IPMI_ERR_UNSPECIFIED;
184 if (smic->truncated) {
185 data[2] = IPMI_ERR_MSG_TRUNCATED;
188 return smic->read_pos;
191 static inline unsigned char read_smic_flags(struct si_sm_data *smic)
193 return smic->io->inputb(smic->io, 2);
196 static inline unsigned char read_smic_status(struct si_sm_data *smic)
198 return smic->io->inputb(smic->io, 1);
201 static inline unsigned char read_smic_data(struct si_sm_data *smic)
203 return smic->io->inputb(smic->io, 0);
206 static inline void write_smic_flags(struct si_sm_data *smic,
209 smic->io->outputb(smic->io, 2, flags);
212 static inline void write_smic_control(struct si_sm_data *smic,
213 unsigned char control)
215 smic->io->outputb(smic->io, 1, control);
218 static inline void write_si_sm_data (struct si_sm_data *smic,
221 smic->io->outputb(smic->io, 0, data);
224 static inline void start_error_recovery(struct si_sm_data *smic, char *reason)
226 (smic->error_retries)++;
227 if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) {
228 if (smic_debug & SMIC_DEBUG_ENABLE) {
230 "ipmi_smic_drv: smic hosed: %s\n", reason);
232 smic->state = SMIC_HOSED;
234 smic->write_count = smic->orig_write_count;
237 smic->state = SMIC_START_OP;
238 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
242 static inline void write_next_byte(struct si_sm_data *smic)
244 write_si_sm_data(smic, smic->write_data[smic->write_pos]);
246 (smic->write_count)--;
249 static inline void read_next_byte (struct si_sm_data *smic)
251 if (smic->read_pos >= MAX_SMIC_READ_SIZE) {
252 read_smic_data (smic);
255 smic->read_data[smic->read_pos] = read_smic_data(smic);
260 /* SMIC Control/Status Code Components */
261 #define SMIC_GET_STATUS 0x00 /* Control form's name */
262 #define SMIC_READY 0x00 /* Status form's name */
263 #define SMIC_WR_START 0x01 /* Unified Control/Status names... */
264 #define SMIC_WR_NEXT 0x02
265 #define SMIC_WR_END 0x03
266 #define SMIC_RD_START 0x04
267 #define SMIC_RD_NEXT 0x05
268 #define SMIC_RD_END 0x06
269 #define SMIC_CODE_MASK 0x0f
271 #define SMIC_CONTROL 0x00
272 #define SMIC_STATUS 0x80
273 #define SMIC_CS_MASK 0x80
275 #define SMIC_SMS 0x40
276 #define SMIC_SMM 0x60
277 #define SMIC_STREAM_MASK 0x60
279 /* SMIC Control Codes */
280 #define SMIC_CC_SMS_GET_STATUS (SMIC_CONTROL|SMIC_SMS|SMIC_GET_STATUS)
281 #define SMIC_CC_SMS_WR_START (SMIC_CONTROL|SMIC_SMS|SMIC_WR_START)
282 #define SMIC_CC_SMS_WR_NEXT (SMIC_CONTROL|SMIC_SMS|SMIC_WR_NEXT)
283 #define SMIC_CC_SMS_WR_END (SMIC_CONTROL|SMIC_SMS|SMIC_WR_END)
284 #define SMIC_CC_SMS_RD_START (SMIC_CONTROL|SMIC_SMS|SMIC_RD_START)
285 #define SMIC_CC_SMS_RD_NEXT (SMIC_CONTROL|SMIC_SMS|SMIC_RD_NEXT)
286 #define SMIC_CC_SMS_RD_END (SMIC_CONTROL|SMIC_SMS|SMIC_RD_END)
288 #define SMIC_CC_SMM_GET_STATUS (SMIC_CONTROL|SMIC_SMM|SMIC_GET_STATUS)
289 #define SMIC_CC_SMM_WR_START (SMIC_CONTROL|SMIC_SMM|SMIC_WR_START)
290 #define SMIC_CC_SMM_WR_NEXT (SMIC_CONTROL|SMIC_SMM|SMIC_WR_NEXT)
291 #define SMIC_CC_SMM_WR_END (SMIC_CONTROL|SMIC_SMM|SMIC_WR_END)
292 #define SMIC_CC_SMM_RD_START (SMIC_CONTROL|SMIC_SMM|SMIC_RD_START)
293 #define SMIC_CC_SMM_RD_NEXT (SMIC_CONTROL|SMIC_SMM|SMIC_RD_NEXT)
294 #define SMIC_CC_SMM_RD_END (SMIC_CONTROL|SMIC_SMM|SMIC_RD_END)
296 /* SMIC Status Codes */
297 #define SMIC_SC_SMS_READY (SMIC_STATUS|SMIC_SMS|SMIC_READY)
298 #define SMIC_SC_SMS_WR_START (SMIC_STATUS|SMIC_SMS|SMIC_WR_START)
299 #define SMIC_SC_SMS_WR_NEXT (SMIC_STATUS|SMIC_SMS|SMIC_WR_NEXT)
300 #define SMIC_SC_SMS_WR_END (SMIC_STATUS|SMIC_SMS|SMIC_WR_END)
301 #define SMIC_SC_SMS_RD_START (SMIC_STATUS|SMIC_SMS|SMIC_RD_START)
302 #define SMIC_SC_SMS_RD_NEXT (SMIC_STATUS|SMIC_SMS|SMIC_RD_NEXT)
303 #define SMIC_SC_SMS_RD_END (SMIC_STATUS|SMIC_SMS|SMIC_RD_END)
305 #define SMIC_SC_SMM_READY (SMIC_STATUS|SMIC_SMM|SMIC_READY)
306 #define SMIC_SC_SMM_WR_START (SMIC_STATUS|SMIC_SMM|SMIC_WR_START)
307 #define SMIC_SC_SMM_WR_NEXT (SMIC_STATUS|SMIC_SMM|SMIC_WR_NEXT)
308 #define SMIC_SC_SMM_WR_END (SMIC_STATUS|SMIC_SMM|SMIC_WR_END)
309 #define SMIC_SC_SMM_RD_START (SMIC_STATUS|SMIC_SMM|SMIC_RD_START)
310 #define SMIC_SC_SMM_RD_NEXT (SMIC_STATUS|SMIC_SMM|SMIC_RD_NEXT)
311 #define SMIC_SC_SMM_RD_END (SMIC_STATUS|SMIC_SMM|SMIC_RD_END)
313 /* these are the control/status codes we actually use
314 SMIC_CC_SMS_GET_STATUS 0x40
315 SMIC_CC_SMS_WR_START 0x41
316 SMIC_CC_SMS_WR_NEXT 0x42
317 SMIC_CC_SMS_WR_END 0x43
318 SMIC_CC_SMS_RD_START 0x44
319 SMIC_CC_SMS_RD_NEXT 0x45
320 SMIC_CC_SMS_RD_END 0x46
322 SMIC_SC_SMS_READY 0xC0
323 SMIC_SC_SMS_WR_START 0xC1
324 SMIC_SC_SMS_WR_NEXT 0xC2
325 SMIC_SC_SMS_WR_END 0xC3
326 SMIC_SC_SMS_RD_START 0xC4
327 SMIC_SC_SMS_RD_NEXT 0xC5
328 SMIC_SC_SMS_RD_END 0xC6
331 static enum si_sm_result smic_event (struct si_sm_data *smic, long time)
333 unsigned char status;
337 if (smic->state == SMIC_HOSED) {
338 init_smic_data(smic, smic->io);
341 if (smic->state != SMIC_IDLE) {
342 if (smic_debug & SMIC_DEBUG_STATES) {
344 "smic_event - smic->smic_timeout = %ld,"
346 smic->smic_timeout, time);
348 /* FIXME: smic_event is sometimes called with time > SMIC_RETRY_TIMEOUT */
349 if (time < SMIC_RETRY_TIMEOUT) {
350 smic->smic_timeout -= time;
351 if (smic->smic_timeout < 0) {
352 start_error_recovery(smic, "smic timed out.");
353 return SI_SM_CALL_WITH_DELAY;
357 flags = read_smic_flags(smic);
358 if (flags & SMIC_FLAG_BSY)
359 return SI_SM_CALL_WITH_DELAY;
361 status = read_smic_status (smic);
362 if (smic_debug & SMIC_DEBUG_STATES)
364 "smic_event - state = %d, flags = 0x%02x,"
365 " status = 0x%02x\n",
366 smic->state, flags, status);
368 switch (smic->state) {
370 /* in IDLE we check for available messages */
371 if (flags & (SMIC_SMI |
372 SMIC_EVM_DATA_AVAIL | SMIC_SMS_DATA_AVAIL))
379 /* sanity check whether smic is really idle */
380 write_smic_control(smic, SMIC_CC_SMS_GET_STATUS);
381 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
382 smic->state = SMIC_OP_OK;
386 if (status != SMIC_SC_SMS_READY) {
387 /* this should not happen */
388 start_error_recovery(smic,
389 "state = SMIC_OP_OK,"
390 " status != SMIC_SC_SMS_READY");
391 return SI_SM_CALL_WITH_DELAY;
393 /* OK so far; smic is idle let us start ... */
394 write_smic_control(smic, SMIC_CC_SMS_WR_START);
395 write_next_byte(smic);
396 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
397 smic->state = SMIC_WRITE_START;
400 case SMIC_WRITE_START:
401 if (status != SMIC_SC_SMS_WR_START) {
402 start_error_recovery(smic,
403 "state = SMIC_WRITE_START, "
404 "status != SMIC_SC_SMS_WR_START");
405 return SI_SM_CALL_WITH_DELAY;
407 /* we must not issue WR_(NEXT|END) unless
408 TX_DATA_READY is set */
409 if (flags & SMIC_TX_DATA_READY) {
410 if (smic->write_count == 1) {
412 write_smic_control(smic, SMIC_CC_SMS_WR_END);
413 smic->state = SMIC_WRITE_END;
415 write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
416 smic->state = SMIC_WRITE_NEXT;
418 write_next_byte(smic);
419 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
422 return SI_SM_CALL_WITH_DELAY;
426 case SMIC_WRITE_NEXT:
427 if (status != SMIC_SC_SMS_WR_NEXT) {
428 start_error_recovery(smic,
429 "state = SMIC_WRITE_NEXT, "
430 "status != SMIC_SC_SMS_WR_NEXT");
431 return SI_SM_CALL_WITH_DELAY;
433 /* this is the same code as in SMIC_WRITE_START */
434 if (flags & SMIC_TX_DATA_READY) {
435 if (smic->write_count == 1) {
436 write_smic_control(smic, SMIC_CC_SMS_WR_END);
437 smic->state = SMIC_WRITE_END;
440 write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
441 smic->state = SMIC_WRITE_NEXT;
443 write_next_byte(smic);
444 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
447 return SI_SM_CALL_WITH_DELAY;
452 if (status != SMIC_SC_SMS_WR_END) {
453 start_error_recovery (smic,
454 "state = SMIC_WRITE_END, "
455 "status != SMIC_SC_SMS_WR_END");
456 return SI_SM_CALL_WITH_DELAY;
458 /* data register holds an error code */
459 data = read_smic_data(smic);
461 if (smic_debug & SMIC_DEBUG_ENABLE) {
463 "SMIC_WRITE_END: data = %02x\n", data);
465 start_error_recovery(smic,
466 "state = SMIC_WRITE_END, "
468 return SI_SM_CALL_WITH_DELAY;
470 smic->state = SMIC_WRITE2READ;
474 case SMIC_WRITE2READ:
475 /* we must wait for RX_DATA_READY to be set before we
477 if (flags & SMIC_RX_DATA_READY) {
478 write_smic_control(smic, SMIC_CC_SMS_RD_START);
479 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
480 smic->state = SMIC_READ_START;
482 return SI_SM_CALL_WITH_DELAY;
486 case SMIC_READ_START:
487 if (status != SMIC_SC_SMS_RD_START) {
488 start_error_recovery(smic,
489 "state = SMIC_READ_START, "
490 "status != SMIC_SC_SMS_RD_START");
491 return SI_SM_CALL_WITH_DELAY;
493 if (flags & SMIC_RX_DATA_READY) {
494 read_next_byte(smic);
495 write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
496 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
497 smic->state = SMIC_READ_NEXT;
499 return SI_SM_CALL_WITH_DELAY;
505 /* smic tells us that this is the last byte to be read
507 case SMIC_SC_SMS_RD_END:
508 read_next_byte(smic);
509 write_smic_control(smic, SMIC_CC_SMS_RD_END);
510 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
511 smic->state = SMIC_READ_END;
513 case SMIC_SC_SMS_RD_NEXT:
514 if (flags & SMIC_RX_DATA_READY) {
515 read_next_byte(smic);
516 write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
517 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
518 smic->state = SMIC_READ_NEXT;
520 return SI_SM_CALL_WITH_DELAY;
524 start_error_recovery(
526 "state = SMIC_READ_NEXT, "
527 "status != SMIC_SC_SMS_RD_(NEXT|END)");
528 return SI_SM_CALL_WITH_DELAY;
533 if (status != SMIC_SC_SMS_READY) {
534 start_error_recovery(smic,
535 "state = SMIC_READ_END, "
536 "status != SMIC_SC_SMS_READY");
537 return SI_SM_CALL_WITH_DELAY;
539 data = read_smic_data(smic);
540 /* data register holds an error code */
542 if (smic_debug & SMIC_DEBUG_ENABLE) {
544 "SMIC_READ_END: data = %02x\n", data);
546 start_error_recovery(smic,
547 "state = SMIC_READ_END, "
549 return SI_SM_CALL_WITH_DELAY;
551 smic->state = SMIC_IDLE;
552 return SI_SM_TRANSACTION_COMPLETE;
556 init_smic_data(smic, smic->io);
560 if (smic_debug & SMIC_DEBUG_ENABLE) {
561 printk(KERN_WARNING "smic->state = %d\n", smic->state);
562 start_error_recovery(smic, "state = UNKNOWN");
563 return SI_SM_CALL_WITH_DELAY;
566 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
567 return SI_SM_CALL_WITHOUT_DELAY;
570 static int smic_detect(struct si_sm_data *smic)
572 /* It's impossible for the SMIC fnags register to be all 1's,
573 (assuming a properly functioning, self-initialized BMC)
574 but that's what you get from reading a bogus address, so we
576 if (read_smic_flags(smic) == 0xff)
582 static void smic_cleanup(struct si_sm_data *kcs)
586 static int smic_size(void)
588 return sizeof(struct si_sm_data);
591 struct si_sm_handlers smic_smi_handlers =
593 .init_data = init_smic_data,
594 .start_transaction = start_smic_transaction,
595 .get_result = smic_get_result,
597 .detect = smic_detect,
598 .cleanup = smic_cleanup,