2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Adjustable divider clock implementation
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
22 * DOC: basic adjustable divider clock that cannot gate
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = parent->rate / divisor
28 * parent - fixed parent. No clk_set_parent support
31 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
33 #define div_mask(d) ((1 << ((d)->width)) - 1)
35 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
37 unsigned int maxdiv = 0;
38 const struct clk_div_table *clkt;
40 for (clkt = table; clkt->div; clkt++)
41 if (clkt->div > maxdiv)
46 static unsigned int _get_maxdiv(struct clk_divider *divider)
48 if (divider->flags & CLK_DIVIDER_ONE_BASED)
49 return div_mask(divider);
50 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
51 return 1 << div_mask(divider);
53 return _get_table_maxdiv(divider->table);
54 return div_mask(divider) + 1;
57 static unsigned int _get_table_div(const struct clk_div_table *table,
60 const struct clk_div_table *clkt;
62 for (clkt = table; clkt->div; clkt++)
68 static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
70 if (divider->flags & CLK_DIVIDER_ONE_BASED)
72 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
75 return _get_table_div(divider->table, val);
79 static unsigned int _get_table_val(const struct clk_div_table *table,
82 const struct clk_div_table *clkt;
84 for (clkt = table; clkt->div; clkt++)
90 static unsigned int _get_val(struct clk_divider *divider, u8 div)
92 if (divider->flags & CLK_DIVIDER_ONE_BASED)
94 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
97 return _get_table_val(divider->table, div);
101 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
102 unsigned long parent_rate)
104 struct clk_divider *divider = to_clk_divider(hw);
105 unsigned int div, val;
107 val = readl(divider->reg) >> divider->shift;
108 val &= div_mask(divider);
110 div = _get_div(divider, val);
112 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
113 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
114 __clk_get_name(hw->clk));
118 return parent_rate / div;
122 * The reverse of DIV_ROUND_UP: The maximum number which
125 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
127 static bool _is_valid_table_div(const struct clk_div_table *table,
130 const struct clk_div_table *clkt;
132 for (clkt = table; clkt->div; clkt++)
133 if (clkt->div == div)
138 static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
140 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
141 return is_power_of_2(div);
143 return _is_valid_table_div(divider->table, div);
147 static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
148 unsigned long *best_parent_rate)
150 struct clk_divider *divider = to_clk_divider(hw);
152 unsigned long parent_rate, best = 0, now, maxdiv;
157 maxdiv = _get_maxdiv(divider);
159 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
160 parent_rate = *best_parent_rate;
161 bestdiv = DIV_ROUND_UP(parent_rate, rate);
162 bestdiv = bestdiv == 0 ? 1 : bestdiv;
163 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
168 * The maximum divider we can use without overflowing
169 * unsigned long in rate * i below
171 maxdiv = min(ULONG_MAX / rate, maxdiv);
173 for (i = 1; i <= maxdiv; i++) {
174 if (!_is_valid_div(divider, i))
176 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
177 MULT_ROUND_UP(rate, i));
178 now = parent_rate / i;
179 if (now <= rate && now > best) {
182 *best_parent_rate = parent_rate;
187 bestdiv = _get_maxdiv(divider);
188 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
194 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
195 unsigned long *prate)
198 div = clk_divider_bestdiv(hw, rate, prate);
203 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
204 unsigned long parent_rate)
206 struct clk_divider *divider = to_clk_divider(hw);
207 unsigned int div, value;
208 unsigned long flags = 0;
211 div = parent_rate / rate;
212 value = _get_val(divider, div);
214 if (value > div_mask(divider))
215 value = div_mask(divider);
218 spin_lock_irqsave(divider->lock, flags);
220 val = readl(divider->reg);
221 val &= ~(div_mask(divider) << divider->shift);
222 val |= value << divider->shift;
223 writel(val, divider->reg);
226 spin_unlock_irqrestore(divider->lock, flags);
231 const struct clk_ops clk_divider_ops = {
232 .recalc_rate = clk_divider_recalc_rate,
233 .round_rate = clk_divider_round_rate,
234 .set_rate = clk_divider_set_rate,
236 EXPORT_SYMBOL_GPL(clk_divider_ops);
238 static struct clk *_register_divider(struct device *dev, const char *name,
239 const char *parent_name, unsigned long flags,
240 void __iomem *reg, u8 shift, u8 width,
241 u8 clk_divider_flags, const struct clk_div_table *table,
244 struct clk_divider *div;
246 struct clk_init_data init;
248 /* allocate the divider */
249 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
251 pr_err("%s: could not allocate divider clk\n", __func__);
252 return ERR_PTR(-ENOMEM);
256 init.ops = &clk_divider_ops;
257 init.flags = flags | CLK_IS_BASIC;
258 init.parent_names = (parent_name ? &parent_name: NULL);
259 init.num_parents = (parent_name ? 1 : 0);
261 /* struct clk_divider assignments */
265 div->flags = clk_divider_flags;
267 div->hw.init = &init;
270 /* register the clock */
271 clk = clk_register(dev, &div->hw);
280 * clk_register_divider - register a divider clock with the clock framework
281 * @dev: device registering this clock
282 * @name: name of this clock
283 * @parent_name: name of clock's parent
284 * @flags: framework-specific flags
285 * @reg: register address to adjust divider
286 * @shift: number of bits to shift the bitfield
287 * @width: width of the bitfield
288 * @clk_divider_flags: divider-specific flags for this clock
289 * @lock: shared register lock for this clock
291 struct clk *clk_register_divider(struct device *dev, const char *name,
292 const char *parent_name, unsigned long flags,
293 void __iomem *reg, u8 shift, u8 width,
294 u8 clk_divider_flags, spinlock_t *lock)
296 return _register_divider(dev, name, parent_name, flags, reg, shift,
297 width, clk_divider_flags, NULL, lock);
301 * clk_register_divider_table - register a table based divider clock with
302 * the clock framework
303 * @dev: device registering this clock
304 * @name: name of this clock
305 * @parent_name: name of clock's parent
306 * @flags: framework-specific flags
307 * @reg: register address to adjust divider
308 * @shift: number of bits to shift the bitfield
309 * @width: width of the bitfield
310 * @clk_divider_flags: divider-specific flags for this clock
311 * @table: array of divider/value pairs ending with a div set to 0
312 * @lock: shared register lock for this clock
314 struct clk *clk_register_divider_table(struct device *dev, const char *name,
315 const char *parent_name, unsigned long flags,
316 void __iomem *reg, u8 shift, u8 width,
317 u8 clk_divider_flags, const struct clk_div_table *table,
320 return _register_divider(dev, name, parent_name, flags, reg, shift,
321 width, clk_divider_flags, table, lock);