2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Adjustable divider clock implementation
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
22 * DOC: basic adjustable divider clock that cannot gate
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
28 * parent - fixed parent. No clk_set_parent support
31 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
33 #define div_mask(d) ((1 << ((d)->width)) - 1)
35 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
37 unsigned int maxdiv = 0;
38 const struct clk_div_table *clkt;
40 for (clkt = table; clkt->div; clkt++)
41 if (clkt->div > maxdiv)
46 static unsigned int _get_table_mindiv(const struct clk_div_table *table)
48 unsigned int mindiv = UINT_MAX;
49 const struct clk_div_table *clkt;
51 for (clkt = table; clkt->div; clkt++)
52 if (clkt->div < mindiv)
57 static unsigned int _get_maxdiv(struct clk_divider *divider)
59 if (divider->flags & CLK_DIVIDER_ONE_BASED)
60 return div_mask(divider);
61 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
62 return 1 << div_mask(divider);
64 return _get_table_maxdiv(divider->table);
65 return div_mask(divider) + 1;
68 static unsigned int _get_table_div(const struct clk_div_table *table,
71 const struct clk_div_table *clkt;
73 for (clkt = table; clkt->div; clkt++)
79 static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
81 if (divider->flags & CLK_DIVIDER_ONE_BASED)
83 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
86 return _get_table_div(divider->table, val);
90 static unsigned int _get_table_val(const struct clk_div_table *table,
93 const struct clk_div_table *clkt;
95 for (clkt = table; clkt->div; clkt++)
101 static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
103 if (divider->flags & CLK_DIVIDER_ONE_BASED)
105 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
108 return _get_table_val(divider->table, div);
112 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
113 unsigned long parent_rate)
115 struct clk_divider *divider = to_clk_divider(hw);
116 unsigned int div, val;
118 val = clk_readl(divider->reg) >> divider->shift;
119 val &= div_mask(divider);
121 div = _get_div(divider, val);
123 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
124 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
125 __clk_get_name(hw->clk));
129 return DIV_ROUND_UP(parent_rate, div);
133 * The reverse of DIV_ROUND_UP: The maximum number which
136 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
138 static bool _is_valid_table_div(const struct clk_div_table *table,
141 const struct clk_div_table *clkt;
143 for (clkt = table; clkt->div; clkt++)
144 if (clkt->div == div)
149 static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
151 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
152 return is_power_of_2(div);
154 return _is_valid_table_div(divider->table, div);
158 static int _round_up_table(const struct clk_div_table *table, int div)
160 const struct clk_div_table *clkt;
163 for (clkt = table; clkt->div; clkt++) {
164 if (clkt->div == div)
166 else if (clkt->div < div)
169 if ((clkt->div - div) < (up - div))
176 static int _round_down_table(const struct clk_div_table *table, int div)
178 const struct clk_div_table *clkt;
179 int down = _get_table_mindiv(table);
181 for (clkt = table; clkt->div; clkt++) {
182 if (clkt->div == div)
184 else if (clkt->div > div)
187 if ((div - clkt->div) < (div - down))
194 static int _div_round_up(struct clk_divider *divider,
195 unsigned long parent_rate, unsigned long rate)
197 int div = DIV_ROUND_UP(parent_rate, rate);
199 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
200 div = __roundup_pow_of_two(div);
202 div = _round_up_table(divider->table, div);
207 static int _div_round_closest(struct clk_divider *divider,
208 unsigned long parent_rate, unsigned long rate)
212 up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
214 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) {
215 up = __roundup_pow_of_two(div);
216 down = __rounddown_pow_of_two(div);
217 } else if (divider->table) {
218 up = _round_up_table(divider->table, div);
219 down = _round_down_table(divider->table, div);
222 return (up - div) <= (div - down) ? up : down;
225 static int _div_round(struct clk_divider *divider, unsigned long parent_rate,
228 if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
229 return _div_round_closest(divider, parent_rate, rate);
231 return _div_round_up(divider, parent_rate, rate);
234 static bool _is_best_div(struct clk_divider *divider,
235 unsigned long rate, unsigned long now, unsigned long best)
237 if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
238 return abs(rate - now) < abs(rate - best);
240 return now <= rate && now > best;
243 static int _next_div(struct clk_divider *divider, int div)
247 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
248 return __roundup_pow_of_two(div);
250 return _round_up_table(divider->table, div);
255 static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
256 unsigned long *best_parent_rate)
258 struct clk_divider *divider = to_clk_divider(hw);
260 unsigned long parent_rate, best = 0, now, maxdiv;
261 unsigned long parent_rate_saved = *best_parent_rate;
266 maxdiv = _get_maxdiv(divider);
268 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
269 parent_rate = *best_parent_rate;
270 bestdiv = _div_round(divider, parent_rate, rate);
271 bestdiv = bestdiv == 0 ? 1 : bestdiv;
272 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
277 * The maximum divider we can use without overflowing
278 * unsigned long in rate * i below
280 maxdiv = min(ULONG_MAX / rate, maxdiv);
282 for (i = 1; i <= maxdiv; i = _next_div(divider, i)) {
283 if (!_is_valid_div(divider, i))
285 if (rate * i == parent_rate_saved) {
287 * It's the most ideal case if the requested rate can be
288 * divided from parent clock without needing to change
289 * parent rate, so return the divider immediately.
291 *best_parent_rate = parent_rate_saved;
294 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
295 MULT_ROUND_UP(rate, i));
296 now = DIV_ROUND_UP(parent_rate, i);
297 if (_is_best_div(divider, rate, now, best)) {
300 *best_parent_rate = parent_rate;
305 bestdiv = _get_maxdiv(divider);
306 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
312 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
313 unsigned long *prate)
316 div = clk_divider_bestdiv(hw, rate, prate);
318 return DIV_ROUND_UP(*prate, div);
321 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
322 unsigned long parent_rate)
324 struct clk_divider *divider = to_clk_divider(hw);
325 unsigned int div, value;
326 unsigned long flags = 0;
329 div = DIV_ROUND_UP(parent_rate, rate);
331 if (!_is_valid_div(divider, div))
334 value = _get_val(divider, div);
336 if (value > div_mask(divider))
337 value = div_mask(divider);
340 spin_lock_irqsave(divider->lock, flags);
342 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
343 val = div_mask(divider) << (divider->shift + 16);
345 val = clk_readl(divider->reg);
346 val &= ~(div_mask(divider) << divider->shift);
348 val |= value << divider->shift;
349 clk_writel(val, divider->reg);
352 spin_unlock_irqrestore(divider->lock, flags);
357 const struct clk_ops clk_divider_ops = {
358 .recalc_rate = clk_divider_recalc_rate,
359 .round_rate = clk_divider_round_rate,
360 .set_rate = clk_divider_set_rate,
362 EXPORT_SYMBOL_GPL(clk_divider_ops);
364 const struct clk_ops clk_divider_ro_ops = {
365 .recalc_rate = clk_divider_recalc_rate,
367 EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
369 static struct clk *_register_divider(struct device *dev, const char *name,
370 const char *parent_name, unsigned long flags,
371 void __iomem *reg, u8 shift, u8 width,
372 u8 clk_divider_flags, const struct clk_div_table *table,
375 struct clk_divider *div;
377 struct clk_init_data init;
379 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
380 if (width + shift > 16) {
381 pr_warn("divider value exceeds LOWORD field\n");
382 return ERR_PTR(-EINVAL);
386 /* allocate the divider */
387 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
389 pr_err("%s: could not allocate divider clk\n", __func__);
390 return ERR_PTR(-ENOMEM);
394 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
395 init.ops = &clk_divider_ro_ops;
397 init.ops = &clk_divider_ops;
398 init.flags = flags | CLK_IS_BASIC;
399 init.parent_names = (parent_name ? &parent_name: NULL);
400 init.num_parents = (parent_name ? 1 : 0);
402 /* struct clk_divider assignments */
406 div->flags = clk_divider_flags;
408 div->hw.init = &init;
411 /* register the clock */
412 clk = clk_register(dev, &div->hw);
421 * clk_register_divider - register a divider clock with the clock framework
422 * @dev: device registering this clock
423 * @name: name of this clock
424 * @parent_name: name of clock's parent
425 * @flags: framework-specific flags
426 * @reg: register address to adjust divider
427 * @shift: number of bits to shift the bitfield
428 * @width: width of the bitfield
429 * @clk_divider_flags: divider-specific flags for this clock
430 * @lock: shared register lock for this clock
432 struct clk *clk_register_divider(struct device *dev, const char *name,
433 const char *parent_name, unsigned long flags,
434 void __iomem *reg, u8 shift, u8 width,
435 u8 clk_divider_flags, spinlock_t *lock)
437 return _register_divider(dev, name, parent_name, flags, reg, shift,
438 width, clk_divider_flags, NULL, lock);
440 EXPORT_SYMBOL_GPL(clk_register_divider);
443 * clk_register_divider_table - register a table based divider clock with
444 * the clock framework
445 * @dev: device registering this clock
446 * @name: name of this clock
447 * @parent_name: name of clock's parent
448 * @flags: framework-specific flags
449 * @reg: register address to adjust divider
450 * @shift: number of bits to shift the bitfield
451 * @width: width of the bitfield
452 * @clk_divider_flags: divider-specific flags for this clock
453 * @table: array of divider/value pairs ending with a div set to 0
454 * @lock: shared register lock for this clock
456 struct clk *clk_register_divider_table(struct device *dev, const char *name,
457 const char *parent_name, unsigned long flags,
458 void __iomem *reg, u8 shift, u8 width,
459 u8 clk_divider_flags, const struct clk_div_table *table,
462 return _register_divider(dev, name, parent_name, flags, reg, shift,
463 width, clk_divider_flags, table, lock);
465 EXPORT_SYMBOL_GPL(clk_register_divider_table);