4 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
7 #include <linux/clk-provider.h>
9 #include <linux/device.h>
10 #include <linux/of_address.h>
12 static DEFINE_SPINLOCK(clklock);
14 #define MAX_FREQ 33333333
15 #define MIN_FREQ 8000000
23 #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
25 static unsigned long pll_recalc_rate(struct clk_hw *hw,
26 unsigned long parent_rate)
28 struct pll_clock *pll_clock = to_pll_clock(hw);
29 int mul = 1 << (readb(pll_clock->pllcr) & 3);
31 return parent_rate * mul;
34 static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
45 for (i = 0; i < 3; i++)
46 offset[i] = abs(rate - (*prate * (1 << i)));
47 for (i = 0; i < 3; i++)
51 m = (offset[i] < offset[m])?i:m;
53 return *prate * (1 << m);
56 static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
57 unsigned long parent_rate)
62 struct pll_clock *pll_clock = to_pll_clock(hw);
64 pll = ((rate / parent_rate) / 2) & 0x03;
65 spin_lock_irqsave(&clklock, flags);
66 val = readb(pll_clock->sckcr);
68 writeb(val, pll_clock->sckcr);
69 val = readb(pll_clock->pllcr);
72 writeb(val, pll_clock->pllcr);
73 spin_unlock_irqrestore(&clklock, flags);
77 static const struct clk_ops pll_ops = {
78 .recalc_rate = pll_recalc_rate,
79 .round_rate = pll_round_rate,
80 .set_rate = pll_set_rate,
83 static void __init h8s2678_pll_clk_setup(struct device_node *node)
87 const char *clk_name = node->name;
88 const char *parent_name;
89 struct pll_clock *pll_clock;
90 struct clk_init_data init;
92 num_parents = of_clk_get_parent_count(node);
93 if (num_parents < 1) {
94 pr_err("%s: no parent found", clk_name);
99 pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
103 pll_clock->sckcr = of_iomap(node, 0);
104 if (pll_clock->sckcr == NULL) {
105 pr_err("%s: failed to map divide register", clk_name);
109 pll_clock->pllcr = of_iomap(node, 1);
110 if (pll_clock->pllcr == NULL) {
111 pr_err("%s: failed to map multiply register", clk_name);
115 parent_name = of_clk_get_parent_name(node, 0);
116 init.name = clk_name;
118 init.flags = CLK_IS_BASIC;
119 init.parent_names = &parent_name;
120 init.num_parents = 1;
121 pll_clock->hw.init = &init;
123 clk = clk_register(NULL, &pll_clock->hw);
125 pr_err("%s: failed to register %s div clock (%ld)\n",
126 __func__, clk_name, PTR_ERR(clk));
130 of_clk_add_provider(node, of_clk_src_simple_get, clk);
134 iounmap(pll_clock->pllcr);
136 iounmap(pll_clock->sckcr);
141 CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
142 h8s2678_pll_clk_setup);