2 #include <linux/clk-provider.h>
4 #include <linux/slab.h>
5 #include <linux/kernel.h>
13 * @clk_hw clock source
14 * @parent the parent clock name
15 * @base base address of pll registers
17 * PLL clock version 1, found on i.MX1/21/25/27/31/35
21 #define MFN_SIGN (BIT(MFN_BITS - 1))
22 #define MFN_MASK (MFN_SIGN - 1)
27 enum imx_pllv1_type type;
30 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
32 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)
34 return pll->type == IMX_PLLV1_IMX1;
37 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)
39 return pll->type == IMX_PLLV1_IMX21;
42 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)
44 return pll->type == IMX_PLLV1_IMX27;
47 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)
49 return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);
52 static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
53 unsigned long parent_rate)
55 struct clk_pllv1 *pll = to_clk_pllv1(hw);
58 unsigned int mfi, mfn, mfd, pd;
62 reg = readl(pll->base);
65 * Get the resulting clock rate from a PLL register value and the input
66 * frequency. PLLs with this register layout can be found on i.MX1,
67 * i.MX21, i.MX27 and i,MX31
69 * mfi + mfn / (mfd + 1)
70 * f = 2 * f_ref * --------------------
74 mfi = (reg >> 10) & 0xf;
76 mfd = (reg >> 16) & 0x3ff;
77 pd = (reg >> 26) & 0xf;
79 mfi = mfi <= 5 ? 5 : mfi;
84 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
85 * 2's complements number.
86 * On i.MX27 the bit 9 is the sign bit.
88 if (mfn_is_negative(pll, mfn)) {
89 if (is_imx27_pllv1(pll))
90 mfn_abs = mfn & MFN_MASK;
92 mfn_abs = BIT(MFN_BITS) - mfn;
95 rate = parent_rate * 2;
98 ll = (unsigned long long)rate * mfn_abs;
102 if (mfn_is_negative(pll, mfn))
105 ll = (rate * mfi) + ll;
110 static struct clk_ops clk_pllv1_ops = {
111 .recalc_rate = clk_pllv1_recalc_rate,
114 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
115 const char *parent, void __iomem *base)
117 struct clk_pllv1 *pll;
119 struct clk_init_data init;
121 pll = kmalloc(sizeof(*pll), GFP_KERNEL);
123 return ERR_PTR(-ENOMEM);
129 init.ops = &clk_pllv1_ops;
131 init.parent_names = &parent;
132 init.num_parents = 1;
134 pll->hw.init = &init;
136 clk = clk_register(NULL, &pll->hw);