drivers/clk/ingenic/jz4740-cgu.c

   1 /*
   2  * Ingenic JZ4740 SoC CGU driver
   3  *
   4  * Copyright (c) 2015 Imagination Technologies
   5  * Author: Paul Burton <paul.burton@imgtec.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/of.h>
  21 #include <dt-bindings/clock/jz4740-cgu.h>
  22 #include "cgu.h"
  23
  24 /* CGU register offsets */
  25 #define CGU_REG_CPCCR           0x00
  26 #define CGU_REG_CPPCR           0x10
  27 #define CGU_REG_SCR             0x24
  28 #define CGU_REG_I2SCDR          0x60
  29 #define CGU_REG_LPCDR           0x64
  30 #define CGU_REG_MSCCDR          0x68
  31 #define CGU_REG_UHCCDR          0x6c
  32 #define CGU_REG_SSICDR          0x74
  33
  34 /* bits within a PLL control register */
  35 #define PLLCTL_M_SHIFT          23
  36 #define PLLCTL_M_MASK           (0x1ff << PLLCTL_M_SHIFT)
  37 #define PLLCTL_N_SHIFT          18
  38 #define PLLCTL_N_MASK           (0x1f << PLLCTL_N_SHIFT)
  39 #define PLLCTL_OD_SHIFT         16
  40 #define PLLCTL_OD_MASK          (0x3 << PLLCTL_OD_SHIFT)
  41 #define PLLCTL_STABLE           (1 << 10)
  42 #define PLLCTL_BYPASS           (1 << 9)
  43 #define PLLCTL_ENABLE           (1 << 8)
  44
  45 static struct ingenic_cgu *cgu;
  46
  47 static const s8 pll_od_encoding[4] = {
  48         0x0, 0x1, -1, 0x3,
  49 };
  50
  51 static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
  52
  53         /* External clocks */
  54
  55         [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
  56         [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
  57
  58         [JZ4740_CLK_PLL] = {
  59                 "pll", CGU_CLK_PLL,
  60                 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
  61                 .pll = {
  62                         .reg = CGU_REG_CPPCR,
  63                         .m_shift = 23,
  64                         .m_bits = 9,
  65                         .m_offset = 2,
  66                         .n_shift = 18,
  67                         .n_bits = 5,
  68                         .n_offset = 2,
  69                         .od_shift = 16,
  70                         .od_bits = 2,
  71                         .od_max = 4,
  72                         .od_encoding = pll_od_encoding,
  73                         .stable_bit = 10,
  74                         .bypass_bit = 9,
  75                         .enable_bit = 8,
  76                 },
  77         },
  78
  79         /* Muxes & dividers */
  80
  81         [JZ4740_CLK_PLL_HALF] = {
  82                 "pll half", CGU_CLK_DIV,
  83                 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
  84                 .div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 },
  85         },
  86
  87         [JZ4740_CLK_CCLK] = {
  88                 "cclk", CGU_CLK_DIV,
  89                 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
  90                 .div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 },
  91         },
  92
  93         [JZ4740_CLK_HCLK] = {
  94                 "hclk", CGU_CLK_DIV,
  95                 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
  96                 .div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 },
  97         },
  98
  99         [JZ4740_CLK_PCLK] = {
 100                 "pclk", CGU_CLK_DIV,
 101                 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
 102                 .div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 },
 103         },
 104
 105         [JZ4740_CLK_MCLK] = {
 106                 "mclk", CGU_CLK_DIV,
 107                 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
 108                 .div = { CGU_REG_CPCCR, 12, 4, 22, -1, -1 },
 109         },
 110
 111         [JZ4740_CLK_LCD] = {
 112                 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
 113                 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
 114                 .div = { CGU_REG_CPCCR, 16, 5, 22, -1, -1 },
 115                 .gate = { CGU_REG_CLKGR, 10 },
 116         },
 117
 118         [JZ4740_CLK_LCD_PCLK] = {
 119                 "lcd_pclk", CGU_CLK_DIV,
 120                 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
 121                 .div = { CGU_REG_LPCDR, 0, 11, -1, -1, -1 },
 122         },
 123
 124         [JZ4740_CLK_I2S] = {
 125                 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
 126                 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
 127                 .mux = { CGU_REG_CPCCR, 31, 1 },
 128                 .div = { CGU_REG_I2SCDR, 0, 8, -1, -1, -1 },
 129                 .gate = { CGU_REG_CLKGR, 6 },
 130         },
 131
 132         [JZ4740_CLK_SPI] = {
 133                 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
 134                 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
 135                 .mux = { CGU_REG_SSICDR, 31, 1 },
 136                 .div = { CGU_REG_SSICDR, 0, 4, -1, -1, -1 },
 137                 .gate = { CGU_REG_CLKGR, 4 },
 138         },
 139
 140         [JZ4740_CLK_MMC] = {
 141                 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
 142                 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
 143                 .div = { CGU_REG_MSCCDR, 0, 5, -1, -1, -1 },
 144                 .gate = { CGU_REG_CLKGR, 7 },
 145         },
 146
 147         [JZ4740_CLK_UHC] = {
 148                 "uhc", CGU_CLK_DIV | CGU_CLK_GATE,
 149                 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
 150                 .div = { CGU_REG_UHCCDR, 0, 4, -1, -1, -1 },
 151                 .gate = { CGU_REG_CLKGR, 14 },
 152         },
 153
 154         [JZ4740_CLK_UDC] = {
 155                 "udc", CGU_CLK_MUX | CGU_CLK_DIV,
 156                 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
 157                 .mux = { CGU_REG_CPCCR, 29, 1 },
 158                 .div = { CGU_REG_CPCCR, 23, 6, -1, -1, -1 },
 159                 .gate = { CGU_REG_SCR, 6 },
 160         },
 161
 162         /* Gate-only clocks */
 163
 164         [JZ4740_CLK_UART0] = {
 165                 "uart0", CGU_CLK_GATE,
 166                 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
 167                 .gate = { CGU_REG_CLKGR, 0 },
 168         },
 169
 170         [JZ4740_CLK_UART1] = {
 171                 "uart1", CGU_CLK_GATE,
 172                 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
 173                 .gate = { CGU_REG_CLKGR, 15 },
 174         },
 175
 176         [JZ4740_CLK_DMA] = {
 177                 "dma", CGU_CLK_GATE,
 178                 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
 179                 .gate = { CGU_REG_CLKGR, 12 },
 180         },
 181
 182         [JZ4740_CLK_IPU] = {
 183                 "ipu", CGU_CLK_GATE,
 184                 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
 185                 .gate = { CGU_REG_CLKGR, 13 },
 186         },
 187
 188         [JZ4740_CLK_ADC] = {
 189                 "adc", CGU_CLK_GATE,
 190                 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
 191                 .gate = { CGU_REG_CLKGR, 8 },
 192         },
 193
 194         [JZ4740_CLK_I2C] = {
 195                 "i2c", CGU_CLK_GATE,
 196                 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
 197                 .gate = { CGU_REG_CLKGR, 3 },
 198         },
 199
 200         [JZ4740_CLK_AIC] = {
 201                 "aic", CGU_CLK_GATE,
 202                 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
 203                 .gate = { CGU_REG_CLKGR, 5 },
 204         },
 205 };
 206
 207 static void __init jz4740_cgu_init(struct device_node *np)
 208 {
 209         int retval;
 210
 211         cgu = ingenic_cgu_new(jz4740_cgu_clocks,
 212                               ARRAY_SIZE(jz4740_cgu_clocks), np);
 213         if (!cgu) {
 214                 pr_err("%s: failed to initialise CGU\n", __func__);
 215                 return;
 216         }
 217
 218         retval = ingenic_cgu_register_clocks(cgu);
 219         if (retval)
 220                 pr_err("%s: failed to register CGU Clocks\n", __func__);
 221 }
 222 CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);