2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/slab.h>
25 static DEFINE_SPINLOCK(clk_lock);
27 static struct clk **clks;
28 static struct clk_onecell_data clk_data;
30 struct clk ** __init meson_clk_init(struct device_node *np,
31 unsigned long nr_clks)
33 clks = kcalloc(nr_clks, sizeof(*clks), GFP_KERNEL);
35 return ERR_PTR(-ENOMEM);
38 clk_data.clk_num = nr_clks;
39 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
44 static void meson_clk_add_lookup(struct clk *clk, unsigned int id)
50 static struct clk * __init
51 meson_clk_register_composite(const struct clk_conf *clk_conf,
52 void __iomem *clk_base)
55 struct clk_mux *mux = NULL;
56 struct clk_divider *div = NULL;
57 struct clk_gate *gate = NULL;
58 const struct clk_ops *mux_ops = NULL;
59 const struct composite_conf *composite_conf;
61 composite_conf = clk_conf->conf.composite;
63 if (clk_conf->num_parents > 1) {
64 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
66 return ERR_PTR(-ENOMEM);
68 mux->reg = clk_base + clk_conf->reg_off
69 + composite_conf->mux_parm.reg_off;
70 mux->shift = composite_conf->mux_parm.shift;
71 mux->mask = BIT(composite_conf->mux_parm.width) - 1;
72 mux->flags = composite_conf->mux_flags;
73 mux->lock = &clk_lock;
74 mux->table = composite_conf->mux_table;
75 mux_ops = (composite_conf->mux_flags & CLK_MUX_READ_ONLY) ?
76 &clk_mux_ro_ops : &clk_mux_ops;
79 if (MESON_PARM_APPLICABLE(&composite_conf->div_parm)) {
80 div = kzalloc(sizeof(*div), GFP_KERNEL);
82 clk = ERR_PTR(-ENOMEM);
86 div->reg = clk_base + clk_conf->reg_off
87 + composite_conf->div_parm.reg_off;
88 div->shift = composite_conf->div_parm.shift;
89 div->width = composite_conf->div_parm.width;
90 div->lock = &clk_lock;
91 div->flags = composite_conf->div_flags;
92 div->table = composite_conf->div_table;
95 if (MESON_PARM_APPLICABLE(&composite_conf->gate_parm)) {
96 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
98 clk = ERR_PTR(-ENOMEM);
102 gate->reg = clk_base + clk_conf->reg_off
103 + composite_conf->div_parm.reg_off;
104 gate->bit_idx = composite_conf->gate_parm.shift;
105 gate->flags = composite_conf->gate_flags;
106 gate->lock = &clk_lock;
109 clk = clk_register_composite(NULL, clk_conf->clk_name,
110 clk_conf->clks_parent,
111 clk_conf->num_parents,
112 mux ? &mux->hw : NULL, mux_ops,
113 div ? &div->hw : NULL, &clk_divider_ops,
114 gate ? &gate->hw : NULL, &clk_gate_ops,
129 static struct clk * __init
130 meson_clk_register_fixed_factor(const struct clk_conf *clk_conf,
131 void __iomem *clk_base)
134 const struct fixed_fact_conf *fixed_fact_conf;
135 const struct parm *p;
136 unsigned int mult, div;
139 fixed_fact_conf = &clk_conf->conf.fixed_fact;
141 mult = clk_conf->conf.fixed_fact.mult;
142 div = clk_conf->conf.fixed_fact.div;
146 p = &fixed_fact_conf->mult_parm;
147 if (MESON_PARM_APPLICABLE(p)) {
148 reg = readl(clk_base + clk_conf->reg_off + p->reg_off);
149 mult = PARM_GET(p->width, p->shift, reg);
155 p = &fixed_fact_conf->div_parm;
156 if (MESON_PARM_APPLICABLE(p)) {
157 reg = readl(clk_base + clk_conf->reg_off + p->reg_off);
158 mult = PARM_GET(p->width, p->shift, reg);
162 clk = clk_register_fixed_factor(NULL,
164 clk_conf->clks_parent[0],
171 static struct clk * __init
172 meson_clk_register_fixed_rate(const struct clk_conf *clk_conf,
173 void __iomem *clk_base)
176 const struct fixed_rate_conf *fixed_rate_conf;
177 const struct parm *r;
181 fixed_rate_conf = &clk_conf->conf.fixed_rate;
182 rate = fixed_rate_conf->rate;
185 r = &fixed_rate_conf->rate_parm;
186 reg = readl(clk_base + clk_conf->reg_off + r->reg_off);
187 rate = PARM_GET(r->width, r->shift, reg);
192 clk = clk_register_fixed_rate(NULL,
194 clk_conf->num_parents
195 ? clk_conf->clks_parent[0] : NULL,
196 clk_conf->flags, rate);
201 void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
203 void __iomem *clk_base)
206 struct clk *clk = NULL;
208 for (i = 0; i < nr_confs; i++) {
209 const struct clk_conf *clk_conf = &clk_confs[i];
211 switch (clk_conf->clk_type) {
213 clk = meson_clk_register_fixed_rate(clk_conf,
216 case CLK_FIXED_FACTOR:
217 clk = meson_clk_register_fixed_factor(clk_conf,
221 clk = meson_clk_register_composite(clk_conf,
225 clk = meson_clk_register_cpu(clk_conf, clk_base,
229 clk = meson_clk_register_pll(clk_conf, clk_base,
237 pr_err("%s: unknown clock type %d\n", __func__,
243 pr_warn("%s: Unable to create %s clock\n", __func__,
248 meson_clk_add_lookup(clk, clk_conf->clk_id);