2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #define PMASK(width) GENMASK(width - 1, 0)
22 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
23 #define CLRPMASK(width, shift) (~SETPMASK(width, shift))
25 #define PARM_GET(width, shift, reg) \
26 (((reg) & SETPMASK(width, shift)) >> (shift))
27 #define PARM_SET(width, shift, reg, val) \
28 (((reg) & CLRPMASK(width, shift)) | (val << (shift)))
30 #define MESON_PARM_APPLICABLE(p) (!!((p)->width))
37 #define PARM(_r, _s, _w) \
44 struct pll_rate_table {
50 #define PLL_RATE(_r, _m, _n, _od) \
59 const struct pll_rate_table *rate_table;
65 struct fixed_fact_conf {
69 struct parm mult_parm;
72 struct fixed_rate_conf {
74 struct parm rate_parm;
77 struct composite_conf {
80 struct parm gate_parm;
81 struct clk_div_table *div_table;
88 #define PNAME(x) static const char *x[]
100 enum clk_type clk_type;
102 const char *clk_name;
103 const char **clks_parent;
107 struct fixed_fact_conf fixed_fact;
108 struct fixed_rate_conf fixed_rate;
109 const struct composite_conf *composite;
110 struct pll_conf *pll;
111 const struct clk_div_table *div_table;
115 #define FIXED_RATE_P(_ro, _ci, _cn, _f, _c) \
118 .clk_type = CLK_FIXED_RATE, \
122 .conf.fixed_rate.rate_parm = _c, \
125 #define FIXED_RATE(_ci, _cn, _f, _r) \
127 .clk_type = CLK_FIXED_RATE, \
131 .conf.fixed_rate.rate = (_r), \
134 #define PLL(_ro, _ci, _cn, _cp, _f, _c) \
137 .clk_type = CLK_PLL, \
140 .clks_parent = (_cp), \
141 .num_parents = ARRAY_SIZE(_cp), \
146 #define FIXED_FACTOR_DIV(_ci, _cn, _cp, _f, _d) \
148 .clk_type = CLK_FIXED_FACTOR, \
151 .clks_parent = (_cp), \
152 .num_parents = ARRAY_SIZE(_cp), \
153 .conf.fixed_fact.div = (_d), \
156 #define CPU(_ro, _ci, _cn, _cp, _dt) \
159 .clk_type = CLK_CPU, \
162 .clks_parent = (_cp), \
163 .num_parents = ARRAY_SIZE(_cp), \
164 .conf.div_table = (_dt), \
167 #define COMPOSITE(_ro, _ci, _cn, _cp, _f, _c) \
170 .clk_type = CLK_COMPOSITE, \
173 .clks_parent = (_cp), \
174 .num_parents = ARRAY_SIZE(_cp), \
176 .conf.composite = (_c), \
179 struct clk **meson_clk_init(struct device_node *np, unsigned long nr_clks);
180 void meson_clk_register_clks(const struct clk_conf *clk_confs,
181 unsigned int nr_confs, void __iomem *clk_base);
182 struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
183 void __iomem *reg_base, spinlock_t *lock);
184 struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
185 void __iomem *reg_base, spinlock_t *lock);
187 #endif /* __CLKC_H */