clk: mmp: Fix the wrong factor table for uart PLL
[firefly-linux-kernel-4.4.55.git] / drivers / clk / mmp / clk-of-pxa168.c
1 /*
2  * pxa168 clock framework source file
3  *
4  * Copyright (C) 2012 Marvell
5  * Chao Xie <xiechao.mail@gmail.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/of_address.h>
19
20 #include <dt-bindings/clock/marvell,pxa168.h>
21
22 #include "clk.h"
23 #include "reset.h"
24
25 #define APBC_RTC        0x28
26 #define APBC_TWSI0      0x2c
27 #define APBC_KPC        0x30
28 #define APBC_UART0      0x0
29 #define APBC_UART1      0x4
30 #define APBC_GPIO       0x8
31 #define APBC_PWM0       0xc
32 #define APBC_PWM1       0x10
33 #define APBC_PWM2       0x14
34 #define APBC_PWM3       0x18
35 #define APBC_SSP0       0x81c
36 #define APBC_SSP1       0x820
37 #define APBC_SSP2       0x84c
38 #define APBC_SSP3       0x858
39 #define APBC_SSP4       0x85c
40 #define APBC_TWSI1      0x6c
41 #define APBC_UART2      0x70
42 #define APMU_SDH0       0x54
43 #define APMU_SDH1       0x58
44 #define APMU_USB        0x5c
45 #define APMU_DISP0      0x4c
46 #define APMU_CCIC0      0x50
47 #define APMU_DFC        0x60
48 #define MPMU_UART_PLL   0x14
49
50 struct pxa168_clk_unit {
51         struct mmp_clk_unit unit;
52         void __iomem *mpmu_base;
53         void __iomem *apmu_base;
54         void __iomem *apbc_base;
55 };
56
57 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
58         {PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
59         {PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
60         {PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
61         {PXA168_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
62 };
63
64 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
65         {PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
66         {PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
67         {PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
68         {PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
69         {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
70         {PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
71         {PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
72         {PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
73         {PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
74         {PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
75         {PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
76         {PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
77         {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
78 };
79
80 static struct mmp_clk_factor_masks uart_factor_masks = {
81         .factor = 2,
82         .num_mask = 0x1fff,
83         .den_mask = 0x1fff,
84         .num_shift = 16,
85         .den_shift = 0,
86 };
87
88 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
89         {.num = 8125, .den = 1536},     /*14.745MHZ */
90 };
91
92 static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
93 {
94         struct clk *clk;
95         struct mmp_clk_unit *unit = &pxa_unit->unit;
96
97         mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
98                                         ARRAY_SIZE(fixed_rate_clks));
99
100         mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
101                                         ARRAY_SIZE(fixed_factor_clks));
102
103         clk = mmp_clk_register_factor("uart_pll", "pll1_4",
104                                 CLK_SET_RATE_PARENT,
105                                 pxa_unit->mpmu_base + MPMU_UART_PLL,
106                                 &uart_factor_masks, uart_factor_tbl,
107                                 ARRAY_SIZE(uart_factor_tbl), NULL);
108         mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
109 }
110
111 static DEFINE_SPINLOCK(uart0_lock);
112 static DEFINE_SPINLOCK(uart1_lock);
113 static DEFINE_SPINLOCK(uart2_lock);
114 static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
115
116 static DEFINE_SPINLOCK(ssp0_lock);
117 static DEFINE_SPINLOCK(ssp1_lock);
118 static DEFINE_SPINLOCK(ssp2_lock);
119 static DEFINE_SPINLOCK(ssp3_lock);
120 static DEFINE_SPINLOCK(ssp4_lock);
121 static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
122
123 static DEFINE_SPINLOCK(reset_lock);
124
125 static struct mmp_param_mux_clk apbc_mux_clks[] = {
126         {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
127         {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
128         {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
129         {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
130         {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
131         {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
132         {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
133         {0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
134 };
135
136 static struct mmp_param_gate_clk apbc_gate_clks[] = {
137         {PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
138         {PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
139         {PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
140         {PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
141         {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
142         {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
143         {PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
144         {PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
145         {PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
146         /* The gate clocks has mux parent. */
147         {PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
148         {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
149         {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
150         {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
151         {PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
152         {PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
153         {PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
154         {PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
155 };
156
157 static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
158 {
159         struct mmp_clk_unit *unit = &pxa_unit->unit;
160
161         mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
162                                 ARRAY_SIZE(apbc_mux_clks));
163
164         mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
165                                 ARRAY_SIZE(apbc_gate_clks));
166
167 }
168
169 static DEFINE_SPINLOCK(sdh0_lock);
170 static DEFINE_SPINLOCK(sdh1_lock);
171 static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
172
173 static DEFINE_SPINLOCK(usb_lock);
174
175 static DEFINE_SPINLOCK(disp0_lock);
176 static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
177
178 static DEFINE_SPINLOCK(ccic0_lock);
179 static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
180 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
181
182 static struct mmp_param_mux_clk apmu_mux_clks[] = {
183         {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
184         {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
185         {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
186         {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
187         {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
188 };
189
190 static struct mmp_param_div_clk apmu_div_clks[] = {
191         {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
192 };
193
194 static struct mmp_param_gate_clk apmu_gate_clks[] = {
195         {PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
196         {PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
197         {PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
198         /* The gate clocks has mux parent. */
199         {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
200         {PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
201         {PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
202         {PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
203         {PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
204         {PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
205 };
206
207 static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
208 {
209         struct mmp_clk_unit *unit = &pxa_unit->unit;
210
211         mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
212                                 ARRAY_SIZE(apmu_mux_clks));
213
214         mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
215                                 ARRAY_SIZE(apmu_div_clks));
216
217         mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
218                                 ARRAY_SIZE(apmu_gate_clks));
219 }
220
221 static void pxa168_clk_reset_init(struct device_node *np,
222                                 struct pxa168_clk_unit *pxa_unit)
223 {
224         struct mmp_clk_reset_cell *cells;
225         int i, nr_resets;
226
227         nr_resets = ARRAY_SIZE(apbc_gate_clks);
228         cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
229         if (!cells)
230                 return;
231
232         for (i = 0; i < nr_resets; i++) {
233                 cells[i].clk_id = apbc_gate_clks[i].id;
234                 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
235                 cells[i].flags = 0;
236                 cells[i].lock = apbc_gate_clks[i].lock;
237                 cells[i].bits = 0x4;
238         }
239
240         mmp_clk_reset_register(np, cells, nr_resets);
241 }
242
243 static void __init pxa168_clk_init(struct device_node *np)
244 {
245         struct pxa168_clk_unit *pxa_unit;
246
247         pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
248         if (!pxa_unit)
249                 return;
250
251         pxa_unit->mpmu_base = of_iomap(np, 0);
252         if (!pxa_unit->mpmu_base) {
253                 pr_err("failed to map mpmu registers\n");
254                 return;
255         }
256
257         pxa_unit->apmu_base = of_iomap(np, 1);
258         if (!pxa_unit->mpmu_base) {
259                 pr_err("failed to map apmu registers\n");
260                 return;
261         }
262
263         pxa_unit->apbc_base = of_iomap(np, 2);
264         if (!pxa_unit->apbc_base) {
265                 pr_err("failed to map apbc registers\n");
266                 return;
267         }
268
269         mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
270
271         pxa168_pll_init(pxa_unit);
272
273         pxa168_apb_periph_clk_init(pxa_unit);
274
275         pxa168_axi_periph_clk_init(pxa_unit);
276
277         pxa168_clk_reset_init(np, pxa_unit);
278 }
279
280 CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);