1 #ifndef __MACH_MMP_CLK_H
2 #define __MACH_MMP_CLK_H
4 #include <linux/clk-provider.h>
5 #include <linux/clkdev.h>
7 #define APBC_NO_BUS_CTRL BIT(0)
8 #define APBC_POWER_CTRL BIT(1)
11 /* Clock type "factor" */
12 struct mmp_clk_factor_masks {
14 unsigned int num_mask;
15 unsigned int den_mask;
16 unsigned int num_shift;
17 unsigned int den_shift;
20 struct mmp_clk_factor_tbl {
25 struct mmp_clk_factor {
28 struct mmp_clk_factor_masks *masks;
29 struct mmp_clk_factor_tbl *ftbl;
30 unsigned int ftbl_cnt;
34 extern struct clk *mmp_clk_register_factor(const char *name,
35 const char *parent_name, unsigned long flags,
36 void __iomem *base, struct mmp_clk_factor_masks *masks,
37 struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
40 /* Clock type "mix" */
41 #define MMP_CLK_BITS_MASK(width, shift) \
42 (((1 << (width)) - 1) << (shift))
43 #define MMP_CLK_BITS_GET_VAL(data, width, shift) \
44 ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
45 #define MMP_CLK_BITS_SET_VAL(val, width, shift) \
46 (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
54 /* The register layout */
55 struct mmp_clk_mix_reg_info {
56 void __iomem *reg_clk_ctrl;
57 void __iomem *reg_clk_sel;
65 /* The suggested clock table from user. */
66 struct mmp_clk_mix_clk_table {
73 struct mmp_clk_mix_config {
74 struct mmp_clk_mix_reg_info reg_info;
75 struct mmp_clk_mix_clk_table *table;
76 unsigned int table_size;
78 struct clk_div_table *div_table;
85 struct mmp_clk_mix_reg_info reg_info;
86 struct mmp_clk_mix_clk_table *table;
88 struct clk_div_table *div_table;
89 unsigned int table_size;
96 extern const struct clk_ops mmp_clk_mix_ops;
97 extern struct clk *mmp_clk_register_mix(struct device *dev,
99 const char **parent_names,
102 struct mmp_clk_mix_config *config,
106 /* Clock type "gate". MMP private gate */
107 #define MMP_CLK_GATE_NEED_DELAY BIT(0)
109 struct mmp_clk_gate {
119 extern const struct clk_ops mmp_clk_gate_ops;
120 extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
121 const char *parent_name, unsigned long flags,
122 void __iomem *reg, u32 mask, u32 val_enable,
123 u32 val_disable, unsigned int gate_flags,
127 extern struct clk *mmp_clk_register_pll2(const char *name,
128 const char *parent_name, unsigned long flags);
129 extern struct clk *mmp_clk_register_apbc(const char *name,
130 const char *parent_name, void __iomem *base,
131 unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
132 extern struct clk *mmp_clk_register_apmu(const char *name,
133 const char *parent_name, void __iomem *base, u32 enable_mask,
136 struct mmp_clk_unit {
137 unsigned int nr_clks;
138 struct clk **clk_table;
139 struct clk_onecell_data clk_data;
142 struct mmp_param_fixed_rate_clk {
145 const char *parent_name;
147 unsigned long fixed_rate;
149 void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
150 struct mmp_param_fixed_rate_clk *clks,
153 struct mmp_param_fixed_factor_clk {
156 const char *parent_name;
161 void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
162 struct mmp_param_fixed_factor_clk *clks,
165 struct mmp_param_general_gate_clk {
168 const char *parent_name;
170 unsigned long offset;
175 void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
176 struct mmp_param_general_gate_clk *clks,
177 void __iomem *base, int size);
179 struct mmp_param_gate_clk {
182 const char *parent_name;
184 unsigned long offset;
188 unsigned int gate_flags;
191 void mmp_register_gate_clks(struct mmp_clk_unit *unit,
192 struct mmp_param_gate_clk *clks,
193 void __iomem *base, int size);
195 struct mmp_param_mux_clk {
198 const char **parent_name;
201 unsigned long offset;
207 void mmp_register_mux_clks(struct mmp_clk_unit *unit,
208 struct mmp_param_mux_clk *clks,
209 void __iomem *base, int size);
211 struct mmp_param_div_clk {
214 const char *parent_name;
216 unsigned long offset;
222 void mmp_register_div_clks(struct mmp_clk_unit *unit,
223 struct mmp_param_div_clk *clks,
224 void __iomem *base, int size);
226 #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
228 .width_div = (w_d), \
229 .shift_div = (s_d), \
230 .width_mux = (w_m), \
231 .shift_mux = (s_m), \
235 void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
237 void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,