2 * Marvell MVEBU CPU clock handling.
4 * Copyright (C) 2012 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 #include <linux/kernel.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
18 #include <linux/delay.h>
20 #define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
21 #define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
22 #define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
29 const char *parent_name;
30 void __iomem *reg_base;
33 static struct clk **clks;
35 static struct clk_onecell_data clk_data;
37 #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
39 static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
40 unsigned long parent_rate)
42 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
45 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
46 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
47 return parent_rate / div;
50 static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
51 unsigned long *parent_rate)
53 /* Valid ratio are 1:1, 1:2 and 1:3 */
56 div = *parent_rate / rate;
62 return *parent_rate / div;
65 static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
66 unsigned long parent_rate)
68 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
72 div = parent_rate / rate;
73 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
74 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
75 | (div << (cpuclk->cpu * 8));
76 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
77 /* Set clock divider reload smooth bit mask */
78 reload_mask = 1 << (20 + cpuclk->cpu);
80 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
82 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
84 /* Now trigger the clock update */
85 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
87 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
89 /* Wait for clocks to settle down then clear reload request */
91 reg &= ~(reload_mask | 1 << 24);
92 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
98 static const struct clk_ops cpu_ops = {
99 .recalc_rate = clk_cpu_recalc_rate,
100 .round_rate = clk_cpu_round_rate,
101 .set_rate = clk_cpu_set_rate,
104 void __init of_cpu_clk_setup(struct device_node *node)
106 struct cpu_clk *cpuclk;
107 void __iomem *clock_complex_base = of_iomap(node, 0);
109 struct device_node *dn;
111 if (clock_complex_base == NULL) {
112 pr_err("%s: clock-complex base register not set\n",
117 for_each_node_by_type(dn, "cpu")
120 cpuclk = kzalloc(ncpus * sizeof(*cpuclk), GFP_KERNEL);
121 if (WARN_ON(!cpuclk))
124 clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL);
128 for_each_node_by_type(dn, "cpu") {
129 struct clk_init_data init;
131 struct clk *parent_clk;
132 char *clk_name = kzalloc(5, GFP_KERNEL);
135 if (WARN_ON(!clk_name))
138 err = of_property_read_u32(dn, "reg", &cpu);
142 sprintf(clk_name, "cpu%d", cpu);
143 parent_clk = of_clk_get(node, 0);
145 cpuclk[cpu].parent_name = __clk_get_name(parent_clk);
146 cpuclk[cpu].clk_name = clk_name;
147 cpuclk[cpu].cpu = cpu;
148 cpuclk[cpu].reg_base = clock_complex_base;
149 cpuclk[cpu].hw.init = &init;
151 init.name = cpuclk[cpu].clk_name;
154 init.parent_names = &cpuclk[cpu].parent_name;
155 init.num_parents = 1;
157 clk = clk_register(NULL, &cpuclk[cpu].hw);
158 if (WARN_ON(IS_ERR(clk)))
162 clk_data.clk_num = MAX_CPU;
163 clk_data.clks = clks;
164 of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
170 kfree(cpuclk[ncpus].clk_name);
175 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",