2 * Marvell MVEBU CPU clock handling.
4 * Copyright (C) 2012 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 #include <linux/kernel.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
18 #include <linux/delay.h>
21 #define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
22 #define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
23 #define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
30 const char *parent_name;
31 void __iomem *reg_base;
34 static struct clk **clks;
36 static struct clk_onecell_data clk_data;
38 #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
40 static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
41 unsigned long parent_rate)
43 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
46 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
47 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
48 return parent_rate / div;
51 static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
52 unsigned long *parent_rate)
54 /* Valid ratio are 1:1, 1:2 and 1:3 */
57 div = *parent_rate / rate;
63 return *parent_rate / div;
66 static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
67 unsigned long parent_rate)
69 struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
73 div = parent_rate / rate;
74 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
75 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
76 | (div << (cpuclk->cpu * 8));
77 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
78 /* Set clock divider reload smooth bit mask */
79 reload_mask = 1 << (20 + cpuclk->cpu);
81 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
83 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
85 /* Now trigger the clock update */
86 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
88 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
90 /* Wait for clocks to settle down then clear reload request */
92 reg &= ~(reload_mask | 1 << 24);
93 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
99 static const struct clk_ops cpu_ops = {
100 .recalc_rate = clk_cpu_recalc_rate,
101 .round_rate = clk_cpu_round_rate,
102 .set_rate = clk_cpu_set_rate,
105 void __init of_cpu_clk_setup(struct device_node *node)
107 struct cpu_clk *cpuclk;
108 void __iomem *clock_complex_base = of_iomap(node, 0);
110 struct device_node *dn;
112 if (clock_complex_base == NULL) {
113 pr_err("%s: clock-complex base register not set\n",
118 for_each_node_by_type(dn, "cpu")
121 cpuclk = kzalloc(ncpus * sizeof(*cpuclk), GFP_KERNEL);
122 if (WARN_ON(!cpuclk))
125 clks = kzalloc(ncpus * sizeof(*clks), GFP_KERNEL);
129 for_each_node_by_type(dn, "cpu") {
130 struct clk_init_data init;
132 struct clk *parent_clk;
133 char *clk_name = kzalloc(5, GFP_KERNEL);
136 if (WARN_ON(!clk_name))
139 err = of_property_read_u32(dn, "reg", &cpu);
143 sprintf(clk_name, "cpu%d", cpu);
144 parent_clk = of_clk_get(node, 0);
146 cpuclk[cpu].parent_name = __clk_get_name(parent_clk);
147 cpuclk[cpu].clk_name = clk_name;
148 cpuclk[cpu].cpu = cpu;
149 cpuclk[cpu].reg_base = clock_complex_base;
150 cpuclk[cpu].hw.init = &init;
152 init.name = cpuclk[cpu].clk_name;
155 init.parent_names = &cpuclk[cpu].parent_name;
156 init.num_parents = 1;
158 clk = clk_register(NULL, &cpuclk[cpu].hw);
159 if (WARN_ON(IS_ERR(clk)))
163 clk_data.clk_num = MAX_CPU;
164 clk_data.clks = clks;
165 of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
173 static const __initconst struct of_device_id clk_cpu_match[] = {
175 .compatible = "marvell,armada-xp-cpu-clock",
176 .data = of_cpu_clk_setup,
183 void __init mvebu_cpu_clk_init(void)
185 of_clk_init(clk_cpu_match);