2 * Marvell EBU SoC common clock handling
4 * Copyright (C) 2012 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #ifndef __CLK_MVEBU_COMMON_H_
16 #define __CLK_MVEBU_COMMON_H_
18 #include <linux/kernel.h>
22 struct coreclk_ratio {
27 struct coreclk_soc_desc {
28 u32 (*get_tclk_freq)(void __iomem *sar);
29 u32 (*get_cpu_freq)(void __iomem *sar);
30 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
31 bool (*is_sscg_enabled)(void __iomem *sar);
32 u32 (*fix_sscg_deviation)(u32 system_clk);
33 const struct coreclk_ratio *ratios;
37 struct clk_gating_soc_desc {
44 void __init mvebu_coreclk_setup(struct device_node *np,
45 const struct coreclk_soc_desc *desc);
47 void __init mvebu_clk_gating_setup(struct device_node *np,
48 const struct clk_gating_soc_desc *desc);
51 * This function is shared among the Kirkwood, Armada 370, Armada XP
54 u32 kirkwood_fix_sscg_deviation(u32 system_clk);