2 * Marvell Orion SoC clocks
4 * Copyright (C) 2014 Thomas Petazzoni
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/clk-provider.h>
19 static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
20 { .id = 0, .name = "ddrclk", }
27 #define SAR_MV88F5182_TCLK_FREQ 8
28 #define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
30 static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
32 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
33 SAR_MV88F5182_TCLK_FREQ_MASK;
42 #define SAR_MV88F5182_CPU_FREQ 4
43 #define SAR_MV88F5182_CPU_FREQ_MASK 0xf
45 static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
47 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
48 SAR_MV88F5182_CPU_FREQ_MASK;
51 else if (opt == 1 || opt == 2)
59 static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
62 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
63 SAR_MV88F5182_CPU_FREQ_MASK;
64 if (opt == 0 || opt == 1) {
67 } else if (opt == 2 || opt == 3) {
76 static const struct coreclk_soc_desc mv88f5182_coreclks = {
77 .get_tclk_freq = mv88f5182_get_tclk_freq,
78 .get_cpu_freq = mv88f5182_get_cpu_freq,
79 .get_clk_ratio = mv88f5182_get_clk_ratio,
80 .ratios = orion_coreclk_ratios,
81 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
84 static void __init mv88f5182_clk_init(struct device_node *np)
86 return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
89 CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
95 static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
97 /* On 5281, tclk is always 166 Mhz */
101 #define SAR_MV88F5281_CPU_FREQ 4
102 #define SAR_MV88F5281_CPU_FREQ_MASK 0xf
104 static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
106 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
107 SAR_MV88F5281_CPU_FREQ_MASK;
108 if (opt == 1 || opt == 2)
116 static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
119 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
120 SAR_MV88F5281_CPU_FREQ_MASK;
124 } else if (opt == 2 || opt == 3) {
133 static const struct coreclk_soc_desc mv88f5281_coreclks = {
134 .get_tclk_freq = mv88f5281_get_tclk_freq,
135 .get_cpu_freq = mv88f5281_get_cpu_freq,
136 .get_clk_ratio = mv88f5281_get_clk_ratio,
137 .ratios = orion_coreclk_ratios,
138 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
141 static void __init mv88f5281_clk_init(struct device_node *np)
143 return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
146 CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
152 #define SAR_MV88F6183_TCLK_FREQ 9
153 #define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
155 static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
157 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
158 SAR_MV88F6183_TCLK_FREQ_MASK;
167 #define SAR_MV88F6183_CPU_FREQ 1
168 #define SAR_MV88F6183_CPU_FREQ_MASK 0x3f
170 static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
172 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
173 SAR_MV88F6183_CPU_FREQ_MASK;
182 static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
185 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
186 SAR_MV88F6183_CPU_FREQ_MASK;
187 if (opt == 9 || opt == 17) {
196 static const struct coreclk_soc_desc mv88f6183_coreclks = {
197 .get_tclk_freq = mv88f6183_get_tclk_freq,
198 .get_cpu_freq = mv88f6183_get_cpu_freq,
199 .get_clk_ratio = mv88f6183_get_clk_ratio,
200 .ratios = orion_coreclk_ratios,
201 .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
205 static void __init mv88f6183_clk_init(struct device_node *np)
207 return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
210 CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);